+publisher:"NSYSU" +contributor:("Shiann-Rong Kuang")

NSYSU

1. Chou, Yu-chieh. On the Design and Implementation of Load Balancing for CDPthread-based Systems.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902109-212626

► In this thesis, we first propose a modified version of the CDPthread to eliminate the restriction on the number of execution engines supportedâby dynamically instead… (more)

Subjects/Keywords: Distributed shared memory; Load balancing; CDPthread

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chou, Y. (2009). On the Design and Implementation of Load Balancing for CDPthread-based Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902109-212626

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chou, Yu-chieh. “On the Design and Implementation of Load Balancing for CDPthread-based Systems.” 2009. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902109-212626.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chou, Yu-chieh. “On the Design and Implementation of Load Balancing for CDPthread-based Systems.” 2009. Web. 18 Feb 2020.

Vancouver:

Chou Y. On the Design and Implementation of Load Balancing for CDPthread-based Systems. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902109-212626.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chou Y. On the Design and Implementation of Load Balancing for CDPthread-based Systems. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902109-212626

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

2. Lin, Chieh-Wei. Software Implementation of Topology-based Communication Library.

Degree: Master, Electrical Engineering, 2013, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0530113-200455

► Along with the rapid development of Internet and computer technology, distributed and parallel computing is prevalently applied in many applications to enhance performance with parallel… (more)

Subjects/Keywords: parallel computing; topology; communication interconnection design; communication library; distributed computing systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lin, C. (2013). Software Implementation of Topology-based Communication Library. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0530113-200455

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lin, Chieh-Wei. “Software Implementation of Topology-based Communication Library.” 2013. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0530113-200455.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lin, Chieh-Wei. “Software Implementation of Topology-based Communication Library.” 2013. Web. 18 Feb 2020.

Vancouver:

Lin C. Software Implementation of Topology-based Communication Library. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0530113-200455.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin C. Software Implementation of Topology-based Communication Library. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0530113-200455

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

3. Chen, Yu-ying. Software Implementation of a Data Model Design.

Degree: Master, Electrical Engineering, 2014, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-142048

► In software engineering, data models represent data at the high and abstract level. In software designs, data models can be designed and transformed into data… (more)

Subjects/Keywords: data model; entity-relationship model; model-driven architecture; software engineering; data access model

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APA (6^th Edition):

Chen, Y. (2014). Software Implementation of a Data Model Design. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-142048

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chen, Yu-ying. “Software Implementation of a Data Model Design.” 2014. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-142048.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chen, Yu-ying. “Software Implementation of a Data Model Design.” 2014. Web. 18 Feb 2020.

Vancouver:

Chen Y. Software Implementation of a Data Model Design. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-142048.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Y. Software Implementation of a Data Model Design. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-142048

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

4. Weng, Chia-Yang. Design Optimization of Hardware Function Evaluation Units with Truncated Multipliers and Squarers.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629117-231250

► Function evaluation is an important operation in the design of special function unit in graphics processing unit (GPU) and other applications in stereo vision and… (more)

Subjects/Keywords: function evaluation; polynomial approximation; uniform segmentation; digital arithmetic; truncated multiplier; truncated squarer

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Weng, C. (2017). Design Optimization of Hardware Function Evaluation Units with Truncated Multipliers and Squarers. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629117-231250

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Weng, Chia-Yang. “Design Optimization of Hardware Function Evaluation Units with Truncated Multipliers and Squarers.” 2017. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629117-231250.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Weng, Chia-Yang. “Design Optimization of Hardware Function Evaluation Units with Truncated Multipliers and Squarers.” 2017. Web. 18 Feb 2020.

Vancouver:

Weng C. Design Optimization of Hardware Function Evaluation Units with Truncated Multipliers and Squarers. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629117-231250.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Weng C. Design Optimization of Hardware Function Evaluation Units with Truncated Multipliers and Squarers. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629117-231250

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

5. Hsiao, Bo-chien. FPGA Implementations of Real Time 3D Stereo Matching Based on Dynamic Programming.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0722117-115932

► Stereo vision is widely used in many computer vision applications including games, autonomous driving, object recognition, etc. Depth is the key information in stereo vision.… (more)

Subjects/Keywords: image rectification; dynamic programming; depth map; stereo matching; FPGA; stereo vision

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Hsiao, B. (2017). FPGA Implementations of Real Time 3D Stereo Matching Based on Dynamic Programming. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0722117-115932

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hsiao, Bo-chien. “FPGA Implementations of Real Time 3D Stereo Matching Based on Dynamic Programming.” 2017. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0722117-115932.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hsiao, Bo-chien. “FPGA Implementations of Real Time 3D Stereo Matching Based on Dynamic Programming.” 2017. Web. 18 Feb 2020.

Vancouver:

Hsiao B. FPGA Implementations of Real Time 3D Stereo Matching Based on Dynamic Programming. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0722117-115932.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsiao B. FPGA Implementations of Real Time 3D Stereo Matching Based on Dynamic Programming. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0722117-115932

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

6. Chao, Chih-Hsun. The performance evaluation of MPI program running at Kernel Distributed Computing Management.

Degree: Master, Electrical Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724117-182652

► In order to meet the operational requirements of cloud computing, how to improve the performance of parallel applications on a cloud platform is a hot… (more)

▼ In order to meet the operational requirements of cloud computing, how to improve the performance of parallel applications on a cloud platform is a hot topic. There are two types of applications running on the cloud platform: computation-intensive and communication-intensive. In running a computation-intensive program, the difference in performance of hardware between nodes can affect the parallelism of the work; and in the communication-intensive program, the communication speed within tasks can affect the efficiency of data exchange. To optimize communication, tasks that exchange lots of data should be mapped to processing units that have a high network performance. This technique is called communication-aware task mapping. In this paper, we explore the communication-aware task mapping as the starting point to reduce the communication latency as the goal. Because the speed of the Internet is full of uncertainty, and it is impractical to actually analyze the underlying network topology and hardware performance, so we propose a method to implement task mapping based on building a cloud connection type. The user can dispatch the cloud computing resources as the separated way to collect processes with high data communication rates at the same node. Finally, we also define the load status of different node according to the heterogeneity of node. In order to analyze the complex communication within tasks effectively and allocate computing resources more easily, we adopt MPI Kernel Cluster on Kernel Distributed Computing Management, proposed by Chiu and Guo. By its ability to analyze and dispatch tasks, and we improved MPIKC's Communication System to build a communication channel that is sufficient to handle complex data transfer topology. As MPIKC and KDCM fit tightly, they provide the feasibility of the program to be designed in a pipeline and significantly optimize the performance of communication-intensive types of programs. At the end, we experimented with two communication-intensive programs, respectively, training Neural Network and Advanced Encryption Standard encryption program. We compare the running time of the process under various distribution conditions and the results show that the method of our purpose can save up to 12 times running time. We confirm that our purpose can effectively reduce the running time of parallel program. Advisors/Committee Members: Yu-Liang Chou (chair), Rong%20Kuang%22%29&pagesize-30">Shiann-Rong Kuang (chair), JIh-ching Chiu (committee member), Tong-Yu Hsieh (chair).

Subjects/Keywords: Cloud Computing; parallel program; Kernel Driver; MPI; Task mapping; Communication-Intensive

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chao, C. (2017). The performance evaluation of MPI program running at Kernel Distributed Computing Management. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724117-182652

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chao, Chih-Hsun. “The performance evaluation of MPI program running at Kernel Distributed Computing Management.” 2017. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724117-182652.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chao, Chih-Hsun. “The performance evaluation of MPI program running at Kernel Distributed Computing Management.” 2017. Web. 18 Feb 2020.

Vancouver:

Chao C. The performance evaluation of MPI program running at Kernel Distributed Computing Management. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724117-182652.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chao C. The performance evaluation of MPI program running at Kernel Distributed Computing Management. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724117-182652

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

7. Liang, Hsiang-Hao. Design of Low-Power and Dynamically Reconfigurable Multi-Precision Special Function Units.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-224433

► Computation of special functions is widely used in many applications such as stereo vision, image processing, and communication. Piecewise polynomial approximation (PPA) is usually adopted… (more)

Subjects/Keywords: polynomial approximation; multi-precision; special function unit; digital arithmetic; function evaluation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Liang, H. (2017). Design of Low-Power and Dynamically Reconfigurable Multi-Precision Special Function Units. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-224433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Liang, Hsiang-Hao. “Design of Low-Power and Dynamically Reconfigurable Multi-Precision Special Function Units.” 2017. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-224433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Liang, Hsiang-Hao. “Design of Low-Power and Dynamically Reconfigurable Multi-Precision Special Function Units.” 2017. Web. 18 Feb 2020.

Vancouver:

Liang H. Design of Low-Power and Dynamically Reconfigurable Multi-Precision Special Function Units. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-224433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liang H. Design of Low-Power and Dynamically Reconfigurable Multi-Precision Special Function Units. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-224433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

8. Chao, Shu-jung. Improving ILP with Semantic-Based Loop Unrolling Mechanism in the Hyperscalar Architecture.

Degree: Master, Electrical Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724117-184404

► In an age of multi-core computing architecture, exploiting ILP of loops can enhance the computing efficiency in the multi-core computing architecture since loop structure is… (more)

▼ In an age of multi-core computing architecture, exploiting ILP of loops can enhance the computing efficiency in the multi-core computing architecture since loop structure is the main construction of the program with high performance computing needs. The characteristics of the loop structure for the program are as follows: (1) Instruction will be fetched from cache and be decoded repeatedly. (2) The limit of instructions issue number of the loop body. (3) There are dependence relations between iterations. These factors result in the poor ILP in the implementation of the loop. In order to develop the maximum benefit of the usage of the cores computing resources, the application of the Hyperscalar architecture should be emphasized. Because there is a specific ordering pattern in machine codes which produced by compiling the loop structure, we can formulate the semantic of the loop with the observations of this pattern. In this thesis, we propose an architecture called semantic-based loop unrolling mechanism in the Hyperscalar architecture. This architecture unrolls the loop in the instruction analyzer (IA) by analyzing the information gathered after finding the closed interval of loop body instructions by parsing the semantic of instructions, which is identical to what we formulate. Proposed architecture consists of three unit: loop detect unit (LDU), loop unrolling unit (LUU), and loop controller. Loop detect unit will find the closed interval of the loop body instructions by parsing the semantic of instructions, which is identical to what we formulate, and collecting the information of this closed interval. Loop unrolling unit will unroll the loop based on the information collected by LDU. The unrolling procedures of LUU are as follows: (1) Decide loop unrolling times by the resources of core numbers, and add the SEQ tag to these instructions. (2) Register renaming and eliminate iteration dependence of the unrolled loop. (3) Generate tag to these instructions and add compensate tag to make sure the accuracy of data. (4) Rearrange the issue order of these instructions to issue the instructions which have been eliminated iteration dependence in advance, and generate instruction tag dispatch table, loop VSRF mapping table, loop memory tag mapping table, and loop specific instruction flush table. Loop controller will depend on the branch instruction with wrong prediction result and the loop which finish the unrolling procedures to decide the dispatch right. If this branch instruction identical to the unrolled loopâs conditional check branch instruction, and then the dispatch right will be handed over to LUU. When the execution of the unrolled loop is finish, loop controller will hand over the dispatch right to IA. In this paper, the verify ARM instructions is generated by Keil Î¼Vision5 compiler. The results show that eliminating iteration dependence can improve ILP by 20% to 100%, and flushing specific instruction can decrease the total execution time of the loop whose loop body contains the internal branch instructions. Advisors/Committee Members: Yu-Liang Chou (chair), Rong%20Kuang%22%29&pagesize-30">Shiann-Rong Kuang (chair), Jih-Ching Chiu (committee member), Tong-Yu Hsieh (chair).

Subjects/Keywords: ILP of loop; hyperscalar; semantic of loop; loop unrolling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chao, S. (2017). Improving ILP with Semantic-Based Loop Unrolling Mechanism in the Hyperscalar Architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724117-184404

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chao, Shu-jung. “Improving ILP with Semantic-Based Loop Unrolling Mechanism in the Hyperscalar Architecture.” 2017. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724117-184404.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chao, Shu-jung. “Improving ILP with Semantic-Based Loop Unrolling Mechanism in the Hyperscalar Architecture.” 2017. Web. 18 Feb 2020.

Vancouver:

Chao S. Improving ILP with Semantic-Based Loop Unrolling Mechanism in the Hyperscalar Architecture. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724117-184404.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chao S. Improving ILP with Semantic-Based Loop Unrolling Mechanism in the Hyperscalar Architecture. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724117-184404

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

9. Wu, Mei-Jung. An Efficient Method to Assess Audio Quality and Its Hardware Implementation.

Degree: Master, Electrical Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801117-101956

► To facilitate storage and transmission, lossy compression is usually used for audio signals despite the possible quality degradation. On the other hand, scaling down of… (more)

▼ To facilitate storage and transmission, lossy compression is usually used for audio signals despite the possible quality degradation. On the other hand, scaling down of transistor sizes makes audio processing chips more sensible to process defects and noises and result in erroneous audio. Aging effects may also result in adverse impacts on audio quality. These would make messages delivered mis-understood. This problem becomes more critical for internet of things applications where speech recognition is expected to play an important role. Fortunately, minor variations in audio are likely to be imperceptible due to human beingsâ hearing insensitivity. This makes errors possibly still acceptable. The life time of audio chips can thus be extended. Therefore, one critical issue is how to effectively evaluate the acceptability of audio. In the literature there have been a number of accurate audio assessment methods developed. However, high computation complexity is required for these methods where long software execution time or unaffordable high hardware cost would be incurred. In this work, our goal is to develop an efficient audio acceptability evaluation method based on human beingsâ hearing sensibility. PEAQ (Perceptual Evaluation of Audio Quality) is one of the widely used audio quality assessment methods. In this work, we use PEAQ results to evaluate accuracy of the proposed methods and also evaluate the performance. Two efficient methods are proposed. Compared to PEAQ, both methods can reduce the software execution time by 94.24% and 77.27%, respectively. The first method can effectively assess output quality of faulty audio circuits â 82.33% accuracy for ordinary audio and even 92.42% for speech. This method is also easy to be implemented by hardware. The incurred hardware cost is only 3.98% with respect to commercial MP3 decoders. The second method is effective for compressed audio. 100% accuracy is achievable when the bandwidth of the reference audio is large enough. For faulty compressed audio, 80.80% accuracy can be achieved. Compared with the first proposed method, this method has higher hardware implementation complexity, and thus software implementation is preferred. Nevertheless, the hardware cost can be reduced if hardware in audio systems is used and investigated with the proposed method. Advisors/Committee Members: Hsin-Wen Ting (chair), Rong%20Kuang%22%29&pagesize-30">Shiann-Rong Kuang (chair), Tong-Yu Hsieh (committee member), Jih-Ching Chiu (chair).

Subjects/Keywords: audio processing circuits; audio acceptability evaluation; error-tolerance; PEAQ; erroneous audio

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Wu, M. (2017). An Efficient Method to Assess Audio Quality and Its Hardware Implementation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801117-101956

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wu, Mei-Jung. “An Efficient Method to Assess Audio Quality and Its Hardware Implementation.” 2017. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801117-101956.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wu, Mei-Jung. “An Efficient Method to Assess Audio Quality and Its Hardware Implementation.” 2017. Web. 18 Feb 2020.

Vancouver:

Wu M. An Efficient Method to Assess Audio Quality and Its Hardware Implementation. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801117-101956.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu M. An Efficient Method to Assess Audio Quality and Its Hardware Implementation. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801117-101956

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

10. Chang, Jia-hao. Design of Tessellation Unit for 3D Graphic Processor.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407

► Tessellation shader is one of the advanced graphics rendering functions supported in state-of-the-art graphics standard applications programming interfaces such as OpenGL 4.x and DirextX 11.… (more)

Subjects/Keywords: tessellation; tessellation primitive generation; OpenGL 4.x; tessellation unit; primitive assembly unit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chang, J. (2017). Design of Tessellation Unit for 3D Graphic Processor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chang, Jia-hao. “Design of Tessellation Unit for 3D Graphic Processor.” 2017. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chang, Jia-hao. “Design of Tessellation Unit for 3D Graphic Processor.” 2017. Web. 18 Feb 2020.

Vancouver:

Chang J. Design of Tessellation Unit for 3D Graphic Processor. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang J. Design of Tessellation Unit for 3D Graphic Processor. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

11. Chung, Chen-Chia. Error-Tolerability Enhancement for Videos by Adaptive I-Frame Insertion.

Degree: Master, Electrical Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808117-123522

► With the advances in semiconductor technology, Internet of Things (IoT) devices and applications have been developing rapidly. Among these devices and applications, surveillance systems play… (more)

▼ With the advances in semiconductor technology, Internet of Things (IoT) devices and applications have been developing rapidly. Among these devices and applications, surveillance systems play an important role in environmental security and also lead to more convenient life. So far surveillance systems have become more and more popular, which makes enhancing the reliability of the associated video processing circuits more critical. Due to aging effects or external disturbances, videos may become erroneous and thus even unrecognizable. On the other hand, since surveillance systems usually have a large number of video sources, manual checking and repairing each video source by the maintenance staff may incur huge cost. Fortunately, errors in video processing circuits may not necessarily invalidate the entire surveillance system. Minor errors may not affect the success of identifying objects of interests in the video. As a result, how to efficiently assess the reliability of video sources is a critical issue to be addressed. Moreover, if the reliability can be further enhanced, the lifetime of video processing circuits can be effectively extended. In this thesis, we carry out detailed error simulations for a video decoder, and analyze the impact of errors on the quality of videos. We also investigate the problems that recent video repair methods would encounter in repairing erroneous videos resulting from faulty decoders. Accordingly we develop an effective video quality enhancement technique and identify the scenarios that the developed technique is applicable. In these scenarios at least 77% of unacceptable erroneous videos can become acceptable. In addition, we also propose an error-tolerability enhancement flow for videos. In particular, this flow integrates with the no-reference error-tolerability test method developed by our research group. This integration leads to 90% test time and 99% needed memory space reduction when compared with the previous video quality assessment method. In addition to testing the error-tolerability of the circuit, our proposed flow can also further improve the error-tolerability of the circuit. Advisors/Committee Members: Rong%20Kuang%22%29&pagesize-30">Shiann-Rong Kuang (chair), Tong-Yu Hsieh (committee member), Jih-Ching Chiu (chair), Hsin-Wen Ting (chair).

Subjects/Keywords: quality improvement; video quality assessment; error-tolerability; erroneous video; video repair

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chung, C. (2017). Error-Tolerability Enhancement for Videos by Adaptive I-Frame Insertion. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808117-123522

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chung, Chen-Chia. “Error-Tolerability Enhancement for Videos by Adaptive I-Frame Insertion.” 2017. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808117-123522.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chung, Chen-Chia. “Error-Tolerability Enhancement for Videos by Adaptive I-Frame Insertion.” 2017. Web. 18 Feb 2020.

Vancouver:

Chung C. Error-Tolerability Enhancement for Videos by Adaptive I-Frame Insertion. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808117-123522.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chung C. Error-Tolerability Enhancement for Videos by Adaptive I-Frame Insertion. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808117-123522

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

12. Chung, Yu-Min. Efficient Noise Detection and Elimination Method for Voice Recognition Applications.

Degree: Master, Electrical Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812117-095430

► In recent years, voice recognition has been widely used in many smart home and smart phone applications. By recognizing human beingâs voices, more convenient operations… (more)

▼ In recent years, voice recognition has been widely used in many smart home and smart phone applications. By recognizing human beingâs voices, more convenient operations are enabled. Voice recognition also plays an important role in automotive electronics. Human beingsâ can thus safely control navigation systems or air conditioners during their driving. However, with the feature size shrinking of the semiconductor manufacturing technology, voice recognition circuits are more easily to be affected by external noises. This may result in unrecognition of voices, and therefore invalidates the system operations, and even raises safety concerns. As a result, it is very critical to accurately detect noises in voice signals, and accordingly eliminate them. This is also the research objective of this thesis. In this thesis we employ the ideal and non-ideal additive Gaussian white noise (AWGN) to simulate various types of noises in voice signals, and accordingly analyze their impacts on the recognition rate. Compared with the developed methods in the literature, we propose a more accurate noise detection technique. Our experimental results show that the proposed technique can achieve more than 99% accuracy. On the other hand, we also investigate the effectiveness of the previous methods in the literature for eliminating noises. We find that for ideal AWGN, the recognition rate can be enhanced by only 4.69%, while for non-ideal AWGN, 8.15% enhancement is achieved. However, by integrating the proposed noise detection technique with the previous method to develop a new noise elimination technique, we find that 12% enhancement on the recognition rate for ideal AWGN can be achieved, while the enhancement for the non-ideal AWGN is 42.11%. One major problem for the previous noise elimination methods is that the computation is quite complicated where the required execution time is 7.4 times the length of the target voice signal. In order to reduce the required computation complexity for eliminating noises, we further propose a linear approximation based novel noise elimination technique. The execution time of the proposed technique is only 6.5% of that for the previous method. For ideal AWGN, the proposed technique can enhance the recognition rate by 12%. As for non-ideal AWGN, the enhancement is 53.31%. Advisors/Committee Members: Jih-Ching Chiu (chair), Tong-Yu Hsieh (committee member), Hsin-Wen Ting (chair), Rong%20Kuang%22%29&pagesize-30">Shiann-Rong Kuang (chair).

Subjects/Keywords: additive Gaussian white noise (AWGN); quality improvement; voice recognition; noise elimination; noise detection

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chung, Y. (2017). Efficient Noise Detection and Elimination Method for Voice Recognition Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812117-095430

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chung, Yu-Min. “Efficient Noise Detection and Elimination Method for Voice Recognition Applications.” 2017. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812117-095430.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chung, Yu-Min. “Efficient Noise Detection and Elimination Method for Voice Recognition Applications.” 2017. Web. 18 Feb 2020.

Vancouver:

Chung Y. Efficient Noise Detection and Elimination Method for Voice Recognition Applications. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812117-095430.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chung Y. Efficient Noise Detection and Elimination Method for Voice Recognition Applications. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812117-095430

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

13. Cheng, Tai-ang. Error-Tolerability Test and Enhancement Methods for Images in Face Detection Applications.

Degree: Master, Electrical Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180159

► Face detection is mainly used to determinate wherther the face in the image can be detected or not. Accordingly the identity of the person can… (more)

▼ Face detection is mainly used to determinate wherther the face in the image can be detected or not. Accordingly the identity of the person can be recognized. In IoT (Internet of Things) applications, face detection plays an important role, such as identity recognition for door-accessing in buildings, and customs. However, high temperature, power switch, data transmission, defects, and wear-out of image processing circuits of the face detection system may result in noisy or erroneous images. Fortunately, these noises or errors do not necessarily fail the face detection system. For example, if the structure of the face is not seriously destroyed, the face is still likely detectable. In other words, the face detection system contains the error-tolerance feature where some errors can be accepted. The lifetime of the system can thus be extended. In the thesis, we carefully analyze the error tolerability of face detection systems, and compare with the human visiual system. Interestingly the comparison results show that the face detection system even has much higher error tolerability. We also propose a high efficiency error-tolerance test method to examine the acceptability of an image. In our experiments a total of 5730 erroneous benchmark images are used to evaluate the test accuracy of the proposed test method. Experimental results show that 97.12% test accuracy is achieved. In addition, in this thesis we also present an efficient image repair method for face detection systems. The results show that the proposed method can effectively enhance the acceptability of erroneous images, and thus improve the reliability of the face detection system. In the literature there have been a number of related repair works. However most of these researches focus on repairing noisy images. Erroenous images due to circuit aging are seldom considered. Although some work targets such images, single-bit errors are assumed. In the thesis, we consider not only erroneous images, but also the occurrence of multiple-bit errors. We also investigate the issues that the previous approaches cannot deal with such errors effectively. Accordingly we propose a more powerful method to repair erroneous image. It is worth mentioning that our developed method has excellent adaptability where our method can be dynamically reconfigured according to the significance of erroneous images. As a result, the content of high-quality images can still be maintained, while the quality of the moderate-quality images can be significantly increased. As for low-quality images, they will not be repaired in order to save computation time and power consumption. Advisors/Committee Members: Hsin-Wen Ting (chair), Rong%20Kuang%22%29&pagesize-30">Shiann-Rong Kuang (chair), Tong-Yu Hsieh (committee member), Jih-Ching Chiu (chair).

Subjects/Keywords: error-tolerance; face detection; image repair; image processing; image qulity evaluation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Cheng, T. (2017). Error-Tolerability Test and Enhancement Methods for Images in Face Detection Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180159

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Cheng, Tai-ang. “Error-Tolerability Test and Enhancement Methods for Images in Face Detection Applications.” 2017. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180159.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Cheng, Tai-ang. “Error-Tolerability Test and Enhancement Methods for Images in Face Detection Applications.” 2017. Web. 18 Feb 2020.

Vancouver:

Cheng T. Error-Tolerability Test and Enhancement Methods for Images in Face Detection Applications. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180159.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cheng T. Error-Tolerability Test and Enhancement Methods for Images in Face Detection Applications. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180159

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

14. Chan, Shang-En. An Efficient No-Reference Error-Tolerability Test Method for Videos.

Degree: Master, Electrical Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180509

► Since the IoT (Internet of Things) and home security is more and more common as technology progresses, the security that can be provided by surveillance… (more)

▼ Since the IoT (Internet of Things) and home security is more and more common as technology progresses, the security that can be provided by surveillance systems receives more and more attentions. However, the aging effects or process defects of the video processing related circuits in surveillance systems may result in errors such that the objects of interests are not easy to be identified and thus raises the security concern. On the other hand, surveillance systems usually have a large number of digital video sources. If the maintenance staff needs to check each video source manually to see if repair or replacement is required, the incurred cost may be unaffordable. Fortunately, the video errors may not necessarily fail the surveillance system. If the error is insignificant, the objects are still likely identifiable, and thus the error is acceptable. Therefore, how to evaluate the acceptability of video signals is one critical issue to be addressed, which is helpful to extend the life time of video processing circuits and thereby the surveillance system. The required maintenance costs can also be reduced. In this thesis, we proposed a no-reference error-tolerability test method for videos. In most of the video applications, especially for the surveillance system or videos that are provided by sensors, the reference (golden) video data are usually unavailable, which makes implementation of an error-tolerability test process quite difficult. No-reference test methods can allow us to evaluate video quality by analyzing only characteristics inside the video without reference videos. In the literature there have been several no-reference video quality assessment methods developed. However, these methods focus on dealing with only noises during transmission or compression of video signals. So far no work targets errors due to problems inside video processing circuits such as aging. We believe that this thesis is the first one that proposes a no-reference error-tolerability test method for erroneous circuits. In order to evaluate error-tolerability of erroneous videos, we simulate all the possible artifacts and generate various erroneous videos. We also analyze the characteristics of these generated erroneous videos as well their qualities. The relationship between video quality and its characteristics is also investigated. Accordingly an efficient error-tolerability test method is proposed, which can accurately evaluate acceptability of errors in short time. Compared with the previous researches, the proposed can achieve more than 90% test accuracy, while that of the previous method is only about 80%. In addition, our execution time is three times as fast as the previous method. Advisors/Committee Members: Tong-Yu Hsieh (committee member), Rong%20Kuang%22%29&pagesize-30">Shiann-Rong Kuang (chair), Jih-Ching Chiu (chair), Hsin-Wen Ting (chair).

Subjects/Keywords: video processing circuits; video quality evaluation; no-reference quality assessment; erroneous video; error-tolerance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chan, S. (2017). An Efficient No-Reference Error-Tolerability Test Method for Videos. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180509

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chan, Shang-En. “An Efficient No-Reference Error-Tolerability Test Method for Videos.” 2017. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180509.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chan, Shang-En. “An Efficient No-Reference Error-Tolerability Test Method for Videos.” 2017. Web. 18 Feb 2020.

Vancouver:

Chan S. An Efficient No-Reference Error-Tolerability Test Method for Videos. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180509.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chan S. An Efficient No-Reference Error-Tolerability Test Method for Videos. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180509

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

15. Ding, Yong-Chun. Potential Forecast Algorithm: A Novel Search-Experience-based Clustering Algorithm.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-165636

► Clustering is a classical problem that has been a valuable research topic because it exists in many fields, such as engineering, computer science, medical science,… (more)

Subjects/Keywords: potential forecast algorithm; metaheuristic; data mining; Clustering; k-means

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Ding, Y. (2017). Potential Forecast Algorithm: A Novel Search-Experience-based Clustering Algorithm. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-165636

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Ding, Yong-Chun. “Potential Forecast Algorithm: A Novel Search-Experience-based Clustering Algorithm.” 2017. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-165636.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Ding, Yong-Chun. “Potential Forecast Algorithm: A Novel Search-Experience-based Clustering Algorithm.” 2017. Web. 18 Feb 2020.

Vancouver:

Ding Y. Potential Forecast Algorithm: A Novel Search-Experience-based Clustering Algorithm. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-165636.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ding Y. Potential Forecast Algorithm: A Novel Search-Experience-based Clustering Algorithm. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-165636

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

16. Liao, Chun-Kai. A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172335

► The proposed PLL in this thesis is implemented in TSMC 90nm 1P9M RF technology with a 1V supply voltage. This thesis presents a wide tuning… (more)

Subjects/Keywords: PLL; Controllable OTA; VCO; Charge Pump; PFD; Bootstrapped Switch

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Liao, C. (2017). A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172335

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Liao, Chun-Kai. “A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier.” 2017. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172335.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Liao, Chun-Kai. “A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier.” 2017. Web. 18 Feb 2020.

Vancouver:

Liao C. A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172335.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liao C. A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172335

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

17. Chen, Hung-Yen. A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172820

► In this thesis, a 10-bit binary search assisted two channel SAR ADC with a two bit per conversion and error tolerance ability operating in 250Ms/s… (more)

Subjects/Keywords: Two bits per conversion; Non-binary; Time-interleaved; Binary search; SAR ADC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chen, H. (2017). A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172820

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chen, Hung-Yen. “A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability.” 2017. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172820.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chen, Hung-Yen. “A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability.” 2017. Web. 18 Feb 2020.

Vancouver:

Chen H. A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172820.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen H. A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172820

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

18. Huang, Yi-Hsuan. VLSI Design And Implementation Of Low Bit-error Rate HomePlug AV System.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-182647

► This thesis implements the HomePlug AV power line communication system to reduce the probability of decoding errors caused by noise interference during transmission. The architecture… (more)

Subjects/Keywords: , PLC; FFT; QAM; Interleaver; Scramble; Turbo Code; OFDM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Huang, Y. (2017). VLSI Design And Implementation Of Low Bit-error Rate HomePlug AV System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-182647

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Huang, Yi-Hsuan. “VLSI Design And Implementation Of Low Bit-error Rate HomePlug AV System.” 2017. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-182647.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Huang, Yi-Hsuan. “VLSI Design And Implementation Of Low Bit-error Rate HomePlug AV System.” 2017. Web. 18 Feb 2020.

Vancouver:

Huang Y. VLSI Design And Implementation Of Low Bit-error Rate HomePlug AV System. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-182647.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang Y. VLSI Design And Implementation Of Low Bit-error Rate HomePlug AV System. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-182647

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

19. Huang, Po-Chun. Design and Implementation of High-Performance Polar Encoder For Next-Generation Communication Systems.

Degree: Master, Electrical Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-163421

► In the communication system, Error Correcting codes (ECC) would become a necessary and important module because it can prevent from the noise disturbance and eliminate… (more)

Subjects/Keywords: 5th generation wireless systems; Variable-Length FIFO feedback; Reconfigurable; Polar codes; Error-correcting code

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Huang, P. (2017). Design and Implementation of High-Performance Polar Encoder For Next-Generation Communication Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-163421

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Huang, Po-Chun. “Design and Implementation of High-Performance Polar Encoder For Next-Generation Communication Systems.” 2017. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-163421.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Huang, Po-Chun. “Design and Implementation of High-Performance Polar Encoder For Next-Generation Communication Systems.” 2017. Web. 18 Feb 2020.

Vancouver:

Huang P. Design and Implementation of High-Performance Polar Encoder For Next-Generation Communication Systems. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-163421.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang P. Design and Implementation of High-Performance Polar Encoder For Next-Generation Communication Systems. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-163421

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

20. Yen, Huai-yu. Power Optimization for 3D Vertex Shader Using Clock Gating.

Degree: Master, Computer Science and Engineering, 2008, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816108-003258

► With technology increasingly and the needs of high performance and multiple functionalities, power dissipation has be a bottleneck in microprocessors. And clock power is the… (more)

Subjects/Keywords: instruction schedule; 3D vertex shader; clock gating; Low power

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Yen, H. (2008). Power Optimization for 3D Vertex Shader Using Clock Gating. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816108-003258

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Yen, Huai-yu. “Power Optimization for 3D Vertex Shader Using Clock Gating.” 2008. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816108-003258.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Yen, Huai-yu. “Power Optimization for 3D Vertex Shader Using Clock Gating.” 2008. Web. 18 Feb 2020.

Vancouver:

Yen H. Power Optimization for 3D Vertex Shader Using Clock Gating. [Internet] [Thesis]. NSYSU; 2008. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816108-003258.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yen H. Power Optimization for 3D Vertex Shader Using Clock Gating. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816108-003258

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

21. Hsu, Hua-Shan. Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip.

Degree: Master, Computer Science and Engineering, 2008, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825108-165911

► The 3D applications, until recently restricted to the desktops and workstations, are expanding into the mobile platforms, such as cellular phones and PDAs. Similar to… (more)

Subjects/Keywords: power management; low power; workload estimation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Hsu, H. (2008). Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825108-165911

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hsu, Hua-Shan. “Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip.” 2008. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825108-165911.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hsu, Hua-Shan. “Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip.” 2008. Web. 18 Feb 2020.

Vancouver:

Hsu H. Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip. [Internet] [Thesis]. NSYSU; 2008. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825108-165911.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu H. Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825108-165911

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

22. Lee, Hsin-mau. Designs, Implementations and Applications of Floating-Point Trigonometric Function Units.

Degree: Master, Computer Science and Engineering, 2008, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251

► In addition to the previous pipelined floating-point CORDIC design, three different architectures supporting both CORDIC rotation mode and vectoring mode are proposed in this thesis.… (more)

Subjects/Keywords: Floating-point; CORDIC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lee, H. (2008). Designs, Implementations and Applications of Floating-Point Trigonometric Function Units. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lee, Hsin-mau. “Designs, Implementations and Applications of Floating-Point Trigonometric Function Units.” 2008. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lee, Hsin-mau. “Designs, Implementations and Applications of Floating-Point Trigonometric Function Units.” 2008. Web. 18 Feb 2020.

Vancouver:

Lee H. Designs, Implementations and Applications of Floating-Point Trigonometric Function Units. [Internet] [Thesis]. NSYSU; 2008. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee H. Designs, Implementations and Applications of Floating-Point Trigonometric Function Units. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

23. Tseng, Guo-Fu. CDPthread: A POSIX-Thread Based Distributed Computing Environment.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728109-115706

► Due to the limitation of single machineâs computing power, and the aspect of cost, distributed design is getting more and more popular nowadays. The Distributed… (more)

Subjects/Keywords: operating system; distributed system; POSIX; distributed shared memory; thread; multi-thread

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Tseng, G. (2009). CDPthread: A POSIX-Thread Based Distributed Computing Environment. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728109-115706

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Tseng, Guo-Fu. “CDPthread: A POSIX-Thread Based Distributed Computing Environment.” 2009. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728109-115706.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Tseng, Guo-Fu. “CDPthread: A POSIX-Thread Based Distributed Computing Environment.” 2009. Web. 18 Feb 2020.

Vancouver:

Tseng G. CDPthread: A POSIX-Thread Based Distributed Computing Environment. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728109-115706.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tseng G. CDPthread: A POSIX-Thread Based Distributed Computing Environment. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728109-115706

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

24. Wu, Zong-Lin. Low-Overhead Isolation Cells for Low-Power Multipliers.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550

► With the rapid progress in manufacturing technology, the chip design is more and more complicated day by day. As a result, the circuit design with… (more)

Subjects/Keywords: low overhead isolation cell; standard cell; low-power multipliers

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Wu, Z. (2009). Low-Overhead Isolation Cells for Low-Power Multipliers. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wu, Zong-Lin. “Low-Overhead Isolation Cells for Low-Power Multipliers.” 2009. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wu, Zong-Lin. “Low-Overhead Isolation Cells for Low-Power Multipliers.” 2009. Web. 18 Feb 2020.

Vancouver:

Wu Z. Low-Overhead Isolation Cells for Low-Power Multipliers. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu Z. Low-Overhead Isolation Cells for Low-Power Multipliers. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

25. Fu, Chien-jung. Design of Various VLSI Sorting Accelerator Architectures.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831109-115655

► In this thesis, various designs of VLSI sorter architectures are proposed. This thesis first presents a baseline serial sorter architecture built on a central memory… (more)

▼ In this thesis, various designs of VLSI sorter architectures are proposed. This thesis first presents a baseline serial sorter architecture built on a central memory module equipped with a single compare-and-swap (C&S) functional unit. A dedicated low-cost address generation circuit which controls the order of data accesses and C&S operation in order to support sorting of data sequences with any length is proposed. By exploring the bit-permutation technique to create the access orders suitable for different C&S steps, the address generator can be built by only two adders and three shifters plus some control circuits, and consumes only about 1K gates. Next, this thesis also proposes a two-bank memory architecture to reduce the required memory ports from four to two such that the sorter memory can be realized by on-chip SRAM blocks. Our experimental results show that the overall silicon cost can be reduced by more than 56% for the sorter circuit which can sort the data sequence of length up to 1024. In addition to the serial sorter architecture, this thesis further proposes three possible parallel sorter architectures including the pipeline sorter, cascade sorter, and block sorter. Among these three architectures, the pipeline sorter can deliver the best throughput although it can be used only for fixed-length data sequences. On the other hand, the block sorter is the most flexible design suitable for sequences with variable length. It is designed based on the block-level even-odd merge sort algorithm. It significantly outperforms the previous block sorter design by using more efficient algorithm, architectural pipelining, and better block C&S(BC&S) unit which can realize separate pre-sort and merge processes efficiently. Our implementation results show that by using the 0.18um technology, the core size of the proposed sorter with block-size of four is about 0.509mm2, and can sorting a 1024-point sequence within 32.84us. Advisors/Committee Members: Chuen-Yau Chen (chair), Yun-Nan Chang (committee member), Rong%20Kuang%22%29&pagesize-30">Shiann-Rong Kuang (chair).

Subjects/Keywords: Sorter; Odd-Even merge sort

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Fu, C. (2009). Design of Various VLSI Sorting Accelerator Architectures. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831109-115655

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Fu, Chien-jung. “Design of Various VLSI Sorting Accelerator Architectures.” 2009. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831109-115655.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Fu, Chien-jung. “Design of Various VLSI Sorting Accelerator Architectures.” 2009. Web. 18 Feb 2020.

Vancouver:

Fu C. Design of Various VLSI Sorting Accelerator Architectures. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831109-115655.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fu C. Design of Various VLSI Sorting Accelerator Architectures. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831109-115655

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

26. Lin, Chueh-Ting. Multi-bank Memory-based Matrix-Transposer Circuit Generator.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-113406

► A novel design methodology of parallel VLSI matrix transposer circuit based on a multi-bank memory architecture is presented. The proposed transposer design is especially suitable… (more)

Subjects/Keywords: Matrix Transposer

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lin, C. (2009). Multi-bank Memory-based Matrix-Transposer Circuit Generator. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-113406

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lin, Chueh-Ting. “Multi-bank Memory-based Matrix-Transposer Circuit Generator.” 2009. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-113406.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lin, Chueh-Ting. “Multi-bank Memory-based Matrix-Transposer Circuit Generator.” 2009. Web. 18 Feb 2020.

Vancouver:

Lin C. Multi-bank Memory-based Matrix-Transposer Circuit Generator. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-113406.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin C. Multi-bank Memory-based Matrix-Transposer Circuit Generator. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-113406

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

27. Lin, Ching-Yuan. Performance Modeling for a 3D Graphics SoC.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522

► The design of SoC is growing into more complicated, hence it is necessary to determine an efficient way to develop an SoC. If we can… (more)

Subjects/Keywords: 3D Graphics; Tile-based; analysis; SystemC; TLM

Record Details Similar Records Cite « Share

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lin, C. (2009). Performance Modeling for a 3D Graphics SoC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lin, Ching-Yuan. “Performance Modeling for a 3D Graphics SoC.” 2009. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lin, Ching-Yuan. “Performance Modeling for a 3D Graphics SoC.” 2009. Web. 18 Feb 2020.

Vancouver:

Lin C. Performance Modeling for a 3D Graphics SoC. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin C. Performance Modeling for a 3D Graphics SoC. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

28. Lee, Cheng-Han. Design, Analysis and Applications of Hybrid CORDIC Processor Architectures.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513

► In this thesis, we propose different CORDIC architectures which solve the problems of long-latency in traditional pipeline CORDIC and the large-area cost in table-based CORDIC.… (more)

Subjects/Keywords: Arithmetic Function Units; CORDIC; Taylor-series expansion

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lee, C. (2010). Design, Analysis and Applications of Hybrid CORDIC Processor Architectures. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lee, Cheng-Han. “Design, Analysis and Applications of Hybrid CORDIC Processor Architectures.” 2010. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lee, Cheng-Han. “Design, Analysis and Applications of Hybrid CORDIC Processor Architectures.” 2010. Web. 18 Feb 2020.

Vancouver:

Lee C. Design, Analysis and Applications of Hybrid CORDIC Processor Architectures. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee C. Design, Analysis and Applications of Hybrid CORDIC Processor Architectures. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

29. Tsai, Cheng-Hsuan. Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704

► The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, various new logic circuit design styles based on… (more)

Subjects/Keywords: CMOS logic; Logic Synthesizer; Standard Cell Library; ASIC Design Flow; Pass-Transition-Logic(PTL)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Tsai, C. (2010). Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Tsai, Cheng-Hsuan. “Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library.” 2010. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Tsai, Cheng-Hsuan. “Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library.” 2010. Web. 18 Feb 2020.

Vancouver:

Tsai C. Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsai C. Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

30. Chiu, Chan-Feng. Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101

► This thesis focuses on efficient design of a vertex shader for per-vertex operations such as Transformation and Lighting in the OpenGL ES 2.0 graphics pipeline.… (more)

Subjects/Keywords: 3D Graph; Logarithmic Number System; Vertex Shader

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chiu, C. (2010). Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chiu, Chan-Feng. “Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System.” 2010. Thesis, NSYSU. Accessed February 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chiu, Chan-Feng. “Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System.” 2010. Web. 18 Feb 2020.

Vancouver:

Chiu C. Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Feb 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chiu C. Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Open Access Theses and Dissertations