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NSYSU
1. Chou, Yu-chieh. On the Design and Implementation of Load Balancing for CDPthread-based Systems.
Degree: Master, Computer Science and Engineering, 2009, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902109-212626
Subjects/Keywords: Distributed shared memory; Load balancing; CDPthread
Record Details
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Chou, Y. (2009). On the Design and Implementation of Load Balancing for CDPthread-based Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902109-212626
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Chou, Yu-chieh. “On the Design and Implementation of Load Balancing for CDPthread-based Systems.” 2009. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902109-212626.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Chou, Yu-chieh. “On the Design and Implementation of Load Balancing for CDPthread-based Systems.” 2009. Web. 10 Apr 2021.
Vancouver:
Chou Y. On the Design and Implementation of Load Balancing for CDPthread-based Systems. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902109-212626.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Chou Y. On the Design and Implementation of Load Balancing for CDPthread-based Systems. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902109-212626
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
2. Lin, Chieh-Wei. Software Implementation of Topology-based Communication Library.
Degree: Master, Electrical Engineering, 2013, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0530113-200455
Subjects/Keywords: parallel computing; topology; communication interconnection design; communication library; distributed computing systems
Record Details
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APA (6th Edition):
Lin, C. (2013). Software Implementation of Topology-based Communication Library. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0530113-200455
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Lin, Chieh-Wei. “Software Implementation of Topology-based Communication Library.” 2013. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0530113-200455.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Lin, Chieh-Wei. “Software Implementation of Topology-based Communication Library.” 2013. Web. 10 Apr 2021.
Vancouver:
Lin C. Software Implementation of Topology-based Communication Library. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0530113-200455.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Lin C. Software Implementation of Topology-based Communication Library. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0530113-200455
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
3. Chen, Yu-ying. Software Implementation of a Data Model Design.
Degree: Master, Electrical Engineering, 2014, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-142048
Subjects/Keywords: data model; entity-relationship model; model-driven architecture; software engineering; data access model
Record Details
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Chen, Y. (2014). Software Implementation of a Data Model Design. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-142048
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Chen, Yu-ying. “Software Implementation of a Data Model Design.” 2014. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-142048.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Chen, Yu-ying. “Software Implementation of a Data Model Design.” 2014. Web. 10 Apr 2021.
Vancouver:
Chen Y. Software Implementation of a Data Model Design. [Internet] [Thesis]. NSYSU; 2014. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-142048.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Chen Y. Software Implementation of a Data Model Design. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-142048
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
4. Yen, Huai-yu. Power Optimization for 3D Vertex Shader Using Clock Gating.
Degree: Master, Computer Science and Engineering, 2008, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816108-003258
Subjects/Keywords: instruction schedule; 3D vertex shader; clock gating; Low power
Record Details
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Yen, H. (2008). Power Optimization for 3D Vertex Shader Using Clock Gating. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816108-003258
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Yen, Huai-yu. “Power Optimization for 3D Vertex Shader Using Clock Gating.” 2008. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816108-003258.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Yen, Huai-yu. “Power Optimization for 3D Vertex Shader Using Clock Gating.” 2008. Web. 10 Apr 2021.
Vancouver:
Yen H. Power Optimization for 3D Vertex Shader Using Clock Gating. [Internet] [Thesis]. NSYSU; 2008. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816108-003258.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Yen H. Power Optimization for 3D Vertex Shader Using Clock Gating. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816108-003258
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
5. Hsu, Hua-Shan. Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip.
Degree: Master, Computer Science and Engineering, 2008, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825108-165911
Subjects/Keywords: power management; low power; workload estimation
Record Details
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Hsu, H. (2008). Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825108-165911
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Hsu, Hua-Shan. “Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip.” 2008. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825108-165911.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Hsu, Hua-Shan. “Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip.” 2008. Web. 10 Apr 2021.
Vancouver:
Hsu H. Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip. [Internet] [Thesis]. NSYSU; 2008. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825108-165911.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Hsu H. Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825108-165911
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
6. Lee, Hsin-mau. Designs, Implementations and Applications of Floating-Point Trigonometric Function Units.
Degree: Master, Computer Science and Engineering, 2008, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251
Subjects/Keywords: Floating-point; CORDIC
Record Details
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Lee, H. (2008). Designs, Implementations and Applications of Floating-Point Trigonometric Function Units. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Lee, Hsin-mau. “Designs, Implementations and Applications of Floating-Point Trigonometric Function Units.” 2008. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Lee, Hsin-mau. “Designs, Implementations and Applications of Floating-Point Trigonometric Function Units.” 2008. Web. 10 Apr 2021.
Vancouver:
Lee H. Designs, Implementations and Applications of Floating-Point Trigonometric Function Units. [Internet] [Thesis]. NSYSU; 2008. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Lee H. Designs, Implementations and Applications of Floating-Point Trigonometric Function Units. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
7. Tseng, Guo-Fu. CDPthread: A POSIX-Thread Based Distributed Computing Environment.
Degree: Master, Computer Science and Engineering, 2009, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728109-115706
Subjects/Keywords: operating system; distributed system; POSIX; distributed shared memory; thread; multi-thread
Record Details
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Tseng, G. (2009). CDPthread: A POSIX-Thread Based Distributed Computing Environment. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728109-115706
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Tseng, Guo-Fu. “CDPthread: A POSIX-Thread Based Distributed Computing Environment.” 2009. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728109-115706.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Tseng, Guo-Fu. “CDPthread: A POSIX-Thread Based Distributed Computing Environment.” 2009. Web. 10 Apr 2021.
Vancouver:
Tseng G. CDPthread: A POSIX-Thread Based Distributed Computing Environment. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728109-115706.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Tseng G. CDPthread: A POSIX-Thread Based Distributed Computing Environment. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728109-115706
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
8. Wu, Zong-Lin. Low-Overhead Isolation Cells for Low-Power Multipliers.
Degree: Master, Computer Science and Engineering, 2009, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550
Subjects/Keywords: low overhead isolation cell; standard cell; low-power multipliers
Record Details
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Wu, Z. (2009). Low-Overhead Isolation Cells for Low-Power Multipliers. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Wu, Zong-Lin. “Low-Overhead Isolation Cells for Low-Power Multipliers.” 2009. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Wu, Zong-Lin. “Low-Overhead Isolation Cells for Low-Power Multipliers.” 2009. Web. 10 Apr 2021.
Vancouver:
Wu Z. Low-Overhead Isolation Cells for Low-Power Multipliers. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Wu Z. Low-Overhead Isolation Cells for Low-Power Multipliers. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
9. Fu, Chien-jung. Design of Various VLSI Sorting Accelerator Architectures.
Degree: Master, Computer Science and Engineering, 2009, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831109-115655
Subjects/Keywords: Sorter; Odd-Even merge sort
Record Details
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Fu, C. (2009). Design of Various VLSI Sorting Accelerator Architectures. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831109-115655
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Fu, Chien-jung. “Design of Various VLSI Sorting Accelerator Architectures.” 2009. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831109-115655.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Fu, Chien-jung. “Design of Various VLSI Sorting Accelerator Architectures.” 2009. Web. 10 Apr 2021.
Vancouver:
Fu C. Design of Various VLSI Sorting Accelerator Architectures. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831109-115655.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Fu C. Design of Various VLSI Sorting Accelerator Architectures. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831109-115655
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
10. Lin, Chueh-Ting. Multi-bank Memory-based Matrix-Transposer Circuit Generator.
Degree: Master, Computer Science and Engineering, 2009, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-113406
Subjects/Keywords: Matrix Transposer
Record Details
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Lin, C. (2009). Multi-bank Memory-based Matrix-Transposer Circuit Generator. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-113406
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Lin, Chueh-Ting. “Multi-bank Memory-based Matrix-Transposer Circuit Generator.” 2009. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-113406.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Lin, Chueh-Ting. “Multi-bank Memory-based Matrix-Transposer Circuit Generator.” 2009. Web. 10 Apr 2021.
Vancouver:
Lin C. Multi-bank Memory-based Matrix-Transposer Circuit Generator. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-113406.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Lin C. Multi-bank Memory-based Matrix-Transposer Circuit Generator. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-113406
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
11. Lin, Ching-Yuan. Performance Modeling for a 3D Graphics SoC.
Degree: Master, Computer Science and Engineering, 2009, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522
Subjects/Keywords: 3D Graphics; Tile-based; analysis; SystemC; TLM
Record Details
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Lin, C. (2009). Performance Modeling for a 3D Graphics SoC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Lin, Ching-Yuan. “Performance Modeling for a 3D Graphics SoC.” 2009. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Lin, Ching-Yuan. “Performance Modeling for a 3D Graphics SoC.” 2009. Web. 10 Apr 2021.
Vancouver:
Lin C. Performance Modeling for a 3D Graphics SoC. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Lin C. Performance Modeling for a 3D Graphics SoC. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
12. Lee, Cheng-Han. Design, Analysis and Applications of Hybrid CORDIC Processor Architectures.
Degree: Master, Computer Science and Engineering, 2010, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513
Subjects/Keywords: Arithmetic Function Units; CORDIC; Taylor-series expansion
Record Details
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Lee, C. (2010). Design, Analysis and Applications of Hybrid CORDIC Processor Architectures. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Lee, Cheng-Han. “Design, Analysis and Applications of Hybrid CORDIC Processor Architectures.” 2010. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Lee, Cheng-Han. “Design, Analysis and Applications of Hybrid CORDIC Processor Architectures.” 2010. Web. 10 Apr 2021.
Vancouver:
Lee C. Design, Analysis and Applications of Hybrid CORDIC Processor Architectures. [Internet] [Thesis]. NSYSU; 2010. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Lee C. Design, Analysis and Applications of Hybrid CORDIC Processor Architectures. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
13. Tsai, Cheng-Hsuan. Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library.
Degree: Master, Computer Science and Engineering, 2010, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704
Subjects/Keywords: CMOS logic; Logic Synthesizer; Standard Cell Library; ASIC Design Flow; Pass-Transition-Logic(PTL)
Record Details
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APA (6th Edition):
Tsai, C. (2010). Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Tsai, Cheng-Hsuan. “Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library.” 2010. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Tsai, Cheng-Hsuan. “Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library.” 2010. Web. 10 Apr 2021.
Vancouver:
Tsai C. Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library. [Internet] [Thesis]. NSYSU; 2010. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Tsai C. Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
14. Chiu, Chan-Feng. Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System.
Degree: Master, Computer Science and Engineering, 2010, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101
Subjects/Keywords: 3D Graph; Logarithmic Number System; Vertex Shader
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APA (6th Edition):
Chiu, C. (2010). Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Chiu, Chan-Feng. “Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System.” 2010. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Chiu, Chan-Feng. “Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System.” 2010. Web. 10 Apr 2021.
Vancouver:
Chiu C. Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System. [Internet] [Thesis]. NSYSU; 2010. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Chiu C. Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
15. Wu, Po-han. Table Size Reduction and Optimization in Multiplierless Table-Based Function Evaluation Designs.
Degree: Master, Computer Science and Engineering, 2013, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631113-083045
Subjects/Keywords: compress-tree; error-analysis; look-up-table-and-add; multiplier-less function evaluation method; elementary function evaluation method
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Wu, P. (2013). Table Size Reduction and Optimization in Multiplierless Table-Based Function Evaluation Designs. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631113-083045
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Wu, Po-han. “Table Size Reduction and Optimization in Multiplierless Table-Based Function Evaluation Designs.” 2013. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631113-083045.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Wu, Po-han. “Table Size Reduction and Optimization in Multiplierless Table-Based Function Evaluation Designs.” 2013. Web. 10 Apr 2021.
Vancouver:
Wu P. Table Size Reduction and Optimization in Multiplierless Table-Based Function Evaluation Designs. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631113-083045.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Wu P. Table Size Reduction and Optimization in Multiplierless Table-Based Function Evaluation Designs. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631113-083045
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
16. Liou, Yu-Ting. Design and Implementation of Wireless Sensor Network Architecture with Optimizing Energy Management Strategy.
Degree: Master, Electrical Engineering, 2013, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721113-011151
Subjects/Keywords: routing path; network topology; AODV; embedded microprocessors; wireless sensor networks
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Liou, Y. (2013). Design and Implementation of Wireless Sensor Network Architecture with Optimizing Energy Management Strategy. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721113-011151
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Liou, Yu-Ting. “Design and Implementation of Wireless Sensor Network Architecture with Optimizing Energy Management Strategy.” 2013. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721113-011151.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Liou, Yu-Ting. “Design and Implementation of Wireless Sensor Network Architecture with Optimizing Energy Management Strategy.” 2013. Web. 10 Apr 2021.
Vancouver:
Liou Y. Design and Implementation of Wireless Sensor Network Architecture with Optimizing Energy Management Strategy. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721113-011151.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Liou Y. Design and Implementation of Wireless Sensor Network Architecture with Optimizing Energy Management Strategy. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721113-011151
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
17. Wang, Sheng-Hao. An Integrated Development Platform for Heterogeneous Multicore Constructed on Windows CE Operating System.
Degree: Master, Electrical Engineering, 2013, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725113-211646
Subjects/Keywords: Synchronous machanism; DSP; Heterogeneous; Driver; WinCE
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Wang, S. (2013). An Integrated Development Platform for Heterogeneous Multicore Constructed on Windows CE Operating System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725113-211646
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Wang, Sheng-Hao. “An Integrated Development Platform for Heterogeneous Multicore Constructed on Windows CE Operating System.” 2013. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725113-211646.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Wang, Sheng-Hao. “An Integrated Development Platform for Heterogeneous Multicore Constructed on Windows CE Operating System.” 2013. Web. 10 Apr 2021.
Vancouver:
Wang S. An Integrated Development Platform for Heterogeneous Multicore Constructed on Windows CE Operating System. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725113-211646.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Wang S. An Integrated Development Platform for Heterogeneous Multicore Constructed on Windows CE Operating System. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725113-211646
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
18. Huang, Jun-ming. Hardware Design of Disparity Estimation Using Belief Propagation.
Degree: Master, Computer Science and Engineering, 2013, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727113-103923
Subjects/Keywords: Markov random field; belief propagation; disparity computation; depth map; stereo matching; stereo vision
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Huang, J. (2013). Hardware Design of Disparity Estimation Using Belief Propagation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727113-103923
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Huang, Jun-ming. “Hardware Design of Disparity Estimation Using Belief Propagation.” 2013. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727113-103923.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Huang, Jun-ming. “Hardware Design of Disparity Estimation Using Belief Propagation.” 2013. Web. 10 Apr 2021.
Vancouver:
Huang J. Hardware Design of Disparity Estimation Using Belief Propagation. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727113-103923.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Huang J. Hardware Design of Disparity Estimation Using Belief Propagation. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727113-103923
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
19. KU, CHIA-CHI. A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications.
Degree: Master, Electrical Engineering, 2013, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-181850
Subjects/Keywords: yield improvement; VLSI testing; error-tolerance; built-in self-test; image enhancement
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
KU, C. (2013). A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-181850
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
KU, CHIA-CHI. “A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications.” 2013. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-181850.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
KU, CHIA-CHI. “A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications.” 2013. Web. 10 Apr 2021.
Vancouver:
KU C. A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-181850.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
KU C. A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-181850
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
20. Huang, Chih-Hong. Hardware Design of Multi-view 3D Stereo Synthesizers Based on Two Image Sequences.
Degree: Master, Computer Science and Engineering, 2013, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-151411
Subjects/Keywords: stereo matching; hole filling; image warping; disparity estimation; depth-image-based rendering (DIBR); multiview virtual images
Record Details
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Huang, C. (2013). Hardware Design of Multi-view 3D Stereo Synthesizers Based on Two Image Sequences. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-151411
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Huang, Chih-Hong. “Hardware Design of Multi-view 3D Stereo Synthesizers Based on Two Image Sequences.” 2013. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-151411.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Huang, Chih-Hong. “Hardware Design of Multi-view 3D Stereo Synthesizers Based on Two Image Sequences.” 2013. Web. 10 Apr 2021.
Vancouver:
Huang C. Hardware Design of Multi-view 3D Stereo Synthesizers Based on Two Image Sequences. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-151411.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Huang C. Hardware Design of Multi-view 3D Stereo Synthesizers Based on Two Image Sequences. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-151411
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
21. Wang, Zih-Ang. Design and Implementation of the Optimized Architecture for Modbus and DNP 3.0 on the CAN Bus.
Degree: Master, Electrical Engineering, 2013, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725113-235040
Subjects/Keywords: Controller Area Network; Modbus and DNP3 Protocol on the CAN Bus; Automation Network; SCADA Area Network; CAN-to-TCP/IP on Ethernet Gateway
Record Details
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Wang, Z. (2013). Design and Implementation of the Optimized Architecture for Modbus and DNP 3.0 on the CAN Bus. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725113-235040
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Wang, Zih-Ang. “Design and Implementation of the Optimized Architecture for Modbus and DNP 3.0 on the CAN Bus.” 2013. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725113-235040.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Wang, Zih-Ang. “Design and Implementation of the Optimized Architecture for Modbus and DNP 3.0 on the CAN Bus.” 2013. Web. 10 Apr 2021.
Vancouver:
Wang Z. Design and Implementation of the Optimized Architecture for Modbus and DNP 3.0 on the CAN Bus. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725113-235040.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Wang Z. Design and Implementation of the Optimized Architecture for Modbus and DNP 3.0 on the CAN Bus. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725113-235040
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
22. Kao, Tien-Tsai. Error Tolerability Analysis and Error-Tolerant Design Investigation of A JPEG2000 Image Encoder.
Degree: Master, Electrical Engineering, 2013, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805113-011126
Subjects/Keywords: quantization; acceptability of faults; error tolerance; yield; discrete wavelet transform; JPEG2000
Record Details
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Kao, T. (2013). Error Tolerability Analysis and Error-Tolerant Design Investigation of A JPEG2000 Image Encoder. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805113-011126
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Kao, Tien-Tsai. “Error Tolerability Analysis and Error-Tolerant Design Investigation of A JPEG2000 Image Encoder.” 2013. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805113-011126.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Kao, Tien-Tsai. “Error Tolerability Analysis and Error-Tolerant Design Investigation of A JPEG2000 Image Encoder.” 2013. Web. 10 Apr 2021.
Vancouver:
Kao T. Error Tolerability Analysis and Error-Tolerant Design Investigation of A JPEG2000 Image Encoder. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805113-011126.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Kao T. Error Tolerability Analysis and Error-Tolerant Design Investigation of A JPEG2000 Image Encoder. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805113-011126
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
23. Hsu, Chao-yi. Design and implementation of a multi-thread unified SIMD graphics processor.
Degree: Master, Computer Science and Engineering, 2013, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808113-022414
Subjects/Keywords: Multi-threading; Unified GPU; Thread control; Fill unit; Multi-texture
Record Details
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APA (6th Edition):
Hsu, C. (2013). Design and implementation of a multi-thread unified SIMD graphics processor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808113-022414
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Hsu, Chao-yi. “Design and implementation of a multi-thread unified SIMD graphics processor.” 2013. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808113-022414.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Hsu, Chao-yi. “Design and implementation of a multi-thread unified SIMD graphics processor.” 2013. Web. 10 Apr 2021.
Vancouver:
Hsu C. Design and implementation of a multi-thread unified SIMD graphics processor. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808113-022414.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Hsu C. Design and implementation of a multi-thread unified SIMD graphics processor. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808113-022414
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
24. Chen, Han-wei. A Memory-efficient 2D-graphics rasterization scheme.
Degree: Master, Computer Science and Engineering, 2013, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-053639
Subjects/Keywords: scan-line buffer; Vector Graphics; Rasterization; winding count; 2D vector graphics
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APA (6th Edition):
Chen, H. (2013). A Memory-efficient 2D-graphics rasterization scheme. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-053639
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Chen, Han-wei. “A Memory-efficient 2D-graphics rasterization scheme.” 2013. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-053639.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Chen, Han-wei. “A Memory-efficient 2D-graphics rasterization scheme.” 2013. Web. 10 Apr 2021.
Vancouver:
Chen H. A Memory-efficient 2D-graphics rasterization scheme. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-053639.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Chen H. A Memory-efficient 2D-graphics rasterization scheme. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-053639
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
25. Tang, En-shou. Design exploration of multi-core GPU architecture.
Degree: Master, Computer Science and Engineering, 2013, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-135037
Subjects/Keywords: GPU; simulation platform; thread scheduling; back-face culling; clipping
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Tang, E. (2013). Design exploration of multi-core GPU architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-135037
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Tang, En-shou. “Design exploration of multi-core GPU architecture.” 2013. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-135037.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Tang, En-shou. “Design exploration of multi-core GPU architecture.” 2013. Web. 10 Apr 2021.
Vancouver:
Tang E. Design exploration of multi-core GPU architecture. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-135037.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Tang E. Design exploration of multi-core GPU architecture. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-135037
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
26. Wu, Pu-Cheng. Implementation of Low Power Multi-Port Memory and Itâs Applications in Graphic Processing Units.
Degree: Master, Computer Science and Engineering, 2013, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-170119
Subjects/Keywords: body-bias; mixed-signal design flow; vertex shader processor; power-gating; low-leakage design; multi-port SRAM
Record Details
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Wu, P. (2013). Implementation of Low Power Multi-Port Memory and Itâs Applications in Graphic Processing Units. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-170119
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Wu, Pu-Cheng. “Implementation of Low Power Multi-Port Memory and Itâs Applications in Graphic Processing Units.” 2013. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-170119.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Wu, Pu-Cheng. “Implementation of Low Power Multi-Port Memory and Itâs Applications in Graphic Processing Units.” 2013. Web. 10 Apr 2021.
Vancouver:
Wu P. Implementation of Low Power Multi-Port Memory and Itâs Applications in Graphic Processing Units. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-170119.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Wu P. Implementation of Low Power Multi-Port Memory and Itâs Applications in Graphic Processing Units. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-170119
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
27. Chi, Ya-Hsiu. Design and Analysis of A New Cache to Support Performance Degradation Tolerance.
Degree: Master, Electrical Engineering, 2013, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810113-160440
Subjects/Keywords: performance degrading fault; performance degradation tolerance; fault tolerance; cache; functionality fault; performance fault
Record Details
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Chi, Y. (2013). Design and Analysis of A New Cache to Support Performance Degradation Tolerance. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810113-160440
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Chi, Ya-Hsiu. “Design and Analysis of A New Cache to Support Performance Degradation Tolerance.” 2013. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810113-160440.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Chi, Ya-Hsiu. “Design and Analysis of A New Cache to Support Performance Degradation Tolerance.” 2013. Web. 10 Apr 2021.
Vancouver:
Chi Y. Design and Analysis of A New Cache to Support Performance Degradation Tolerance. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810113-160440.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Chi Y. Design and Analysis of A New Cache to Support Performance Degradation Tolerance. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810113-160440
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
28. Lu, Tzu-yi. Software Implementation of A Unified Behavior Model Design.
Degree: Master, Electrical Engineering, 2013, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812113-154338
Subjects/Keywords: behavioral model; design representation; parser; modeling; requirement analysis
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Lu, T. (2013). Software Implementation of A Unified Behavior Model Design. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812113-154338
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Lu, Tzu-yi. “Software Implementation of A Unified Behavior Model Design.” 2013. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812113-154338.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Lu, Tzu-yi. “Software Implementation of A Unified Behavior Model Design.” 2013. Web. 10 Apr 2021.
Vancouver:
Lu T. Software Implementation of A Unified Behavior Model Design. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812113-154338.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Lu T. Software Implementation of A Unified Behavior Model Design. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812113-154338
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
29. Wu, Chien-chan. Software Implementation of a Configurable Design of Interconnection Routers.
Degree: Master, Electrical Engineering, 2013, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622113-175410
Subjects/Keywords: system design; configurable design; router; automatic generation
Record Details
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Wu, C. (2013). Software Implementation of a Configurable Design of Interconnection Routers. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622113-175410
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Wu, Chien-chan. “Software Implementation of a Configurable Design of Interconnection Routers.” 2013. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622113-175410.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Wu, Chien-chan. “Software Implementation of a Configurable Design of Interconnection Routers.” 2013. Web. 10 Apr 2021.
Vancouver:
Wu C. Software Implementation of a Configurable Design of Interconnection Routers. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622113-175410.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Wu C. Software Implementation of a Configurable Design of Interconnection Routers. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622113-175410
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
30. Wu, Cheng-tao. Software Implementation of a Configurable Design of Control Units of Pipeline Processors.
Degree: Master, Electrical Engineering, 2014, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-151336
Subjects/Keywords: Verilog; computer aided design; architecture description language; controller; pipeline processor
Record Details
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Wu, C. (2014). Software Implementation of a Configurable Design of Control Units of Pipeline Processors. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-151336
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Wu, Cheng-tao. “Software Implementation of a Configurable Design of Control Units of Pipeline Processors.” 2014. Thesis, NSYSU. Accessed April 10, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-151336.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Wu, Cheng-tao. “Software Implementation of a Configurable Design of Control Units of Pipeline Processors.” 2014. Web. 10 Apr 2021.
Vancouver:
Wu C. Software Implementation of a Configurable Design of Control Units of Pipeline Processors. [Internet] [Thesis]. NSYSU; 2014. [cited 2021 Apr 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-151336.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Wu C. Software Implementation of a Configurable Design of Control Units of Pipeline Processors. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-151336
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation