+publisher:"NSYSU" +contributor:("Shen-Fu Hsiao")

NSYSU

1. Hung, Tsz-En. A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820117-170503

► The graphics processing units (GPUs) commonly used in mobile devices differ from those used in PCs, owing to cost and power constraints. Some embedded GPUs… (more)

Subjects/Keywords: GPU; Tile based rendering; Billboard textures; GPU memory modeling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Hung, T. (2017). A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820117-170503

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hung, Tsz-En. “A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs.” 2017. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820117-170503.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hung, Tsz-En. “A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs.” 2017. Web. 16 Dec 2019.

Vancouver:

Hung T. A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820117-170503.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hung T. A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820117-170503

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

2. Weng, Chia-Yang. Design Optimization of Hardware Function Evaluation Units with Truncated Multipliers and Squarers.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629117-231250

► Function evaluation is an important operation in the design of special function unit in graphics processing unit (GPU) and other applications in stereo vision and… (more)

Subjects/Keywords: function evaluation; polynomial approximation; uniform segmentation; digital arithmetic; truncated multiplier; truncated squarer

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Weng, C. (2017). Design Optimization of Hardware Function Evaluation Units with Truncated Multipliers and Squarers. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629117-231250

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Weng, Chia-Yang. “Design Optimization of Hardware Function Evaluation Units with Truncated Multipliers and Squarers.” 2017. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629117-231250.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Weng, Chia-Yang. “Design Optimization of Hardware Function Evaluation Units with Truncated Multipliers and Squarers.” 2017. Web. 16 Dec 2019.

Vancouver:

Weng C. Design Optimization of Hardware Function Evaluation Units with Truncated Multipliers and Squarers. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629117-231250.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Weng C. Design Optimization of Hardware Function Evaluation Units with Truncated Multipliers and Squarers. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629117-231250

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

3. Liu, Yun-Shen. A ROM-less DDFS with Curvature Non-equal Division Parabolic Polynomial Interpolation Method and Frequency-Shift Readout Circuit for Marijuana Rapid Quantitative Test Microsystem.

Degree: Master, Electrical Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806117-150925

► This thesis was motivated by an MOST-sponsored project, âHighly Sensitive Microsystem for Marijuana Rapid Quantitative Testâ, where a frequency-shift readout circuit is required to carry… (more)

Subjects/Keywords: resonant frequency; SFDR; frequency-shift readout circuit; FPW; DDFS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Liu, Y. (2017). A ROM-less DDFS with Curvature Non-equal Division Parabolic Polynomial Interpolation Method and Frequency-Shift Readout Circuit for Marijuana Rapid Quantitative Test Microsystem. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806117-150925

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Liu, Yun-Shen. “A ROM-less DDFS with Curvature Non-equal Division Parabolic Polynomial Interpolation Method and Frequency-Shift Readout Circuit for Marijuana Rapid Quantitative Test Microsystem.” 2017. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806117-150925.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Liu, Yun-Shen. “A ROM-less DDFS with Curvature Non-equal Division Parabolic Polynomial Interpolation Method and Frequency-Shift Readout Circuit for Marijuana Rapid Quantitative Test Microsystem.” 2017. Web. 16 Dec 2019.

Vancouver:

Liu Y. A ROM-less DDFS with Curvature Non-equal Division Parabolic Polynomial Interpolation Method and Frequency-Shift Readout Circuit for Marijuana Rapid Quantitative Test Microsystem. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806117-150925.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu Y. A ROM-less DDFS with Curvature Non-equal Division Parabolic Polynomial Interpolation Method and Frequency-Shift Readout Circuit for Marijuana Rapid Quantitative Test Microsystem. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806117-150925

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

4. Ho, Zong-Ying. LED Control Chip with Process-recognized Valley Detector Applied in High Efficiency Flyback Conveter Systems.

Degree: Master, Electrical Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806117-153041

► Although conventional LED drivers might be realized with different structures, we select Flyback converter design as the research topic in this thesis, The reason is… (more)

▼ Although conventional LED drivers might be realized with different structures, we select Flyback converter design as the research topic in this thesis, The reason is that not only it provides the stability of the output current, but also meets certain safety requirement.The purpose of the proposed Flyback control chip is to achieve quasi-resonant boundary conduction and provide stable current regulation. Thus, the proposed design comprises load output current estimation circuit, diode conduction time detection circuit,and pulse width modulation control circuit to generate a switch signal. Besides, the stability is analyzed and a compensation circuit is proposed to filter out unnecessary noise and reduce the ripple coupled in the output. In order to achieve the quasi-resonant mode control, the accuracy of Valley Detector is very important. When the secondary side inductor current can no longer be supplied to the load, it will cause oscillation between parasitic capacitance of the primary inductor and the power transistor. As soon as the valid valley is detected, an enable signal is delivered to PWM circuit to determine the turn-on time of the power transistor. However, the valley signal is hard to be detected accurately. The worst scenario is that the wrong detection will cause that the power transistor can no longer be turned on. Therefore, a protection circuit is proposed to prevent the case and improve the accuracy such that the efficiency is enhanced. Regarding the chip process variation, a detection circuit is added, which output is used to compensate the phase margin of the operational amplifier. The output voltage range of the LED driver based on the proposed design is 6 to 60 V, where LEDs are driven by a fixed 0.7 A with a single stage power factor corrector. As a result, it can achieve the maximum efficiency 92.61% given four LED loads. Advisors/Committee Members: Chua-Chin Wang (committee member), Ya-Hsin, Hsueh (chair), Fu%20Hsiao%22%29&pagesize-30">Shen-Fu Hsiao (chair), Chiu, Jih-Ching (chair).

Subjects/Keywords: flyback converter; LED; valley detection; process detection; PWM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Ho, Z. (2017). LED Control Chip with Process-recognized Valley Detector Applied in High Efficiency Flyback Conveter Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806117-153041

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Ho, Zong-Ying. “LED Control Chip with Process-recognized Valley Detector Applied in High Efficiency Flyback Conveter Systems.” 2017. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806117-153041.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Ho, Zong-Ying. “LED Control Chip with Process-recognized Valley Detector Applied in High Efficiency Flyback Conveter Systems.” 2017. Web. 16 Dec 2019.

Vancouver:

Ho Z. LED Control Chip with Process-recognized Valley Detector Applied in High Efficiency Flyback Conveter Systems. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806117-153041.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ho Z. LED Control Chip with Process-recognized Valley Detector Applied in High Efficiency Flyback Conveter Systems. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806117-153041

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

5. Hsiao, Bo-chien. FPGA Implementations of Real Time 3D Stereo Matching Based on Dynamic Programming.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0722117-115932

► Stereo vision is widely used in many computer vision applications including games, autonomous driving, object recognition, etc. Depth is the key information in stereo vision.… (more)

Subjects/Keywords: image rectification; dynamic programming; depth map; stereo matching; FPGA; stereo vision

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Hsiao, B. (2017). FPGA Implementations of Real Time 3D Stereo Matching Based on Dynamic Programming. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0722117-115932

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hsiao, Bo-chien. “FPGA Implementations of Real Time 3D Stereo Matching Based on Dynamic Programming.” 2017. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0722117-115932.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hsiao, Bo-chien. “FPGA Implementations of Real Time 3D Stereo Matching Based on Dynamic Programming.” 2017. Web. 16 Dec 2019.

Vancouver:

Hsiao B. FPGA Implementations of Real Time 3D Stereo Matching Based on Dynamic Programming. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0722117-115932.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsiao B. FPGA Implementations of Real Time 3D Stereo Matching Based on Dynamic Programming. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0722117-115932

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

6. You, Tz-Heng. Design of Low-Cost HOG and Its Application to Pedestrian Detection in ADAS.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725117-173711

► This thesis presents two versions of simplifications, Gradient Comprison HOG (GC-HOG) and Simplified HOG (S-HOG) for Histograms of Oriented Gradients (HOG), a feature extraction algorithm… (more)

Subjects/Keywords: FPGA; Hardware Design; Pedestrian Detection; ADAS; HOG

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

You, T. (2017). Design of Low-Cost HOG and Its Application to Pedestrian Detection in ADAS. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725117-173711

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

You, Tz-Heng. “Design of Low-Cost HOG and Its Application to Pedestrian Detection in ADAS.” 2017. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725117-173711.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

You, Tz-Heng. “Design of Low-Cost HOG and Its Application to Pedestrian Detection in ADAS.” 2017. Web. 16 Dec 2019.

Vancouver:

You T. Design of Low-Cost HOG and Its Application to Pedestrian Detection in ADAS. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725117-173711.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

You T. Design of Low-Cost HOG and Its Application to Pedestrian Detection in ADAS. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725117-173711

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

7. Tsai, Chen-Yen. Architecture Design and Hardware Implementation of LK Optical Flow.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725117-173553

► Due to rapid advances of machine learning and computer vision, object track recognition and tracking are fundamental technologies in many applications, including the popular advanced… (more)

Subjects/Keywords: Computer vision; LK optical flow; Moving object tracking; Pyramid optical flow; Hardware implementation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Tsai, C. (2017). Architecture Design and Hardware Implementation of LK Optical Flow. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725117-173553

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Tsai, Chen-Yen. “Architecture Design and Hardware Implementation of LK Optical Flow.” 2017. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725117-173553.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Tsai, Chen-Yen. “Architecture Design and Hardware Implementation of LK Optical Flow.” 2017. Web. 16 Dec 2019.

Vancouver:

Tsai C. Architecture Design and Hardware Implementation of LK Optical Flow. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725117-173553.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsai C. Architecture Design and Hardware Implementation of LK Optical Flow. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725117-173553

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

8. Chang, Chih-hsuan. Hardware Design of Stereo Matching Based on Guided Image Filtering.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-232935

► Stereo vision has many applications, including 3D movies and the recent advanced driver assisted systems (ADAS). In stereo vision, stereo matching of generating depth information… (more)

Subjects/Keywords: stereo vision; stereo matching; depth information; mean filtering; guided image filtering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chang, C. (2017). Hardware Design of Stereo Matching Based on Guided Image Filtering. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-232935

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chang, Chih-hsuan. “Hardware Design of Stereo Matching Based on Guided Image Filtering.” 2017. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-232935.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chang, Chih-hsuan. “Hardware Design of Stereo Matching Based on Guided Image Filtering.” 2017. Web. 16 Dec 2019.

Vancouver:

Chang C. Hardware Design of Stereo Matching Based on Guided Image Filtering. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-232935.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang C. Hardware Design of Stereo Matching Based on Guided Image Filtering. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-232935

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

9. Liang, Hsiang-Hao. Design of Low-Power and Dynamically Reconfigurable Multi-Precision Special Function Units.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-224433

► Computation of special functions is widely used in many applications such as stereo vision, image processing, and communication. Piecewise polynomial approximation (PPA) is usually adopted… (more)

Subjects/Keywords: polynomial approximation; multi-precision; special function unit; digital arithmetic; function evaluation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Liang, H. (2017). Design of Low-Power and Dynamically Reconfigurable Multi-Precision Special Function Units. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-224433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Liang, Hsiang-Hao. “Design of Low-Power and Dynamically Reconfigurable Multi-Precision Special Function Units.” 2017. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-224433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Liang, Hsiang-Hao. “Design of Low-Power and Dynamically Reconfigurable Multi-Precision Special Function Units.” 2017. Web. 16 Dec 2019.

Vancouver:

Liang H. Design of Low-Power and Dynamically Reconfigurable Multi-Precision Special Function Units. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-224433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liang H. Design of Low-Power and Dynamically Reconfigurable Multi-Precision Special Function Units. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-224433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

10. Chen, Xiang-Jun. User Designable Interactive Artificial Aquarium with Leap Motion.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806117-093656

► Today, we have many kinds of the 3C device like smart phone or notebook. We use these for work, communication, and entertainment. In the past… (more)

Subjects/Keywords: Artificial fish; Leap motion; Hand tracking; Artificial Intelligence; Aquarium

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APA (6^th Edition):

Chen, X. (2017). User Designable Interactive Artificial Aquarium with Leap Motion. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806117-093656

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chen, Xiang-Jun. “User Designable Interactive Artificial Aquarium with Leap Motion.” 2017. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806117-093656.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chen, Xiang-Jun. “User Designable Interactive Artificial Aquarium with Leap Motion.” 2017. Web. 16 Dec 2019.

Vancouver:

Chen X. User Designable Interactive Artificial Aquarium with Leap Motion. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806117-093656.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen X. User Designable Interactive Artificial Aquarium with Leap Motion. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806117-093656

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

11. Chang, Jia-hao. Design of Tessellation Unit for 3D Graphic Processor.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407

► Tessellation shader is one of the advanced graphics rendering functions supported in state-of-the-art graphics standard applications programming interfaces such as OpenGL 4.x and DirextX 11.… (more)

Subjects/Keywords: tessellation; tessellation primitive generation; OpenGL 4.x; tessellation unit; primitive assembly unit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chang, J. (2017). Design of Tessellation Unit for 3D Graphic Processor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chang, Jia-hao. “Design of Tessellation Unit for 3D Graphic Processor.” 2017. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chang, Jia-hao. “Design of Tessellation Unit for 3D Graphic Processor.” 2017. Web. 16 Dec 2019.

Vancouver:

Chang J. Design of Tessellation Unit for 3D Graphic Processor. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang J. Design of Tessellation Unit for 3D Graphic Processor. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

12. Lee, Hsin-mau. Designs, Implementations and Applications of Floating-Point Trigonometric Function Units.

Degree: Master, Computer Science and Engineering, 2008, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251

► In addition to the previous pipelined floating-point CORDIC design, three different architectures supporting both CORDIC rotation mode and vectoring mode are proposed in this thesis.… (more)

Subjects/Keywords: Floating-point; CORDIC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lee, H. (2008). Designs, Implementations and Applications of Floating-Point Trigonometric Function Units. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lee, Hsin-mau. “Designs, Implementations and Applications of Floating-Point Trigonometric Function Units.” 2008. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lee, Hsin-mau. “Designs, Implementations and Applications of Floating-Point Trigonometric Function Units.” 2008. Web. 16 Dec 2019.

Vancouver:

Lee H. Designs, Implementations and Applications of Floating-Point Trigonometric Function Units. [Internet] [Thesis]. NSYSU; 2008. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee H. Designs, Implementations and Applications of Floating-Point Trigonometric Function Units. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

13. Lin, Wei-Sen. Design of Unified Arithmetic Units for 3D Graphics Vertex Shader.

Degree: Master, Computer Science and Engineering, 2008, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-114207

► Vertex shader, one of the core parts in 3D graphics systems, is to speed up the operations of coordinate transformation and lighting in 3D graphics… (more)

Subjects/Keywords: Vertex Shader; higher-order approximation; throughput of the matrix computation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lin, W. (2008). Design of Unified Arithmetic Units for 3D Graphics Vertex Shader. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-114207

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lin, Wei-Sen. “Design of Unified Arithmetic Units for 3D Graphics Vertex Shader.” 2008. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-114207.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lin, Wei-Sen. “Design of Unified Arithmetic Units for 3D Graphics Vertex Shader.” 2008. Web. 16 Dec 2019.

Vancouver:

Lin W. Design of Unified Arithmetic Units for 3D Graphics Vertex Shader. [Internet] [Thesis]. NSYSU; 2008. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-114207.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin W. Design of Unified Arithmetic Units for 3D Graphics Vertex Shader. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-114207

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

14. Liu, Yi-cheng. Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell.

Degree: Master, Electrical Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501

► The thesis is composed of tow topics: a fully bidirectional mixed- voltage-tolerant I/O cell using a new output stage circuit and a sub-3ÃVDD wide range… (more)

Subjects/Keywords: I/O cell; Mixed-Voltage-Tolerant; Dynamic Biasing; Sub 3ÃVDD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Liu, Y. (2009). Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Liu, Yi-cheng. “Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell.” 2009. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Liu, Yi-cheng. “Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell.” 2009. Web. 16 Dec 2019.

Vancouver:

Liu Y. Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell. [Internet] [Thesis]. NSYSU; 2009. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu Y. Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

15. Yen, Shao-Fu. A Charger Circuit of Li-ion Batteries and a Capacitor-less LDO for Wireless Biomedical Systems.

Degree: Master, Electrical Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706109-135451

► The thesis is composed of two topics : a charger circuit of Li-ion batteries for wireless biomedical systems and a capacitor-less low dropout regulatorï¼LDOï¼. The… (more)

Subjects/Keywords: regulator; capacitor-less; Li-ion; ldo; biomedical

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Yen, S. (2009). A Charger Circuit of Li-ion Batteries and a Capacitor-less LDO for Wireless Biomedical Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706109-135451

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Yen, Shao-Fu. “A Charger Circuit of Li-ion Batteries and a Capacitor-less LDO for Wireless Biomedical Systems.” 2009. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706109-135451.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Yen, Shao-Fu. “A Charger Circuit of Li-ion Batteries and a Capacitor-less LDO for Wireless Biomedical Systems.” 2009. Web. 16 Dec 2019.

Vancouver:

Yen S. A Charger Circuit of Li-ion Batteries and a Capacitor-less LDO for Wireless Biomedical Systems. [Internet] [Thesis]. NSYSU; 2009. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706109-135451.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yen S. A Charger Circuit of Li-ion Batteries and a Capacitor-less LDO for Wireless Biomedical Systems. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706109-135451

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

16. Lai, Yu-ren. Design of the Superscalar Dual-Core Architecture using Single-Issue Out-of-Order Instruction Pipe for Embedded System.

Degree: Master, Electrical Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729109-173040

► With the improvement in VLSI technology, realization of multiple processor cores on a single chip becomes easier. Therefore, more and more users execute applications on… (more)

▼ With the improvement in VLSI technology, realization of multiple processor cores on a single chip becomes easier. Therefore, more and more users execute applications on current multi-core architectures. The multi-core system has a brilliant performance in executing multi-threaded applications, but this system could not gain any performance in single-threaded applications. This paper proposes a multi-core architecture for enhancing single-threaded performance in embedded system, and focuses on four points: 1. Construct a simple out-of-order execution core. 2. Design a dynamically scheduled instruction analyzer. 3. Design a mechanism for sharing operands between two cores. 4. Design a mechanism for committing instructions synchronously between two cores. The architecture of each core is single-issue out-of-order instruction pipe. First, instruction analyzer will fetch instructions and generate instruction dependence tags by detecting the dependencies among the fetched instructions, then schedule instructions dynamically and dispatch to the cores. In the core, instructions can know where to get required operands according to the information of instruction tags, this mechanism enables data can be shared between two cores. Instructions are executed by data-driven approach, but in-order complete to maintain the correctness of the program order. Based on ARM instruction set, this paper tries to explore ways to achieve interaction control mechanisms between two cores and to accelerate a single-thread in the dual-core architecture. We write a simulation model of the proposed architecture in C language as our trace-driven simulation framework and the MediaBench suite is selected for the experiments. According simulation result, the architecture can obtain average 40% performance speedup comparing to the five-stage pipelined architecture. Advisors/Committee Members: Tsung Lee (chair), fu%20Hsiao%22%29&pagesize-30">Shen-fu Hsiao (chair), Jih-chin Chiu (committee member), Chung-ping Chung (chair).

Subjects/Keywords: Dual-Core; Superscalar; Embedded System; Out-of-Order; Single-Issue

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lai, Y. (2009). Design of the Superscalar Dual-Core Architecture using Single-Issue Out-of-Order Instruction Pipe for Embedded System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729109-173040

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lai, Yu-ren. “Design of the Superscalar Dual-Core Architecture using Single-Issue Out-of-Order Instruction Pipe for Embedded System.” 2009. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729109-173040.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lai, Yu-ren. “Design of the Superscalar Dual-Core Architecture using Single-Issue Out-of-Order Instruction Pipe for Embedded System.” 2009. Web. 16 Dec 2019.

Vancouver:

Lai Y. Design of the Superscalar Dual-Core Architecture using Single-Issue Out-of-Order Instruction Pipe for Embedded System. [Internet] [Thesis]. NSYSU; 2009. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729109-173040.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lai Y. Design of the Superscalar Dual-Core Architecture using Single-Issue Out-of-Order Instruction Pipe for Embedded System. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729109-173040

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

17. Wu, Zong-Lin. Low-Overhead Isolation Cells for Low-Power Multipliers.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550

► With the rapid progress in manufacturing technology, the chip design is more and more complicated day by day. As a result, the circuit design with… (more)

Subjects/Keywords: low overhead isolation cell; standard cell; low-power multipliers

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APA (6^th Edition):

Wu, Z. (2009). Low-Overhead Isolation Cells for Low-Power Multipliers. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wu, Zong-Lin. “Low-Overhead Isolation Cells for Low-Power Multipliers.” 2009. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wu, Zong-Lin. “Low-Overhead Isolation Cells for Low-Power Multipliers.” 2009. Web. 16 Dec 2019.

Vancouver:

Wu Z. Low-Overhead Isolation Cells for Low-Power Multipliers. [Internet] [Thesis]. NSYSU; 2009. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu Z. Low-Overhead Isolation Cells for Low-Power Multipliers. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

18. Lin, Ching-Yuan. Performance Modeling for a 3D Graphics SoC.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522

► The design of SoC is growing into more complicated, hence it is necessary to determine an efficient way to develop an SoC. If we can… (more)

Subjects/Keywords: 3D Graphics; Tile-based; analysis; SystemC; TLM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lin, C. (2009). Performance Modeling for a 3D Graphics SoC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lin, Ching-Yuan. “Performance Modeling for a 3D Graphics SoC.” 2009. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lin, Ching-Yuan. “Performance Modeling for a 3D Graphics SoC.” 2009. Web. 16 Dec 2019.

Vancouver:

Lin C. Performance Modeling for a 3D Graphics SoC. [Internet] [Thesis]. NSYSU; 2009. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin C. Performance Modeling for a 3D Graphics SoC. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

19. Lin, Tzu-chun. Implementation of Action Recognition Algorithm on Multiple-Streaming Multimedia Unit.

Degree: Master, Electrical Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803110-142110

► Action recognition had become prosperous in development and been broadly applied in several sectors. From homeland security, personal property, home caring, even the smart environment… (more)

Subjects/Keywords: SIMD; Action Recognition; Embedded computer vision; MMX; Streaming Processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lin, T. (2010). Implementation of Action Recognition Algorithm on Multiple-Streaming Multimedia Unit. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803110-142110

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lin, Tzu-chun. “Implementation of Action Recognition Algorithm on Multiple-Streaming Multimedia Unit.” 2010. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803110-142110.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lin, Tzu-chun. “Implementation of Action Recognition Algorithm on Multiple-Streaming Multimedia Unit.” 2010. Web. 16 Dec 2019.

Vancouver:

Lin T. Implementation of Action Recognition Algorithm on Multiple-Streaming Multimedia Unit. [Internet] [Thesis]. NSYSU; 2010. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803110-142110.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin T. Implementation of Action Recognition Algorithm on Multiple-Streaming Multimedia Unit. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803110-142110

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

20. Lei, Kin-fong. Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems.

Degree: Master, Electrical Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743

► In the multi-core systems, the data transfer between cores becomes a major challenge. The on-chip interconnect networks should be low latency, high throughput, scalability, better… (more)

Subjects/Keywords: On-Chip Interconnect Networks; Asynchronous Ring Bus; Multi-Core Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lei, K. (2010). Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lei, Kin-fong. “Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems.” 2010. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lei, Kin-fong. “Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems.” 2010. Web. 16 Dec 2019.

Vancouver:

Lei K. Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems. [Internet] [Thesis]. NSYSU; 2010. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lei K. Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

21. Lee, Cheng-Han. Design, Analysis and Applications of Hybrid CORDIC Processor Architectures.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513

► In this thesis, we propose different CORDIC architectures which solve the problems of long-latency in traditional pipeline CORDIC and the large-area cost in table-based CORDIC.… (more)

Subjects/Keywords: Arithmetic Function Units; CORDIC; Taylor-series expansion

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lee, C. (2010). Design, Analysis and Applications of Hybrid CORDIC Processor Architectures. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lee, Cheng-Han. “Design, Analysis and Applications of Hybrid CORDIC Processor Architectures.” 2010. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lee, Cheng-Han. “Design, Analysis and Applications of Hybrid CORDIC Processor Architectures.” 2010. Web. 16 Dec 2019.

Vancouver:

Lee C. Design, Analysis and Applications of Hybrid CORDIC Processor Architectures. [Internet] [Thesis]. NSYSU; 2010. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee C. Design, Analysis and Applications of Hybrid CORDIC Processor Architectures. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

22. Tsai, Cheng-Hsuan. Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704

► The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, various new logic circuit design styles based on… (more)

Subjects/Keywords: CMOS logic; Logic Synthesizer; Standard Cell Library; ASIC Design Flow; Pass-Transition-Logic(PTL)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Tsai, C. (2010). Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Tsai, Cheng-Hsuan. “Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library.” 2010. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Tsai, Cheng-Hsuan. “Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library.” 2010. Web. 16 Dec 2019.

Vancouver:

Tsai C. Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library. [Internet] [Thesis]. NSYSU; 2010. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsai C. Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

23. Chiu, Chan-Feng. Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101

► This thesis focuses on efficient design of a vertex shader for per-vertex operations such as Transformation and Lighting in the OpenGL ES 2.0 graphics pipeline.… (more)

Subjects/Keywords: 3D Graph; Logarithmic Number System; Vertex Shader

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chiu, C. (2010). Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chiu, Chan-Feng. “Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System.” 2010. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chiu, Chan-Feng. “Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System.” 2010. Web. 16 Dec 2019.

Vancouver:

Chiu C. Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System. [Internet] [Thesis]. NSYSU; 2010. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chiu C. Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

24. Chen, Li-Yao. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

► OpenGL ES 2.0 programmable 3D graphics pipeline is the current new standard for embedded graphics processor designs. The programmable vertex shader replaces the geometry operations… (more)

Subjects/Keywords: Integration; SOC; Programmable; SIMD; Vertex Shader

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chen, L. (2010). Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chen, Li-Yao. “Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.” 2010. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chen, Li-Yao. “Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.” 2010. Web. 16 Dec 2019.

Vancouver:

Chen L. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. [Internet] [Thesis]. NSYSU; 2010. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen L. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

25. Wu, Yi-hong. A 16-channel High-Voltage Stimulation Generator and A Pulse Frequency Modulation Boost Converter for Spinal Cord Stimulation Systems.

Degree: Master, Electrical Engineering, 2013, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114950

► This thesis consists of two topics, i.e., a 16-channel high-voltage stimulation generator and a pulse frequency modulation (PFM) boost converter, which are mainly designed for… (more)

Subjects/Keywords: stimulation waveform generator; current-limiting; minimum off time one-shot circuit; PFM boost converter; SCS

Record Details Similar Records Cite « Share

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Wu, Y. (2013). A 16-channel High-Voltage Stimulation Generator and A Pulse Frequency Modulation Boost Converter for Spinal Cord Stimulation Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114950

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wu, Yi-hong. “A 16-channel High-Voltage Stimulation Generator and A Pulse Frequency Modulation Boost Converter for Spinal Cord Stimulation Systems.” 2013. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114950.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wu, Yi-hong. “A 16-channel High-Voltage Stimulation Generator and A Pulse Frequency Modulation Boost Converter for Spinal Cord Stimulation Systems.” 2013. Web. 16 Dec 2019.

Vancouver:

Wu Y. A 16-channel High-Voltage Stimulation Generator and A Pulse Frequency Modulation Boost Converter for Spinal Cord Stimulation Systems. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114950.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu Y. A 16-channel High-Voltage Stimulation Generator and A Pulse Frequency Modulation Boost Converter for Spinal Cord Stimulation Systems. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114950

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

26. Chen, Sih-Yu. Single-ended Disturb-free 5T Load-less 4Kb SRAM with Leakage Current Sensor and Compensation Circuit.

Degree: Master, Electrical Engineering, 2013, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114220

► This thesis consists of two topics, including a single-ended disturb-free 5T load-less 4Kb SRAM, and the leakage current sensor and compensation circuit mainly designed for… (more)

Subjects/Keywords: single-ended; leakage current sensor; power-delay product; load-less; disturb-free; leakage current compensation circuit

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chen, S. (2013). Single-ended Disturb-free 5T Load-less 4Kb SRAM with Leakage Current Sensor and Compensation Circuit. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114220

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chen, Sih-Yu. “Single-ended Disturb-free 5T Load-less 4Kb SRAM with Leakage Current Sensor and Compensation Circuit.” 2013. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114220.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chen, Sih-Yu. “Single-ended Disturb-free 5T Load-less 4Kb SRAM with Leakage Current Sensor and Compensation Circuit.” 2013. Web. 16 Dec 2019.

Vancouver:

Chen S. Single-ended Disturb-free 5T Load-less 4Kb SRAM with Leakage Current Sensor and Compensation Circuit. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114220.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen S. Single-ended Disturb-free 5T Load-less 4Kb SRAM with Leakage Current Sensor and Compensation Circuit. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114220

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

27. Wu, Po-han. Table Size Reduction and Optimization in Multiplierless Table-Based Function Evaluation Designs.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631113-083045

► In hardware design of the elementary function evaluation, Table-lookup-and-addition method is a category of multiplier-less method, based on several lookup tables and a multi-operand adder… (more)

Subjects/Keywords: compress-tree; error-analysis; look-up-table-and-add; multiplier-less function evaluation method; elementary function evaluation method

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Wu, P. (2013). Table Size Reduction and Optimization in Multiplierless Table-Based Function Evaluation Designs. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631113-083045

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wu, Po-han. “Table Size Reduction and Optimization in Multiplierless Table-Based Function Evaluation Designs.” 2013. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631113-083045.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wu, Po-han. “Table Size Reduction and Optimization in Multiplierless Table-Based Function Evaluation Designs.” 2013. Web. 16 Dec 2019.

Vancouver:

Wu P. Table Size Reduction and Optimization in Multiplierless Table-Based Function Evaluation Designs. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631113-083045.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu P. Table Size Reduction and Optimization in Multiplierless Table-Based Function Evaluation Designs. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631113-083045

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

28. Huang, Jun-ming. Hardware Design of Disparity Estimation Using Belief Propagation.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727113-103923

► Stereo vision is widely used in 3D graphics applications. Depth map, an important information in stereo vision, can be generated using stereo matching. In general,… (more)

Subjects/Keywords: Markov random field; belief propagation; disparity computation; depth map; stereo matching; stereo vision

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Huang, J. (2013). Hardware Design of Disparity Estimation Using Belief Propagation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727113-103923

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Huang, Jun-ming. “Hardware Design of Disparity Estimation Using Belief Propagation.” 2013. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727113-103923.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Huang, Jun-ming. “Hardware Design of Disparity Estimation Using Belief Propagation.” 2013. Web. 16 Dec 2019.

Vancouver:

Huang J. Hardware Design of Disparity Estimation Using Belief Propagation. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727113-103923.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang J. Hardware Design of Disparity Estimation Using Belief Propagation. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727113-103923

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

29. Huang, Chih-Hong. Hardware Design of Multi-view 3D Stereo Synthesizers Based on Two Image Sequences.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-151411

► Standared 3D stereo showing images at different view positions requires images captured from various view angles and thus needs large transmission bandwidth. In this thesis,… (more)

Subjects/Keywords: stereo matching; hole filling; image warping; disparity estimation; depth-image-based rendering (DIBR); multiview virtual images

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Huang, C. (2013). Hardware Design of Multi-view 3D Stereo Synthesizers Based on Two Image Sequences. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-151411

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Huang, Chih-Hong. “Hardware Design of Multi-view 3D Stereo Synthesizers Based on Two Image Sequences.” 2013. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-151411.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Huang, Chih-Hong. “Hardware Design of Multi-view 3D Stereo Synthesizers Based on Two Image Sequences.” 2013. Web. 16 Dec 2019.

Vancouver:

Huang C. Hardware Design of Multi-view 3D Stereo Synthesizers Based on Two Image Sequences. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-151411.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang C. Hardware Design of Multi-view 3D Stereo Synthesizers Based on Two Image Sequences. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-151411

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

30. Wu, Pu-Cheng. Implementation of Low Power Multi-Port Memory and Itâs Applications in Graphic Processing Units.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-170119

► Memory design plays an important role in current system-on-chip (SoC) design because memory takes a significant portion of total area. As the complexity of processor… (more)

Subjects/Keywords: body-bias; mixed-signal design flow; vertex shader processor; power-gating; low-leakage design; multi-port SRAM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Wu, P. (2013). Implementation of Low Power Multi-Port Memory and Itâs Applications in Graphic Processing Units. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-170119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wu, Pu-Cheng. “Implementation of Low Power Multi-Port Memory and Itâs Applications in Graphic Processing Units.” 2013. Thesis, NSYSU. Accessed December 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-170119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wu, Pu-Cheng. “Implementation of Low Power Multi-Port Memory and Itâs Applications in Graphic Processing Units.” 2013. Web. 16 Dec 2019.

Vancouver:

Wu P. Implementation of Low Power Multi-Port Memory and Itâs Applications in Graphic Processing Units. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Dec 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-170119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu P. Implementation of Low Power Multi-Port Memory and Itâs Applications in Graphic Processing Units. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-170119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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Open Access Theses and Dissertations