+publisher:"NSYSU" +contributor:("Shen-Fu Hsiao")

NSYSU

1. Hung, Tsz-En. A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820117-170503

► The graphics processing units (GPUs) commonly used in mobile devices differ from those used in PCs, owing to cost and power constraints. Some embedded GPUs… (more)

Subjects/Keywords: GPU; Tile based rendering; Billboard textures; GPU memory modeling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Hung, T. (2017). A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820117-170503

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hung, Tsz-En. “A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs.” 2017. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820117-170503.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hung, Tsz-En. “A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs.” 2017. Web. 07 Mar 2021.

Vancouver:

Hung T. A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs. [Internet] [Thesis]. NSYSU; 2017. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820117-170503.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hung T. A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820117-170503

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

2. Lee, Hsin-mau. Designs, Implementations and Applications of Floating-Point Trigonometric Function Units.

Degree: Master, Computer Science and Engineering, 2008, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251

► In addition to the previous pipelined floating-point CORDIC design, three different architectures supporting both CORDIC rotation mode and vectoring mode are proposed in this thesis.… (more)

Subjects/Keywords: Floating-point; CORDIC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lee, H. (2008). Designs, Implementations and Applications of Floating-Point Trigonometric Function Units. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lee, Hsin-mau. “Designs, Implementations and Applications of Floating-Point Trigonometric Function Units.” 2008. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lee, Hsin-mau. “Designs, Implementations and Applications of Floating-Point Trigonometric Function Units.” 2008. Web. 07 Mar 2021.

Vancouver:

Lee H. Designs, Implementations and Applications of Floating-Point Trigonometric Function Units. [Internet] [Thesis]. NSYSU; 2008. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee H. Designs, Implementations and Applications of Floating-Point Trigonometric Function Units. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

3. Lin, Wei-Sen. Design of Unified Arithmetic Units for 3D Graphics Vertex Shader.

Degree: Master, Computer Science and Engineering, 2008, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-114207

► Vertex shader, one of the core parts in 3D graphics systems, is to speed up the operations of coordinate transformation and lighting in 3D graphics… (more)

Subjects/Keywords: Vertex Shader; higher-order approximation; throughput of the matrix computation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lin, W. (2008). Design of Unified Arithmetic Units for 3D Graphics Vertex Shader. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-114207

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lin, Wei-Sen. “Design of Unified Arithmetic Units for 3D Graphics Vertex Shader.” 2008. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-114207.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lin, Wei-Sen. “Design of Unified Arithmetic Units for 3D Graphics Vertex Shader.” 2008. Web. 07 Mar 2021.

Vancouver:

Lin W. Design of Unified Arithmetic Units for 3D Graphics Vertex Shader. [Internet] [Thesis]. NSYSU; 2008. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-114207.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin W. Design of Unified Arithmetic Units for 3D Graphics Vertex Shader. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-114207

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

4. Liu, Yi-cheng. Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell.

Degree: Master, Electrical Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501

► The thesis is composed of tow topics: a fully bidirectional mixed- voltage-tolerant I/O cell using a new output stage circuit and a sub-3ÃVDD wide range… (more)

Subjects/Keywords: I/O cell; Mixed-Voltage-Tolerant; Dynamic Biasing; Sub 3ÃVDD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Liu, Y. (2009). Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Liu, Yi-cheng. “Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell.” 2009. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Liu, Yi-cheng. “Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell.” 2009. Web. 07 Mar 2021.

Vancouver:

Liu Y. Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu Y. Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

5. Yen, Shao-Fu. A Charger Circuit of Li-ion Batteries and a Capacitor-less LDO for Wireless Biomedical Systems.

Degree: Master, Electrical Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706109-135451

► The thesis is composed of two topics : a charger circuit of Li-ion batteries for wireless biomedical systems and a capacitor-less low dropout regulatorï¼LDOï¼. The… (more)

Subjects/Keywords: regulator; capacitor-less; Li-ion; ldo; biomedical

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Yen, S. (2009). A Charger Circuit of Li-ion Batteries and a Capacitor-less LDO for Wireless Biomedical Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706109-135451

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Yen, Shao-Fu. “A Charger Circuit of Li-ion Batteries and a Capacitor-less LDO for Wireless Biomedical Systems.” 2009. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706109-135451.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Yen, Shao-Fu. “A Charger Circuit of Li-ion Batteries and a Capacitor-less LDO for Wireless Biomedical Systems.” 2009. Web. 07 Mar 2021.

Vancouver:

Yen S. A Charger Circuit of Li-ion Batteries and a Capacitor-less LDO for Wireless Biomedical Systems. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706109-135451.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yen S. A Charger Circuit of Li-ion Batteries and a Capacitor-less LDO for Wireless Biomedical Systems. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706109-135451

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

6. Lai, Yu-ren. Design of the Superscalar Dual-Core Architecture using Single-Issue Out-of-Order Instruction Pipe for Embedded System.

Degree: Master, Electrical Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729109-173040

► With the improvement in VLSI technology, realization of multiple processor cores on a single chip becomes easier. Therefore, more and more users execute applications on… (more)

▼ With the improvement in VLSI technology, realization of multiple processor cores on a single chip becomes easier. Therefore, more and more users execute applications on current multi-core architectures. The multi-core system has a brilliant performance in executing multi-threaded applications, but this system could not gain any performance in single-threaded applications. This paper proposes a multi-core architecture for enhancing single-threaded performance in embedded system, and focuses on four points: 1. Construct a simple out-of-order execution core. 2. Design a dynamically scheduled instruction analyzer. 3. Design a mechanism for sharing operands between two cores. 4. Design a mechanism for committing instructions synchronously between two cores. The architecture of each core is single-issue out-of-order instruction pipe. First, instruction analyzer will fetch instructions and generate instruction dependence tags by detecting the dependencies among the fetched instructions, then schedule instructions dynamically and dispatch to the cores. In the core, instructions can know where to get required operands according to the information of instruction tags, this mechanism enables data can be shared between two cores. Instructions are executed by data-driven approach, but in-order complete to maintain the correctness of the program order. Based on ARM instruction set, this paper tries to explore ways to achieve interaction control mechanisms between two cores and to accelerate a single-thread in the dual-core architecture. We write a simulation model of the proposed architecture in C language as our trace-driven simulation framework and the MediaBench suite is selected for the experiments. According simulation result, the architecture can obtain average 40% performance speedup comparing to the five-stage pipelined architecture. Advisors/Committee Members: Tsung Lee (chair), fu%20Hsiao%22%29&pagesize-30">Shen-fu Hsiao (chair), Jih-chin Chiu (committee member), Chung-ping Chung (chair).

Subjects/Keywords: Dual-Core; Superscalar; Embedded System; Out-of-Order; Single-Issue

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lai, Y. (2009). Design of the Superscalar Dual-Core Architecture using Single-Issue Out-of-Order Instruction Pipe for Embedded System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729109-173040

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lai, Yu-ren. “Design of the Superscalar Dual-Core Architecture using Single-Issue Out-of-Order Instruction Pipe for Embedded System.” 2009. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729109-173040.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lai, Yu-ren. “Design of the Superscalar Dual-Core Architecture using Single-Issue Out-of-Order Instruction Pipe for Embedded System.” 2009. Web. 07 Mar 2021.

Vancouver:

Lai Y. Design of the Superscalar Dual-Core Architecture using Single-Issue Out-of-Order Instruction Pipe for Embedded System. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729109-173040.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lai Y. Design of the Superscalar Dual-Core Architecture using Single-Issue Out-of-Order Instruction Pipe for Embedded System. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729109-173040

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

7. Wu, Zong-Lin. Low-Overhead Isolation Cells for Low-Power Multipliers.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550

► With the rapid progress in manufacturing technology, the chip design is more and more complicated day by day. As a result, the circuit design with… (more)

Subjects/Keywords: low overhead isolation cell; standard cell; low-power multipliers

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Wu, Z. (2009). Low-Overhead Isolation Cells for Low-Power Multipliers. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wu, Zong-Lin. “Low-Overhead Isolation Cells for Low-Power Multipliers.” 2009. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wu, Zong-Lin. “Low-Overhead Isolation Cells for Low-Power Multipliers.” 2009. Web. 07 Mar 2021.

Vancouver:

Wu Z. Low-Overhead Isolation Cells for Low-Power Multipliers. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu Z. Low-Overhead Isolation Cells for Low-Power Multipliers. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

8. Lin, Ching-Yuan. Performance Modeling for a 3D Graphics SoC.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522

► The design of SoC is growing into more complicated, hence it is necessary to determine an efficient way to develop an SoC. If we can… (more)

Subjects/Keywords: 3D Graphics; Tile-based; analysis; SystemC; TLM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lin, C. (2009). Performance Modeling for a 3D Graphics SoC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lin, Ching-Yuan. “Performance Modeling for a 3D Graphics SoC.” 2009. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lin, Ching-Yuan. “Performance Modeling for a 3D Graphics SoC.” 2009. Web. 07 Mar 2021.

Vancouver:

Lin C. Performance Modeling for a 3D Graphics SoC. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin C. Performance Modeling for a 3D Graphics SoC. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

9. Lin, Tzu-chun. Implementation of Action Recognition Algorithm on Multiple-Streaming Multimedia Unit.

Degree: Master, Electrical Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803110-142110

► Action recognition had become prosperous in development and been broadly applied in several sectors. From homeland security, personal property, home caring, even the smart environment… (more)

Subjects/Keywords: SIMD; Action Recognition; Embedded computer vision; MMX; Streaming Processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lin, T. (2010). Implementation of Action Recognition Algorithm on Multiple-Streaming Multimedia Unit. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803110-142110

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lin, Tzu-chun. “Implementation of Action Recognition Algorithm on Multiple-Streaming Multimedia Unit.” 2010. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803110-142110.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lin, Tzu-chun. “Implementation of Action Recognition Algorithm on Multiple-Streaming Multimedia Unit.” 2010. Web. 07 Mar 2021.

Vancouver:

Lin T. Implementation of Action Recognition Algorithm on Multiple-Streaming Multimedia Unit. [Internet] [Thesis]. NSYSU; 2010. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803110-142110.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin T. Implementation of Action Recognition Algorithm on Multiple-Streaming Multimedia Unit. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803110-142110

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

10. Lei, Kin-fong. Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems.

Degree: Master, Electrical Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743

► In the multi-core systems, the data transfer between cores becomes a major challenge. The on-chip interconnect networks should be low latency, high throughput, scalability, better… (more)

Subjects/Keywords: On-Chip Interconnect Networks; Asynchronous Ring Bus; Multi-Core Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lei, K. (2010). Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lei, Kin-fong. “Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems.” 2010. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lei, Kin-fong. “Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems.” 2010. Web. 07 Mar 2021.

Vancouver:

Lei K. Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems. [Internet] [Thesis]. NSYSU; 2010. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lei K. Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

11. Lee, Cheng-Han. Design, Analysis and Applications of Hybrid CORDIC Processor Architectures.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513

► In this thesis, we propose different CORDIC architectures which solve the problems of long-latency in traditional pipeline CORDIC and the large-area cost in table-based CORDIC.… (more)

Subjects/Keywords: Arithmetic Function Units; CORDIC; Taylor-series expansion

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lee, C. (2010). Design, Analysis and Applications of Hybrid CORDIC Processor Architectures. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lee, Cheng-Han. “Design, Analysis and Applications of Hybrid CORDIC Processor Architectures.” 2010. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lee, Cheng-Han. “Design, Analysis and Applications of Hybrid CORDIC Processor Architectures.” 2010. Web. 07 Mar 2021.

Vancouver:

Lee C. Design, Analysis and Applications of Hybrid CORDIC Processor Architectures. [Internet] [Thesis]. NSYSU; 2010. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee C. Design, Analysis and Applications of Hybrid CORDIC Processor Architectures. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

12. Tsai, Cheng-Hsuan. Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704

► The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, various new logic circuit design styles based on… (more)

Subjects/Keywords: CMOS logic; Logic Synthesizer; Standard Cell Library; ASIC Design Flow; Pass-Transition-Logic(PTL)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Tsai, C. (2010). Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Tsai, Cheng-Hsuan. “Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library.” 2010. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Tsai, Cheng-Hsuan. “Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library.” 2010. Web. 07 Mar 2021.

Vancouver:

Tsai C. Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library. [Internet] [Thesis]. NSYSU; 2010. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsai C. Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

13. Chiu, Chan-Feng. Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101

► This thesis focuses on efficient design of a vertex shader for per-vertex operations such as Transformation and Lighting in the OpenGL ES 2.0 graphics pipeline.… (more)

Subjects/Keywords: 3D Graph; Logarithmic Number System; Vertex Shader

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chiu, C. (2010). Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chiu, Chan-Feng. “Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System.” 2010. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chiu, Chan-Feng. “Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System.” 2010. Web. 07 Mar 2021.

Vancouver:

Chiu C. Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System. [Internet] [Thesis]. NSYSU; 2010. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chiu C. Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

14. Chen, Li-Yao. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

► OpenGL ES 2.0 programmable 3D graphics pipeline is the current new standard for embedded graphics processor designs. The programmable vertex shader replaces the geometry operations… (more)

Subjects/Keywords: Integration; SOC; Programmable; SIMD; Vertex Shader

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chen, L. (2010). Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chen, Li-Yao. “Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.” 2010. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chen, Li-Yao. “Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.” 2010. Web. 07 Mar 2021.

Vancouver:

Chen L. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. [Internet] [Thesis]. NSYSU; 2010. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen L. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

15. Wu, Yi-hong. A 16-channel High-Voltage Stimulation Generator and A Pulse Frequency Modulation Boost Converter for Spinal Cord Stimulation Systems.

Degree: Master, Electrical Engineering, 2013, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114950

► This thesis consists of two topics, i.e., a 16-channel high-voltage stimulation generator and a pulse frequency modulation (PFM) boost converter, which are mainly designed for… (more)

Subjects/Keywords: stimulation waveform generator; current-limiting; minimum off time one-shot circuit; PFM boost converter; SCS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Wu, Y. (2013). A 16-channel High-Voltage Stimulation Generator and A Pulse Frequency Modulation Boost Converter for Spinal Cord Stimulation Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114950

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wu, Yi-hong. “A 16-channel High-Voltage Stimulation Generator and A Pulse Frequency Modulation Boost Converter for Spinal Cord Stimulation Systems.” 2013. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114950.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wu, Yi-hong. “A 16-channel High-Voltage Stimulation Generator and A Pulse Frequency Modulation Boost Converter for Spinal Cord Stimulation Systems.” 2013. Web. 07 Mar 2021.

Vancouver:

Wu Y. A 16-channel High-Voltage Stimulation Generator and A Pulse Frequency Modulation Boost Converter for Spinal Cord Stimulation Systems. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114950.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu Y. A 16-channel High-Voltage Stimulation Generator and A Pulse Frequency Modulation Boost Converter for Spinal Cord Stimulation Systems. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114950

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

16. Chen, Sih-Yu. Single-ended Disturb-free 5T Load-less 4Kb SRAM with Leakage Current Sensor and Compensation Circuit.

Degree: Master, Electrical Engineering, 2013, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114220

► This thesis consists of two topics, including a single-ended disturb-free 5T load-less 4Kb SRAM, and the leakage current sensor and compensation circuit mainly designed for… (more)

Subjects/Keywords: single-ended; leakage current sensor; power-delay product; load-less; disturb-free; leakage current compensation circuit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chen, S. (2013). Single-ended Disturb-free 5T Load-less 4Kb SRAM with Leakage Current Sensor and Compensation Circuit. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114220

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chen, Sih-Yu. “Single-ended Disturb-free 5T Load-less 4Kb SRAM with Leakage Current Sensor and Compensation Circuit.” 2013. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114220.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chen, Sih-Yu. “Single-ended Disturb-free 5T Load-less 4Kb SRAM with Leakage Current Sensor and Compensation Circuit.” 2013. Web. 07 Mar 2021.

Vancouver:

Chen S. Single-ended Disturb-free 5T Load-less 4Kb SRAM with Leakage Current Sensor and Compensation Circuit. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114220.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen S. Single-ended Disturb-free 5T Load-less 4Kb SRAM with Leakage Current Sensor and Compensation Circuit. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-114220

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

17. Wu, Po-han. Table Size Reduction and Optimization in Multiplierless Table-Based Function Evaluation Designs.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631113-083045

► In hardware design of the elementary function evaluation, Table-lookup-and-addition method is a category of multiplier-less method, based on several lookup tables and a multi-operand adder… (more)

Subjects/Keywords: compress-tree; error-analysis; look-up-table-and-add; multiplier-less function evaluation method; elementary function evaluation method

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Wu, P. (2013). Table Size Reduction and Optimization in Multiplierless Table-Based Function Evaluation Designs. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631113-083045

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wu, Po-han. “Table Size Reduction and Optimization in Multiplierless Table-Based Function Evaluation Designs.” 2013. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631113-083045.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wu, Po-han. “Table Size Reduction and Optimization in Multiplierless Table-Based Function Evaluation Designs.” 2013. Web. 07 Mar 2021.

Vancouver:

Wu P. Table Size Reduction and Optimization in Multiplierless Table-Based Function Evaluation Designs. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631113-083045.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu P. Table Size Reduction and Optimization in Multiplierless Table-Based Function Evaluation Designs. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631113-083045

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

18. Huang, Jun-ming. Hardware Design of Disparity Estimation Using Belief Propagation.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727113-103923

► Stereo vision is widely used in 3D graphics applications. Depth map, an important information in stereo vision, can be generated using stereo matching. In general,… (more)

Subjects/Keywords: Markov random field; belief propagation; disparity computation; depth map; stereo matching; stereo vision

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Huang, J. (2013). Hardware Design of Disparity Estimation Using Belief Propagation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727113-103923

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Huang, Jun-ming. “Hardware Design of Disparity Estimation Using Belief Propagation.” 2013. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727113-103923.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Huang, Jun-ming. “Hardware Design of Disparity Estimation Using Belief Propagation.” 2013. Web. 07 Mar 2021.

Vancouver:

Huang J. Hardware Design of Disparity Estimation Using Belief Propagation. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727113-103923.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang J. Hardware Design of Disparity Estimation Using Belief Propagation. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727113-103923

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

19. Huang, Chih-Hong. Hardware Design of Multi-view 3D Stereo Synthesizers Based on Two Image Sequences.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-151411

► Standared 3D stereo showing images at different view positions requires images captured from various view angles and thus needs large transmission bandwidth. In this thesis,… (more)

Subjects/Keywords: stereo matching; hole filling; image warping; disparity estimation; depth-image-based rendering (DIBR); multiview virtual images

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Huang, C. (2013). Hardware Design of Multi-view 3D Stereo Synthesizers Based on Two Image Sequences. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-151411

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Huang, Chih-Hong. “Hardware Design of Multi-view 3D Stereo Synthesizers Based on Two Image Sequences.” 2013. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-151411.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Huang, Chih-Hong. “Hardware Design of Multi-view 3D Stereo Synthesizers Based on Two Image Sequences.” 2013. Web. 07 Mar 2021.

Vancouver:

Huang C. Hardware Design of Multi-view 3D Stereo Synthesizers Based on Two Image Sequences. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-151411.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang C. Hardware Design of Multi-view 3D Stereo Synthesizers Based on Two Image Sequences. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-151411

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

20. Wu, Pu-Cheng. Implementation of Low Power Multi-Port Memory and Itâs Applications in Graphic Processing Units.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-170119

► Memory design plays an important role in current system-on-chip (SoC) design because memory takes a significant portion of total area. As the complexity of processor… (more)

Subjects/Keywords: body-bias; mixed-signal design flow; vertex shader processor; power-gating; low-leakage design; multi-port SRAM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Wu, P. (2013). Implementation of Low Power Multi-Port Memory and Itâs Applications in Graphic Processing Units. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-170119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wu, Pu-Cheng. “Implementation of Low Power Multi-Port Memory and Itâs Applications in Graphic Processing Units.” 2013. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-170119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wu, Pu-Cheng. “Implementation of Low Power Multi-Port Memory and Itâs Applications in Graphic Processing Units.” 2013. Web. 07 Mar 2021.

Vancouver:

Wu P. Implementation of Low Power Multi-Port Memory and Itâs Applications in Graphic Processing Units. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-170119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu P. Implementation of Low Power Multi-Port Memory and Itâs Applications in Graphic Processing Units. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-170119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

21. Hou, Zong-you. Transmitter with Over-Voltage Protection and Bus Driver Controller with Hazard Detection for FlexRay Systems.

Degree: Master, Electrical Engineering, 2014, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-163105

► FlexRay is a high-speed automotive bus standard designed to integrate ECUs, sensors, and discretes within an in-car network. The research of this thesis is mainly… (more)

Subjects/Keywords: Bus Driver (BD); state transition; hazard detection; FlexRay transmitter; over-voltage detector

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APA (6^th Edition):

Hou, Z. (2014). Transmitter with Over-Voltage Protection and Bus Driver Controller with Hazard Detection for FlexRay Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-163105

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hou, Zong-you. “Transmitter with Over-Voltage Protection and Bus Driver Controller with Hazard Detection for FlexRay Systems.” 2014. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-163105.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hou, Zong-you. “Transmitter with Over-Voltage Protection and Bus Driver Controller with Hazard Detection for FlexRay Systems.” 2014. Web. 07 Mar 2021.

Vancouver:

Hou Z. Transmitter with Over-Voltage Protection and Bus Driver Controller with Hazard Detection for FlexRay Systems. [Internet] [Thesis]. NSYSU; 2014. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-163105.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hou Z. Transmitter with Over-Voltage Protection and Bus Driver Controller with Hazard Detection for FlexRay Systems. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-163105

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

22. Tsai, Tsung-Yi. A Process Compensation and Non-linear Calibration Temperature Detector and A Hysteresis Current-Controlled Boost Converter for Battery Management Systems.

Degree: Master, Electrical Engineering, 2014, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135226

► The reaserch in the thesis is mainly associated with Battery Management Systems (BMS) in Electronic Vehicles(EV), especially regarding thermal sensor and boost converter design. In… (more)

Subjects/Keywords: temperature detector; non-linear calibration; hysteresis; boost converter

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APA (6^th Edition):

Tsai, T. (2014). A Process Compensation and Non-linear Calibration Temperature Detector and A Hysteresis Current-Controlled Boost Converter for Battery Management Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135226

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Tsai, Tsung-Yi. “A Process Compensation and Non-linear Calibration Temperature Detector and A Hysteresis Current-Controlled Boost Converter for Battery Management Systems.” 2014. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135226.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Tsai, Tsung-Yi. “A Process Compensation and Non-linear Calibration Temperature Detector and A Hysteresis Current-Controlled Boost Converter for Battery Management Systems.” 2014. Web. 07 Mar 2021.

Vancouver:

Tsai T. A Process Compensation and Non-linear Calibration Temperature Detector and A Hysteresis Current-Controlled Boost Converter for Battery Management Systems. [Internet] [Thesis]. NSYSU; 2014. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135226.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsai T. A Process Compensation and Non-linear Calibration Temperature Detector and A Hysteresis Current-Controlled Boost Converter for Battery Management Systems. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135226

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

23. Tong, Ting-Chi. Bandwidth Optimized Integrated Predictive Pixel Compensator of H.264 Decoder.

Degree: Master, Computer Science and Engineering, 2008, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807108-200335

► In this thesis, a high-efficient integrated pixel compensator architecture for the H.264/AVC standard has been proposed which can provide both inter and intra prediction functions… (more)

▼ In this thesis, a high-efficient integrated pixel compensator architecture for the H.264/AVC standard has been proposed which can provide both inter and intra prediction functions for luma and chroma components of pixels. By decomposing the algorithms used for both prediction methods into small micro-operation steps, the fundamental arithmetic processing unit architecture capable for performing these operations can be first determined. Next, by considering the possible reference sample transfer issue, the overall compensator architecture will be built by using parallel processing units with some input and intermediate buffers which can be dynamically configured to perform proper computation schedules of different modes suitable for the nature input order of reference samples. The proposed design not only can avoid the additional data transposition buffer, but most importantly the data transfer time spent to fetch the reference samples can be overlapped with the data computation time. Since both arithmetic units and the intermediate data buffer for both inter and intra prediction processes have been shared, our integrated design can achieve more than 30% reduction of gate count compared with the sum of the separate designs. Our design can also lead to more than 38% saving of gate count compared with the previous designs. In addition to the data-path design, this thesis also addresses the memory bandwidth optimization issue which is especially important for the luma interpolation process. A new data-reuse buffer design based on a two-dimensional cache architecture to explore the possible data reuse among the inter and intra partitions will be proposed. The proposed design can be easily integrated with the H.264 interpolator to reduce the enormous demand of memory access. Our experimental results shows that our saving of memory bandwidth can be 20% more than what the best design can achieve by exploring the intra-partition data reuse only. Besides, our compensator can decode the videos up to HDTV resolution, and be applied for the dedicated H.264 hardware codec for various consumer devices. Advisors/Committee Members: Chuen-Yau Chen (chair), Yun-Nan Chang (committee member), Fu%20Hsiao%22%29&pagesize-30">Shen-Fu Hsiao (chair).

Subjects/Keywords: Predictive Pixel Compensator; Inter Prediction; Intra Prediction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Tong, T. (2008). Bandwidth Optimized Integrated Predictive Pixel Compensator of H.264 Decoder. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807108-200335

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Tong, Ting-Chi. “Bandwidth Optimized Integrated Predictive Pixel Compensator of H.264 Decoder.” 2008. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807108-200335.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Tong, Ting-Chi. “Bandwidth Optimized Integrated Predictive Pixel Compensator of H.264 Decoder.” 2008. Web. 07 Mar 2021.

Vancouver:

Tong T. Bandwidth Optimized Integrated Predictive Pixel Compensator of H.264 Decoder. [Internet] [Thesis]. NSYSU; 2008. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807108-200335.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tong T. Bandwidth Optimized Integrated Predictive Pixel Compensator of H.264 Decoder. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807108-200335

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

24. Wu, Ming-Shiou. Dynamic Multi-channel Multi-path Routing Protocol for Wireless Mesh Networks.

Degree: Master, Electrical Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728110-113535

► With the wireless mesh network in the embedded systems related applications booming in recent years, the demand of enhancing the overall end to end network… (more)

Subjects/Keywords: Routing Protocol; Multi-path; Multi-channel; Wireless Mesh Networks

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Wu, M. (2010). Dynamic Multi-channel Multi-path Routing Protocol for Wireless Mesh Networks. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728110-113535

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wu, Ming-Shiou. “Dynamic Multi-channel Multi-path Routing Protocol for Wireless Mesh Networks.” 2010. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728110-113535.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wu, Ming-Shiou. “Dynamic Multi-channel Multi-path Routing Protocol for Wireless Mesh Networks.” 2010. Web. 07 Mar 2021.

Vancouver:

Wu M. Dynamic Multi-channel Multi-path Routing Protocol for Wireless Mesh Networks. [Internet] [Thesis]. NSYSU; 2010. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728110-113535.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu M. Dynamic Multi-channel Multi-path Routing Protocol for Wireless Mesh Networks. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728110-113535

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

25. Zhang Jian, Jun-Hong. Design of Low Cost Finite-Impulse Response (FIR) Filters Using Multiple Constant Truncated Multipliers.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-142752

► Finite impulse response (FIR) digital filters are frequently used in many digital signal processing and communication applications, such as IS-95 CDMA, Digital Mobile Phone Systems… (more)

Subjects/Keywords: Common Sub-expression Elimination (CSE); Booth recoding; error analysis; truncated multiplier; FIR filter; multiple constant multiplication (MCM); VLSI design; Canonical Signed Digit (CSD) encoding

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Zhang Jian, J. (2012). Design of Low Cost Finite-Impulse Response (FIR) Filters Using Multiple Constant Truncated Multipliers. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-142752

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Zhang Jian, Jun-Hong. “Design of Low Cost Finite-Impulse Response (FIR) Filters Using Multiple Constant Truncated Multipliers.” 2012. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-142752.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Zhang Jian, Jun-Hong. “Design of Low Cost Finite-Impulse Response (FIR) Filters Using Multiple Constant Truncated Multipliers.” 2012. Web. 07 Mar 2021.

Vancouver:

Zhang Jian J. Design of Low Cost Finite-Impulse Response (FIR) Filters Using Multiple Constant Truncated Multipliers. [Internet] [Thesis]. NSYSU; 2012. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-142752.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang Jian J. Design of Low Cost Finite-Impulse Response (FIR) Filters Using Multiple Constant Truncated Multipliers. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-142752

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

26. Wang, Wen-Ling. Hardware Design for Disparity Estimation Using Dynamic Programming.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0911112-120201

► Recently, stereo vision has been widely used in many applications, and depth map is important information in stereo vision. In general, depth map can be… (more)

Subjects/Keywords: depth map; disparity; stereo vision; dynamic programming; stereo correspondence; stereo matching

Record Details Similar Records Cite « Share

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Wang, W. (2012). Hardware Design for Disparity Estimation Using Dynamic Programming. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0911112-120201

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wang, Wen-Ling. “Hardware Design for Disparity Estimation Using Dynamic Programming.” 2012. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0911112-120201.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wang, Wen-Ling. “Hardware Design for Disparity Estimation Using Dynamic Programming.” 2012. Web. 07 Mar 2021.

Vancouver:

Wang W. Hardware Design for Disparity Estimation Using Dynamic Programming. [Internet] [Thesis]. NSYSU; 2012. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0911112-120201.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang W. Hardware Design for Disparity Estimation Using Dynamic Programming. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0911112-120201

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

27. Lin, Shin-hung. Improved Bit-Level Truncation with Joint Error Analysis for Table-Based Function Evaluation.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0912112-092221

► Function evaluation is often used in many science and engineering applications. In order to reduce the computation time, different hardware implementations have been proposed to… (more)

Subjects/Keywords: non-uniform segmentation; piecewise polynomial approximation; error analysis; table-based function evaluation; truncated multipliers; uniform segmentation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lin, S. (2012). Improved Bit-Level Truncation with Joint Error Analysis for Table-Based Function Evaluation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0912112-092221

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lin, Shin-hung. “Improved Bit-Level Truncation with Joint Error Analysis for Table-Based Function Evaluation.” 2012. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0912112-092221.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lin, Shin-hung. “Improved Bit-Level Truncation with Joint Error Analysis for Table-Based Function Evaluation.” 2012. Web. 07 Mar 2021.

Vancouver:

Lin S. Improved Bit-Level Truncation with Joint Error Analysis for Table-Based Function Evaluation. [Internet] [Thesis]. NSYSU; 2012. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0912112-092221.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin S. Improved Bit-Level Truncation with Joint Error Analysis for Table-Based Function Evaluation. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0912112-092221

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

28. Yang, Chin-lun. A Ray Tracing Acceleration Scheme for Dynamic Scenes.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806116-194815

► Once restricted by its enormous computational demand, ray-tracing has regained a great deal of attention nowadays due to the fast increase of systemsâ computing power.… (more)

▼ Once restricted by its enormous computational demand, ray-tracing has regained a great deal of attention nowadays due to the fast increase of systemsâ computing power. This thesis proposes an efficient ray-tracing scheme to render dynamic scenes by exploring the coherence between consecutive frames. Since for many ordinary dynamic scenes, the ray emitted from the same pixels of two consecutive frames may hit the same object with high possibility. This thesis adopts an extra hit-buffer to store the index of primitive each ray intersects for the current scene. To render the following scene, for the trace of each ray the proposed scheme will first apply the ray-triangle intersection operation to the triangle it hits in the previous frame before proceeding to the normal tree traversal procedure. Once the ray hits the same triangle, the intersection depth can be used to exclude the test operation of many nodes during the tree traversal. In addition, by assuming that only few objects in a scene may move from frame to frame, the bounding volume hierarchies (BVH) tree structure of the current scene can be obtained by updating the tree structure of the previous one. Therefore, we can annotate each node of the tree by an additional flag to denote whether it has been modified or not. The unmodified nodes can be directly ignored during the tree traversal for those rays which hit the same primitives in the current scene. For our own test scenes whose total number of modified triangles is less than 5% of the overall triangle count, our experimental results show that more than one half of ray-node tests and ray-triangle intersection operations can be saved, which can result in more than 50% reduction in the software ray-tracing time. For the common test scene TOASTERS where more than 90% of triangles have been moved in consecutive scenes, the proposed scheme can still achieve the saving of trace time up to 30%. Advisors/Committee Members: Xin-Yu Shih (chair), Chun-Fa Chang (chair), Fu%20Hsiao%22%29&pagesize-30">Shen-Fu Hsiao (chair), Yun-Nan Chang (committee member).

Subjects/Keywords: Dynamic scene; BVH update; Ray-tracing; Frame coherence; BVH

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Yang, C. (2016). A Ray Tracing Acceleration Scheme for Dynamic Scenes. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806116-194815

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Yang, Chin-lun. “A Ray Tracing Acceleration Scheme for Dynamic Scenes.” 2016. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806116-194815.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Yang, Chin-lun. “A Ray Tracing Acceleration Scheme for Dynamic Scenes.” 2016. Web. 07 Mar 2021.

Vancouver:

Yang C. A Ray Tracing Acceleration Scheme for Dynamic Scenes. [Internet] [Thesis]. NSYSU; 2016. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806116-194815.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang C. A Ray Tracing Acceleration Scheme for Dynamic Scenes. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806116-194815

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

29. Yang, Chih-hsiang. Multi-view Image Generation by Hole Area Partial Rendering in DIBR Hole Filling for 3D Display.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807116-111802

► To provide multi-view image for three-dimensional display, the efficiency of traditional rendering multiple times method is very low. There is an alternative called depth-image-based rendering… (more)

Subjects/Keywords: stereoscopic vision; 3D display; multi-view rendering; computer graphic; DIBR

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Yang, C. (2016). Multi-view Image Generation by Hole Area Partial Rendering in DIBR Hole Filling for 3D Display. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807116-111802

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Yang, Chih-hsiang. “Multi-view Image Generation by Hole Area Partial Rendering in DIBR Hole Filling for 3D Display.” 2016. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807116-111802.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Yang, Chih-hsiang. “Multi-view Image Generation by Hole Area Partial Rendering in DIBR Hole Filling for 3D Display.” 2016. Web. 07 Mar 2021.

Vancouver:

Yang C. Multi-view Image Generation by Hole Area Partial Rendering in DIBR Hole Filling for 3D Display. [Internet] [Thesis]. NSYSU; 2016. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807116-111802.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang C. Multi-view Image Generation by Hole Area Partial Rendering in DIBR Hole Filling for 3D Display. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807116-111802

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

30. Chen, Zhi-wei. Design and Implementation of Highly-parallel Efficient BVH Tree Builder Architecture for Ray Tracing.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-135254

► Bounding volume hierarchy (BVH) tree construction is a very important issue for real-time ray-tracing rendering of dynamic scenes. How to accelerate this process by either… (more)

Subjects/Keywords: computer graphics; BVH tree construction; ray-tracing hardware; ray-tracing; BVH

Record Details Similar Records Cite « Share

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chen, Z. (2017). Design and Implementation of Highly-parallel Efficient BVH Tree Builder Architecture for Ray Tracing. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-135254

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chen, Zhi-wei. “Design and Implementation of Highly-parallel Efficient BVH Tree Builder Architecture for Ray Tracing.” 2017. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-135254.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chen, Zhi-wei. “Design and Implementation of Highly-parallel Efficient BVH Tree Builder Architecture for Ray Tracing.” 2017. Web. 07 Mar 2021.

Vancouver:

Chen Z. Design and Implementation of Highly-parallel Efficient BVH Tree Builder Architecture for Ray Tracing. [Internet] [Thesis]. NSYSU; 2017. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-135254.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Z. Design and Implementation of Highly-parallel Efficient BVH Tree Builder Architecture for Ray Tracing. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-135254

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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Open Access Theses and Dissertations