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You searched for +publisher:"NSYSU" +contributor:("Ko-chi Kuo"). Showing records 1 – 30 of 97 total matches.

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NSYSU

1. Ko, Xue-Da. Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 With the improvement of semiconductor manufacturing processes, the power consumption of the integrated circuit(IC) is growing rapidly. Therefore, the power consumption reduction of IC is… (more)

Subjects/Keywords: Static Timing Analysis; Level Converter; Critical Path; Multiple-Supply Voltage

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ko, X. (2013). Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ko, Xue-Da. “Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology.” 2013. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ko, Xue-Da. “Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology.” 2013. Web. 08 Aug 2020.

Vancouver:

Ko X. Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ko X. Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

2. Hsu, Hsun-Chia. A digital circuit chip design with error correctable, error detected and encryption/decryption for Power Line Communication.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 Power Line Communications (PLC) is a used of power lines as a transmission medium of communication technology. Currently PLC technology is growing and maturing rapidly,… (more)

Subjects/Keywords: FSK; Power line communication; Binary BCH code; CRC; TEA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hsu, H. (2013). A digital circuit chip design with error correctable, error detected and encryption/decryption for Power Line Communication. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-122551

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsu, Hsun-Chia. “A digital circuit chip design with error correctable, error detected and encryption/decryption for Power Line Communication.” 2013. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-122551.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsu, Hsun-Chia. “A digital circuit chip design with error correctable, error detected and encryption/decryption for Power Line Communication.” 2013. Web. 08 Aug 2020.

Vancouver:

Hsu H. A digital circuit chip design with error correctable, error detected and encryption/decryption for Power Line Communication. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-122551.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu H. A digital circuit chip design with error correctable, error detected and encryption/decryption for Power Line Communication. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-122551

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

3. Xie, Shan-yang. Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 This All-Digital phase-locked loop uses TSMC90nm process. It uses digital frequency detector and successive approximation register to control the digitally controlled oscillator as well as… (more)

Subjects/Keywords: low power schmitt trigger inverter; digitally controlled oscillator; all digital phase-locked loop; digital frequency detector; successive approximation register

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xie, S. (2018). Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xie, Shan-yang. “Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop.” 2018. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xie, Shan-yang. “Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop.” 2018. Web. 08 Aug 2020.

Vancouver:

Xie S. Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xie S. Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

4. Liao, Chun-Kai. A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 The proposed PLL in this thesis is implemented in TSMC 90nm 1P9M RF technology with a 1V supply voltage. This thesis presents a wide tuning… (more)

Subjects/Keywords: PLL; Controllable OTA; VCO; Charge Pump; PFD; Bootstrapped Switch

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liao, C. (2017). A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172335

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liao, Chun-Kai. “A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier.” 2017. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172335.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liao, Chun-Kai. “A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier.” 2017. Web. 08 Aug 2020.

Vancouver:

Liao C. A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172335.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liao C. A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172335

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

5. Chen, Hung-Yen. A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 In this thesis, a 10-bit binary search assisted two channel SAR ADC with a two bit per conversion and error tolerance ability operating in 250Ms/s… (more)

Subjects/Keywords: Two bits per conversion; Non-binary; Time-interleaved; Binary search; SAR ADC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, H. (2017). A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172820

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Hung-Yen. “A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability.” 2017. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172820.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Hung-Yen. “A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability.” 2017. Web. 08 Aug 2020.

Vancouver:

Chen H. A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172820.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen H. A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172820

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

6. Huang, Yi-Hsuan. VLSI Design And Implementation Of Low Bit-error Rate HomePlug AV System.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 This thesis implements the HomePlug AV power line communication system to reduce the probability of decoding errors caused by noise interference during transmission. The architecture… (more)

Subjects/Keywords: , PLC; FFT; QAM; Interleaver; Scramble; Turbo Code; OFDM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, Y. (2017). VLSI Design And Implementation Of Low Bit-error Rate HomePlug AV System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-182647

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Yi-Hsuan. “VLSI Design And Implementation Of Low Bit-error Rate HomePlug AV System.” 2017. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-182647.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Yi-Hsuan. “VLSI Design And Implementation Of Low Bit-error Rate HomePlug AV System.” 2017. Web. 08 Aug 2020.

Vancouver:

Huang Y. VLSI Design And Implementation Of Low Bit-error Rate HomePlug AV System. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-182647.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang Y. VLSI Design And Implementation Of Low Bit-error Rate HomePlug AV System. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-182647

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

7. Yen, Huai-yu. Power Optimization for 3D Vertex Shader Using Clock Gating.

Degree: Master, Computer Science and Engineering, 2008, NSYSU

 With technology increasingly and the needs of high performance and multiple functionalities, power dissipation has be a bottleneck in microprocessors. And clock power is the… (more)

Subjects/Keywords: instruction schedule; 3D vertex shader; clock gating; Low power

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yen, H. (2008). Power Optimization for 3D Vertex Shader Using Clock Gating. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816108-003258

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yen, Huai-yu. “Power Optimization for 3D Vertex Shader Using Clock Gating.” 2008. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816108-003258.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yen, Huai-yu. “Power Optimization for 3D Vertex Shader Using Clock Gating.” 2008. Web. 08 Aug 2020.

Vancouver:

Yen H. Power Optimization for 3D Vertex Shader Using Clock Gating. [Internet] [Thesis]. NSYSU; 2008. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816108-003258.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yen H. Power Optimization for 3D Vertex Shader Using Clock Gating. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816108-003258

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

8. Wu, Zong-Lin. Low-Overhead Isolation Cells for Low-Power Multipliers.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

 With the rapid progress in manufacturing technology, the chip design is more and more complicated day by day. As a result, the circuit design with… (more)

Subjects/Keywords: low overhead isolation cell; standard cell; low-power multipliers

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, Z. (2009). Low-Overhead Isolation Cells for Low-Power Multipliers. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Zong-Lin. “Low-Overhead Isolation Cells for Low-Power Multipliers.” 2009. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Zong-Lin. “Low-Overhead Isolation Cells for Low-Power Multipliers.” 2009. Web. 08 Aug 2020.

Vancouver:

Wu Z. Low-Overhead Isolation Cells for Low-Power Multipliers. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu Z. Low-Overhead Isolation Cells for Low-Power Multipliers. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

9. Yang, Cheng-Yen. IEEE 802.15.4 Protocol Stack Library Implementation,Hardware Design, and Applications in Medical Monitoring.

Degree: Master, Electrical Engineering, 2010, NSYSU

 Due to the rapid development of semiconductor technology, the number of transistors of integrated circuits in unit area increases by double in roughly every two… (more)

Subjects/Keywords: Protocol Stack Library; Clock-Gating; CSMA/CA; On-Chip-Bus; Medical Monitoring; Wireless Person Area Network; IEEE 802.15.4; Low power; Wireless Sensor Network; WISHBONE

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, C. (2010). IEEE 802.15.4 Protocol Stack Library Implementation,Hardware Design, and Applications in Medical Monitoring. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712110-165927

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Cheng-Yen. “IEEE 802.15.4 Protocol Stack Library Implementation,Hardware Design, and Applications in Medical Monitoring.” 2010. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712110-165927.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Cheng-Yen. “IEEE 802.15.4 Protocol Stack Library Implementation,Hardware Design, and Applications in Medical Monitoring.” 2010. Web. 08 Aug 2020.

Vancouver:

Yang C. IEEE 802.15.4 Protocol Stack Library Implementation,Hardware Design, and Applications in Medical Monitoring. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712110-165927.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang C. IEEE 802.15.4 Protocol Stack Library Implementation,Hardware Design, and Applications in Medical Monitoring. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712110-165927

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

10. Chen, Chih-hung. 1MHz Bandwidth Switched-Current Sigma Delta Modulator.

Degree: Master, Electrical Engineering, 2010, NSYSU

 The thesis proposes an integrator with an OPAMP in the feedback loop to fulfill 1MHz bandwidth SI Sigma Delta modulator. The OPAMP is used to… (more)

Subjects/Keywords: delta-sigma modulator; sigma-delta modulator; switched-current circuit; integrator; sample and hole; current comparator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, C. (2010). 1MHz Bandwidth Switched-Current Sigma Delta Modulator. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901110-122544

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Chih-hung. “1MHz Bandwidth Switched-Current Sigma Delta Modulator.” 2010. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901110-122544.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Chih-hung. “1MHz Bandwidth Switched-Current Sigma Delta Modulator.” 2010. Web. 08 Aug 2020.

Vancouver:

Chen C. 1MHz Bandwidth Switched-Current Sigma Delta Modulator. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901110-122544.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen C. 1MHz Bandwidth Switched-Current Sigma Delta Modulator. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901110-122544

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

11. Lai, Kai-hsin. Bilinear Second Order Integral Bandpass Filter.

Degree: Master, Electrical Engineering, 2011, NSYSU

 Traditional transfer function of integrators have warping effect in high frequency, this isnât good for make filter circuit. In reference[3] they mention a new transfer… (more)

Subjects/Keywords: Filter; integrator; Modified; double sampling; bilinear

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lai, K. (2011). Bilinear Second Order Integral Bandpass Filter. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0125111-164403

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lai, Kai-hsin. “Bilinear Second Order Integral Bandpass Filter.” 2011. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0125111-164403.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lai, Kai-hsin. “Bilinear Second Order Integral Bandpass Filter.” 2011. Web. 08 Aug 2020.

Vancouver:

Lai K. Bilinear Second Order Integral Bandpass Filter. [Internet] [Thesis]. NSYSU; 2011. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0125111-164403.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lai K. Bilinear Second Order Integral Bandpass Filter. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0125111-164403

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

12. Lin, Shin-Yang. A CMOS LNA for 3.1-10.6GHz Ultra-Wideband.

Degree: Master, Electrical Engineering, 2011, NSYSU

 The objective of this thesis is aimed at the design of low noise amplifier (LNA) for an ultra-wideband (UWB) receiver system using standard 0.18um CMOS… (more)

Subjects/Keywords: low noise amplifier; input matching; Series-peaking; Resistive-feedback; Ultra-wideband; CMOS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, S. (2011). A CMOS LNA for 3.1-10.6GHz Ultra-Wideband. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0125111-154905

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Shin-Yang. “A CMOS LNA for 3.1-10.6GHz Ultra-Wideband.” 2011. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0125111-154905.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Shin-Yang. “A CMOS LNA for 3.1-10.6GHz Ultra-Wideband.” 2011. Web. 08 Aug 2020.

Vancouver:

Lin S. A CMOS LNA for 3.1-10.6GHz Ultra-Wideband. [Internet] [Thesis]. NSYSU; 2011. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0125111-154905.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin S. A CMOS LNA for 3.1-10.6GHz Ultra-Wideband. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0125111-154905

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

13. Wang, Deng-Shian. A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS.

Degree: Master, Electrical Engineering, 2013, NSYSU

 This thesis includes two designs: A high-voltage (HV) multiplexer and a successive-approximation register ADC for Battery Management Systems (BMS). The proposed designs are implemented by… (more)

Subjects/Keywords: BMS; high-voltage multiplexer; charge redistribution architecture; successive-approximation register ADC; high-voltage switch

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, D. (2013). A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0608113-213119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Deng-Shian. “A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS.” 2013. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0608113-213119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Deng-Shian. “A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS.” 2013. Web. 08 Aug 2020.

Vancouver:

Wang D. A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0608113-213119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang D. A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0608113-213119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

14. Hu , Yi. A Receiver with Over-Voltage Protection for FlexRay Systems and an 8:1 High-Voltage Analog Multiplexer for Battery Management Systems.

Degree: Master, Electrical Engineering, 2013, NSYSU

 The research of this thesis is mainly focused on automotive electronics including two topics, a Receiver (Rx) with over-voltage protection for FlexRay systems and an… (more)

Subjects/Keywords: over-voltage protection; HV switches; FlexRay Receiver; BMS; HV MUX

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APA (6th Edition):

Hu , Y. (2013). A Receiver with Over-Voltage Protection for FlexRay Systems and an 8:1 High-Voltage Analog Multiplexer for Battery Management Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-151412

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hu , Yi. “A Receiver with Over-Voltage Protection for FlexRay Systems and an 8:1 High-Voltage Analog Multiplexer for Battery Management Systems.” 2013. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-151412.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hu , Yi. “A Receiver with Over-Voltage Protection for FlexRay Systems and an 8:1 High-Voltage Analog Multiplexer for Battery Management Systems.” 2013. Web. 08 Aug 2020.

Vancouver:

Hu Y. A Receiver with Over-Voltage Protection for FlexRay Systems and an 8:1 High-Voltage Analog Multiplexer for Battery Management Systems. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-151412.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hu Y. A Receiver with Over-Voltage Protection for FlexRay Systems and an 8:1 High-Voltage Analog Multiplexer for Battery Management Systems. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-151412

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

15. Liao, Chiang-Hsiang. Development of A Rapid Readout System for CEA Detection and An SRAM with Leakage Sensor and Read Delay Compensation.

Degree: Master, Electrical Engineering, 2014, NSYSU

 This thesis is composed of a biomedical sensing system design and a novel circuit design of 5T SRAM (static random access memory, SRAM). The first… (more)

Subjects/Keywords: leakage current sensor; SRAM; readout circuit

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APA (6th Edition):

Liao, C. (2014). Development of A Rapid Readout System for CEA Detection and An SRAM with Leakage Sensor and Read Delay Compensation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135024

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liao, Chiang-Hsiang. “Development of A Rapid Readout System for CEA Detection and An SRAM with Leakage Sensor and Read Delay Compensation.” 2014. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135024.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liao, Chiang-Hsiang. “Development of A Rapid Readout System for CEA Detection and An SRAM with Leakage Sensor and Read Delay Compensation.” 2014. Web. 08 Aug 2020.

Vancouver:

Liao C. Development of A Rapid Readout System for CEA Detection and An SRAM with Leakage Sensor and Read Delay Compensation. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135024.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liao C. Development of A Rapid Readout System for CEA Detection and An SRAM with Leakage Sensor and Read Delay Compensation. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135024

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

16. Bai, Je-Wei. A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 In this thesis, a 10-bit, 80 MS/s analog-to-digital converter with a 1 V supply voltage is implemented by using the TSMC 90nm process technology. This… (more)

Subjects/Keywords: non-binary digital error correction; digital error correction; 2b/Cycle; Successive Approximation Register; Analog to Digital Converter

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APA (6th Edition):

Bai, J. (2016). A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bai, Je-Wei. “A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction.” 2016. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bai, Je-Wei. “A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction.” 2016. Web. 08 Aug 2020.

Vancouver:

Bai J. A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bai J. A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

17. Sung, Ying-Ju. A 12-bit Digital-to-Analog Converter with the specified code and thermometer code decoder.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 With the continuous development of technology, mobile communication device has more and more demand for function, with the widespread use of smartphones and, increasingly, APP… (more)

Subjects/Keywords: digital-to-analog converter; the specified code; high precision; small area; high speed

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sung, Y. (2016). A 12-bit Digital-to-Analog Converter with the specified code and thermometer code decoder. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-160737

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sung, Ying-Ju. “A 12-bit Digital-to-Analog Converter with the specified code and thermometer code decoder.” 2016. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-160737.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sung, Ying-Ju. “A 12-bit Digital-to-Analog Converter with the specified code and thermometer code decoder.” 2016. Web. 08 Aug 2020.

Vancouver:

Sung Y. A 12-bit Digital-to-Analog Converter with the specified code and thermometer code decoder. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-160737.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sung Y. A 12-bit Digital-to-Analog Converter with the specified code and thermometer code decoder. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-160737

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

18. Liou, Shih-Hao. All-Digital SAR-Controlled Delay-Locked Loop with Tracking System Based on Thermometer Code.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 This All-Digital delay-locked loop uses TSMC90nm process. It uses digital phase detector and successive approximation register to control the digital delay line as well as… (more)

Subjects/Keywords: binary-weighted code; successive approximation register; delay lock loop; thermometer code; low power

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APA (6th Edition):

Liou, S. (2016). All-Digital SAR-Controlled Delay-Locked Loop with Tracking System Based on Thermometer Code. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729116-130544

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liou, Shih-Hao. “All-Digital SAR-Controlled Delay-Locked Loop with Tracking System Based on Thermometer Code.” 2016. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729116-130544.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liou, Shih-Hao. “All-Digital SAR-Controlled Delay-Locked Loop with Tracking System Based on Thermometer Code.” 2016. Web. 08 Aug 2020.

Vancouver:

Liou S. All-Digital SAR-Controlled Delay-Locked Loop with Tracking System Based on Thermometer Code. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729116-130544.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liou S. All-Digital SAR-Controlled Delay-Locked Loop with Tracking System Based on Thermometer Code. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729116-130544

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

19. Chang, Chia-ming. A 10-bit Process-Calibrated Current-Steering D/A Converter and High Bandwidth and High Coversion Gain Power Detector for Frequency-Shift Readout Systems.

Degree: Master, Electrical Engineering, 2014, NSYSU

 Since the combination of antigens with the corresponding antibody will change the resonant frequency of certain MEMS sensors, this kind of technology is often utilized… (more)

Subjects/Keywords: current-steering; process-calibrated; DAC; power detector

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APA (6th Edition):

Chang, C. (2014). A 10-bit Process-Calibrated Current-Steering D/A Converter and High Bandwidth and High Coversion Gain Power Detector for Frequency-Shift Readout Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-155610

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Chia-ming. “A 10-bit Process-Calibrated Current-Steering D/A Converter and High Bandwidth and High Coversion Gain Power Detector for Frequency-Shift Readout Systems.” 2014. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-155610.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Chia-ming. “A 10-bit Process-Calibrated Current-Steering D/A Converter and High Bandwidth and High Coversion Gain Power Detector for Frequency-Shift Readout Systems.” 2014. Web. 08 Aug 2020.

Vancouver:

Chang C. A 10-bit Process-Calibrated Current-Steering D/A Converter and High Bandwidth and High Coversion Gain Power Detector for Frequency-Shift Readout Systems. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-155610.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang C. A 10-bit Process-Calibrated Current-Steering D/A Converter and High Bandwidth and High Coversion Gain Power Detector for Frequency-Shift Readout Systems. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-155610

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

20. chou, chen-kang. A 6~10 GHz UWB Low Noise Amplifier.

Degree: Master, Electrical Engineering, 2012, NSYSU

 The main contents of this thesis are improving a UWB LNA, and analyze the input-matching, the noise, and the gain. First we use the feedback… (more)

Subjects/Keywords: output matching; feedback resistor; LNA; UWB; input matching

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APA (6th Edition):

chou, c. (2012). A 6~10 GHz UWB Low Noise Amplifier. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724112-010216

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

chou, chen-kang. “A 6~10 GHz UWB Low Noise Amplifier.” 2012. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724112-010216.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

chou, chen-kang. “A 6~10 GHz UWB Low Noise Amplifier.” 2012. Web. 08 Aug 2020.

Vancouver:

chou c. A 6~10 GHz UWB Low Noise Amplifier. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724112-010216.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

chou c. A 6~10 GHz UWB Low Noise Amplifier. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724112-010216

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

21. Yang, Chen-yueh. Characterization of Lateral Bipolar Transistor in 180nm and 350nm CMOS for a Biosignal Acquisition Stage.

Degree: Master, Electrical Engineering, 2016, NSYSU

 Technologies and applications of biomedical signals processing become increasingly popular as integrated circuit fabrication technology and process advances, a low interference input stage in a… (more)

Subjects/Keywords: ASIC; Low noise; Biomedical signal; Flicker noise; Lateral Bipolar Transistor

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APA (6th Edition):

Yang, C. (2016). Characterization of Lateral Bipolar Transistor in 180nm and 350nm CMOS for a Biosignal Acquisition Stage. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0913116-111333

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Chen-yueh. “Characterization of Lateral Bipolar Transistor in 180nm and 350nm CMOS for a Biosignal Acquisition Stage.” 2016. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0913116-111333.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Chen-yueh. “Characterization of Lateral Bipolar Transistor in 180nm and 350nm CMOS for a Biosignal Acquisition Stage.” 2016. Web. 08 Aug 2020.

Vancouver:

Yang C. Characterization of Lateral Bipolar Transistor in 180nm and 350nm CMOS for a Biosignal Acquisition Stage. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0913116-111333.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang C. Characterization of Lateral Bipolar Transistor in 180nm and 350nm CMOS for a Biosignal Acquisition Stage. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0913116-111333

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

22. Huang, Kai-chi. A 0.5 V 10-bit 500KS/s SAR ADC With MergeãSplit and Tri-Level Switching in 90 nm CMOS.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 This thesis presents a 10-bit 500KS/s Successive Approximation Analog-to-Digital Converter (SAR ADC) for biomedical applications with a 0.5 V supply voltage which is implemented by… (more)

Subjects/Keywords: Successive Approximation ADC; Low Voltage; Low Speed; Merge and Split Switching; Tri-level Switching

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APA (6th Edition):

Huang, K. (2017). A 0.5 V 10-bit 500KS/s SAR ADC With MergeãSplit and Tri-Level Switching in 90 nm CMOS. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0012117-163328

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Kai-chi. “A 0.5 V 10-bit 500KS/s SAR ADC With MergeãSplit and Tri-Level Switching in 90 nm CMOS.” 2017. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0012117-163328.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Kai-chi. “A 0.5 V 10-bit 500KS/s SAR ADC With MergeãSplit and Tri-Level Switching in 90 nm CMOS.” 2017. Web. 08 Aug 2020.

Vancouver:

Huang K. A 0.5 V 10-bit 500KS/s SAR ADC With MergeãSplit and Tri-Level Switching in 90 nm CMOS. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0012117-163328.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang K. A 0.5 V 10-bit 500KS/s SAR ADC With MergeãSplit and Tri-Level Switching in 90 nm CMOS. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0012117-163328

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

23. Huang, Po-chao. A High speed 12-bit Digital-to-Analog Converter with the extended encoding scheme.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 In the mobile communication applications, the Digital-to-analog converter (DAC) needs the higher accuracy and speed. However, the operation time is limited by the battery capacity… (more)

Subjects/Keywords: DAC; high speed; high precision

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, P. (2017). A High speed 12-bit Digital-to-Analog Converter with the extended encoding scheme. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0013117-100446

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Po-chao. “A High speed 12-bit Digital-to-Analog Converter with the extended encoding scheme.” 2017. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0013117-100446.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Po-chao. “A High speed 12-bit Digital-to-Analog Converter with the extended encoding scheme.” 2017. Web. 08 Aug 2020.

Vancouver:

Huang P. A High speed 12-bit Digital-to-Analog Converter with the extended encoding scheme. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0013117-100446.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang P. A High speed 12-bit Digital-to-Analog Converter with the extended encoding scheme. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0013117-100446

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

24. Tu, Yu-Ting. A Phase Detector with Offset Voltage Calibration for Biosensors.

Degree: Master, Electrical Engineering, 2017, NSYSU

 Biological signal measurement becomes very important as the technology rapidly advances. Consequently, it drives the development of biosensors and biosensing technologies. Particularily, the phase of… (more)

Subjects/Keywords: offset calibration; current feedback instrumentation amplifier; phase shift detector

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tu, Y. (2017). A Phase Detector with Offset Voltage Calibration for Biosensors. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0215117-132236

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tu, Yu-Ting. “A Phase Detector with Offset Voltage Calibration for Biosensors.” 2017. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0215117-132236.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tu, Yu-Ting. “A Phase Detector with Offset Voltage Calibration for Biosensors.” 2017. Web. 08 Aug 2020.

Vancouver:

Tu Y. A Phase Detector with Offset Voltage Calibration for Biosensors. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0215117-132236.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tu Y. A Phase Detector with Offset Voltage Calibration for Biosensors. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0215117-132236

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

25. Wu, Chun-Lin. Design of ray tracing circuit with hierarchical traversal.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 Fast rendering of computer graphics has gradually become an essential requirement for many embedded electronic devices. Ray-tracing can render more realistic graphics than the conventional… (more)

Subjects/Keywords: BVH; Frustum culling; Hierarchical traversal; Ray-tracing; Packet ray

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, C. (2015). Design of ray tracing circuit with hierarchical traversal. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-120610

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Chun-Lin. “Design of ray tracing circuit with hierarchical traversal.” 2015. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-120610.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Chun-Lin. “Design of ray tracing circuit with hierarchical traversal.” 2015. Web. 08 Aug 2020.

Vancouver:

Wu C. Design of ray tracing circuit with hierarchical traversal. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-120610.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu C. Design of ray tracing circuit with hierarchical traversal. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-120610

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

26. Hsu, Chien-te. Design of parallel computing processor based on OpenCL architecture.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 In addition to pursuing more shader cores for better rendering performance, another important trend in the evolution of modern graphic processing units (GPU) is to… (more)

Subjects/Keywords: Scalar Processor; Multi-core; GPU; General Computing; OpenCL

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hsu, C. (2015). Design of parallel computing processor based on OpenCL architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-113525

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsu, Chien-te. “Design of parallel computing processor based on OpenCL architecture.” 2015. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-113525.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsu, Chien-te. “Design of parallel computing processor based on OpenCL architecture.” 2015. Web. 08 Aug 2020.

Vancouver:

Hsu C. Design of parallel computing processor based on OpenCL architecture. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-113525.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu C. Design of parallel computing processor based on OpenCL architecture. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-113525

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

27. Ke, Guan-Wei. A Fast Lock Technique for the 5Ghz Wide band PLL Frequency Synthesizer Design.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 This thesis presents a wide tuning, low phase noise, and fast locking CMOS integer-N frequency synthesizer with 1.8V power supply. The frequency synthesizer is fabricated… (more)

Subjects/Keywords: VCO; Charge Pump; ABS; PLL; PFD; Continuous-Time PFD; OBS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ke, G. (2013). A Fast Lock Technique for the 5Ghz Wide band PLL Frequency Synthesizer Design. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0416113-151940

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ke, Guan-Wei. “A Fast Lock Technique for the 5Ghz Wide band PLL Frequency Synthesizer Design.” 2013. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0416113-151940.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ke, Guan-Wei. “A Fast Lock Technique for the 5Ghz Wide band PLL Frequency Synthesizer Design.” 2013. Web. 08 Aug 2020.

Vancouver:

Ke G. A Fast Lock Technique for the 5Ghz Wide band PLL Frequency Synthesizer Design. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0416113-151940.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ke G. A Fast Lock Technique for the 5Ghz Wide band PLL Frequency Synthesizer Design. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0416113-151940

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

28. Liu, Jun-hong. Low-Power Continuous-Time Sigma-Delta Modulator for GSM.

Degree: Master, Electrical Engineering, 2012, NSYSU

 Continuous-time sigma-delta modulator can be applied to wireless communications, photography and MP3 player. Portable electronics products became mainstream the design of a low power consumption… (more)

Subjects/Keywords: sigma-delta modulator; GSM; low power consumption; low power supply; continuous-time

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, J. (2012). Low-Power Continuous-Time Sigma-Delta Modulator for GSM. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712112-144604

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Jun-hong. “Low-Power Continuous-Time Sigma-Delta Modulator for GSM.” 2012. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712112-144604.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Jun-hong. “Low-Power Continuous-Time Sigma-Delta Modulator for GSM.” 2012. Web. 08 Aug 2020.

Vancouver:

Liu J. Low-Power Continuous-Time Sigma-Delta Modulator for GSM. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712112-144604.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu J. Low-Power Continuous-Time Sigma-Delta Modulator for GSM. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712112-144604

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

29. Kuo, Ya-Wen. Chopper-Stabilized Continuous-time Sigma-Delta Modulator Design for Biomedical Sensing Applications.

Degree: Master, Electrical Engineering, 2012, NSYSU

 Continuous-time sigma-delta modulators play an important role in the development of biomedical sensors. It is suitable for monitoring of basic human vital functions (i.e., heartbeat… (more)

Subjects/Keywords: chopper-stabilized; flicker noise; human vital functions monitoring; sigma-delta modulator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kuo, Y. (2012). Chopper-Stabilized Continuous-time Sigma-Delta Modulator Design for Biomedical Sensing Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712112-150713

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kuo, Ya-Wen. “Chopper-Stabilized Continuous-time Sigma-Delta Modulator Design for Biomedical Sensing Applications.” 2012. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712112-150713.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kuo, Ya-Wen. “Chopper-Stabilized Continuous-time Sigma-Delta Modulator Design for Biomedical Sensing Applications.” 2012. Web. 08 Aug 2020.

Vancouver:

Kuo Y. Chopper-Stabilized Continuous-time Sigma-Delta Modulator Design for Biomedical Sensing Applications. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712112-150713.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kuo Y. Chopper-Stabilized Continuous-time Sigma-Delta Modulator Design for Biomedical Sensing Applications. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712112-150713

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

30. Xi Pond, Jun. Low Voltage Active Inductor Low Noise Amplifier.

Degree: Master, Electrical Engineering, 2012, NSYSU

 This paper is the use of the active inductor instead of passive inductors to save area, enter the match aspects of the use of the… (more)

Subjects/Keywords: Early active inductor; Low voltage active inductor; LNA; Noise; Regulated cascode active inductor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xi Pond, J. (2012). Low Voltage Active Inductor Low Noise Amplifier. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723112-203731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xi Pond, Jun. “Low Voltage Active Inductor Low Noise Amplifier.” 2012. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723112-203731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xi Pond, Jun. “Low Voltage Active Inductor Low Noise Amplifier.” 2012. Web. 08 Aug 2020.

Vancouver:

Xi Pond J. Low Voltage Active Inductor Low Noise Amplifier. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723112-203731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xi Pond J. Low Voltage Active Inductor Low Noise Amplifier. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723112-203731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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