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You searched for +publisher:"NSYSU" +contributor:("Ko-Chi Kuo"). Showing records 1 – 30 of 97 total matches.

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NSYSU

1. Ko, Xue-Da. Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 With the improvement of semiconductor manufacturing processes, the power consumption of the integrated circuit(IC) is growing rapidly. Therefore, the power consumption reduction of IC is… (more)

Subjects/Keywords: Static Timing Analysis; Level Converter; Critical Path; Multiple-Supply Voltage

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ko, X. (2013). Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ko, Xue-Da. “Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology.” 2013. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ko, Xue-Da. “Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology.” 2013. Web. 20 Sep 2020.

Vancouver:

Ko X. Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ko X. Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

2. Hsu, Hsun-Chia. A digital circuit chip design with error correctable, error detected and encryption/decryption for Power Line Communication.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 Power Line Communications (PLC) is a used of power lines as a transmission medium of communication technology. Currently PLC technology is growing and maturing rapidly,… (more)

Subjects/Keywords: FSK; Power line communication; Binary BCH code; CRC; TEA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hsu, H. (2013). A digital circuit chip design with error correctable, error detected and encryption/decryption for Power Line Communication. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-122551

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsu, Hsun-Chia. “A digital circuit chip design with error correctable, error detected and encryption/decryption for Power Line Communication.” 2013. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-122551.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsu, Hsun-Chia. “A digital circuit chip design with error correctable, error detected and encryption/decryption for Power Line Communication.” 2013. Web. 20 Sep 2020.

Vancouver:

Hsu H. A digital circuit chip design with error correctable, error detected and encryption/decryption for Power Line Communication. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-122551.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu H. A digital circuit chip design with error correctable, error detected and encryption/decryption for Power Line Communication. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-122551

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

3. Xie, Shan-yang. Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 This All-Digital phase-locked loop uses TSMC90nm process. It uses digital frequency detector and successive approximation register to control the digitally controlled oscillator as well as… (more)

Subjects/Keywords: low power schmitt trigger inverter; digitally controlled oscillator; all digital phase-locked loop; digital frequency detector; successive approximation register

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APA (6th Edition):

Xie, S. (2018). Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xie, Shan-yang. “Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop.” 2018. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xie, Shan-yang. “Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop.” 2018. Web. 20 Sep 2020.

Vancouver:

Xie S. Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xie S. Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

4. Liao, Chun-Kai. A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 The proposed PLL in this thesis is implemented in TSMC 90nm 1P9M RF technology with a 1V supply voltage. This thesis presents a wide tuning… (more)

Subjects/Keywords: PLL; Controllable OTA; VCO; Charge Pump; PFD; Bootstrapped Switch

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liao, C. (2017). A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172335

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liao, Chun-Kai. “A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier.” 2017. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172335.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liao, Chun-Kai. “A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier.” 2017. Web. 20 Sep 2020.

Vancouver:

Liao C. A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172335.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liao C. A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172335

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

5. Chen, Hung-Yen. A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 In this thesis, a 10-bit binary search assisted two channel SAR ADC with a two bit per conversion and error tolerance ability operating in 250Ms/s… (more)

Subjects/Keywords: Two bits per conversion; Non-binary; Time-interleaved; Binary search; SAR ADC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, H. (2017). A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172820

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Hung-Yen. “A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability.” 2017. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172820.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Hung-Yen. “A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability.” 2017. Web. 20 Sep 2020.

Vancouver:

Chen H. A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172820.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen H. A 10-bit 250 MS/s Binary Search and two channel SAR ADC with a two bit per conversion and error tolerance ability. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-172820

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

6. Huang, Yi-Hsuan. VLSI Design And Implementation Of Low Bit-error Rate HomePlug AV System.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 This thesis implements the HomePlug AV power line communication system to reduce the probability of decoding errors caused by noise interference during transmission. The architecture… (more)

Subjects/Keywords: , PLC; FFT; QAM; Interleaver; Scramble; Turbo Code; OFDM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, Y. (2017). VLSI Design And Implementation Of Low Bit-error Rate HomePlug AV System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-182647

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Yi-Hsuan. “VLSI Design And Implementation Of Low Bit-error Rate HomePlug AV System.” 2017. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-182647.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Yi-Hsuan. “VLSI Design And Implementation Of Low Bit-error Rate HomePlug AV System.” 2017. Web. 20 Sep 2020.

Vancouver:

Huang Y. VLSI Design And Implementation Of Low Bit-error Rate HomePlug AV System. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-182647.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang Y. VLSI Design And Implementation Of Low Bit-error Rate HomePlug AV System. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814117-182647

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

7. Lee, Yao-Lun. A Programmable Gain Amplifier with Auto Gain Control Mechanism for the CMOS Image Sensor.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 In this thesis, a programmable gain amplifier for the CMOS image sensor is implemented by using the TSMC 0.18 ï­m process technology. The main circuit… (more)

Subjects/Keywords: programmable gain amplifier; dynamic comparator; switch capacitor amplifier; bandgap reference circuit; folded cascade operational amplifier

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lee, Y. (2018). A Programmable Gain Amplifier with Auto Gain Control Mechanism for the CMOS Image Sensor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-121128

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lee, Yao-Lun. “A Programmable Gain Amplifier with Auto Gain Control Mechanism for the CMOS Image Sensor.” 2018. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-121128.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lee, Yao-Lun. “A Programmable Gain Amplifier with Auto Gain Control Mechanism for the CMOS Image Sensor.” 2018. Web. 20 Sep 2020.

Vancouver:

Lee Y. A Programmable Gain Amplifier with Auto Gain Control Mechanism for the CMOS Image Sensor. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-121128.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee Y. A Programmable Gain Amplifier with Auto Gain Control Mechanism for the CMOS Image Sensor. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-121128

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

8. Chang, Jing-Sheng. A Novel Linear-Logarithmic Active Pixel Sensor for the CMOS Image Sensor with wide dynamic range.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 In this thesis, a new active pixel architecture is designed using TSMC 0.18μm 1P6M 1.8V mixed signal processing, which is different from linear pixel sensor… (more)

Subjects/Keywords: 3T APS; Dynamic Range; CMOS Image Sensor; Fill Factor; Logarithmic Pixel

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, J. (2018). A Novel Linear-Logarithmic Active Pixel Sensor for the CMOS Image Sensor with wide dynamic range. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-133453

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Jing-Sheng. “A Novel Linear-Logarithmic Active Pixel Sensor for the CMOS Image Sensor with wide dynamic range.” 2018. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-133453.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Jing-Sheng. “A Novel Linear-Logarithmic Active Pixel Sensor for the CMOS Image Sensor with wide dynamic range.” 2018. Web. 20 Sep 2020.

Vancouver:

Chang J. A Novel Linear-Logarithmic Active Pixel Sensor for the CMOS Image Sensor with wide dynamic range. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-133453.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang J. A Novel Linear-Logarithmic Active Pixel Sensor for the CMOS Image Sensor with wide dynamic range. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-133453

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

9. Chen, Yan-Lin. A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 In this thesis, a 10-bit, 10 MS/s dual-mode analog-to-digital converter with a 1.8 V supply voltage is implemented by using the TSMC 0.18ï­m process technology.… (more)

Subjects/Keywords: Dual-Mode; Edge Image; Image Sensor; Analog to Digital Converter; Successive Approximation Register

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, Y. (2018). A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-132437

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Yan-Lin. “A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor.” 2018. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-132437.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Yan-Lin. “A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor.” 2018. Web. 20 Sep 2020.

Vancouver:

Chen Y. A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-132437.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Y. A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-132437

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

10. Wu, Ching-Feng. Implementation of a 10-bit SAR ADC With Merge, Split, and Tri-Level Switching using Mortise-Tenon Structure Capacitor.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 This thesis presents a 10-bit 500 KS/s Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for biomedical application with a 0.5 V supply voltage which is… (more)

Subjects/Keywords: Successive Approximation Register ADC; Merge and Split Switching; Dummy Input Pair; Parasitic Minimization; Low Voltage; Mortise-Tenon structure; Tri-level Switching

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, C. (2018). Implementation of a 10-bit SAR ADC With Merge, Split, and Tri-Level Switching using Mortise-Tenon Structure Capacitor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0520118-082221

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Ching-Feng. “Implementation of a 10-bit SAR ADC With Merge, Split, and Tri-Level Switching using Mortise-Tenon Structure Capacitor.” 2018. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0520118-082221.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Ching-Feng. “Implementation of a 10-bit SAR ADC With Merge, Split, and Tri-Level Switching using Mortise-Tenon Structure Capacitor.” 2018. Web. 20 Sep 2020.

Vancouver:

Wu C. Implementation of a 10-bit SAR ADC With Merge, Split, and Tri-Level Switching using Mortise-Tenon Structure Capacitor. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0520118-082221.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu C. Implementation of a 10-bit SAR ADC With Merge, Split, and Tri-Level Switching using Mortise-Tenon Structure Capacitor. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0520118-082221

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

11. Liao, Pei-Tong. A mains interference rejection filter design in a wearable biomedical signal monitoring system.

Degree: Master, Electrical Engineering, 2018, NSYSU

 This thesis presents an adjustable filter which can reject the main interference in a wearable health care system. This AFE system is implemented in TSMC… (more)

Subjects/Keywords: Biomedical signal; IoT; SOC chip; high quality factor; notch filter; switched

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liao, P. (2018). A mains interference rejection filter design in a wearable biomedical signal monitoring system. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627118-235810

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liao, Pei-Tong. “A mains interference rejection filter design in a wearable biomedical signal monitoring system.” 2018. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627118-235810.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liao, Pei-Tong. “A mains interference rejection filter design in a wearable biomedical signal monitoring system.” 2018. Web. 20 Sep 2020.

Vancouver:

Liao P. A mains interference rejection filter design in a wearable biomedical signal monitoring system. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627118-235810.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liao P. A mains interference rejection filter design in a wearable biomedical signal monitoring system. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627118-235810

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

12. Ma, Jo-Yun. Automatic line interference detection and electrode rebalancing for wearable ECG front-end.

Degree: Master, Electrical Engineering, 2018, NSYSU

 To solve one of the major problems in recording biopotentials, which is the unwanted 60Hz interference produced by power line, an automatically adjusting resistors design… (more)

Subjects/Keywords: biomedical recording; dual potentiometers; undersampling; imbalance impedance; Goertzel algorithm

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ma, J. (2018). Automatic line interference detection and electrode rebalancing for wearable ECG front-end. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626118-223114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ma, Jo-Yun. “Automatic line interference detection and electrode rebalancing for wearable ECG front-end.” 2018. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626118-223114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ma, Jo-Yun. “Automatic line interference detection and electrode rebalancing for wearable ECG front-end.” 2018. Web. 20 Sep 2020.

Vancouver:

Ma J. Automatic line interference detection and electrode rebalancing for wearable ECG front-end. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626118-223114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ma J. Automatic line interference detection and electrode rebalancing for wearable ECG front-end. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626118-223114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

13. Lu, Chieh-Feng. Design and implementation of a 20MHz/32MHz PLL frequency Synthesizer in 180nm CMOS.

Degree: Master, Electrical Engineering, 2018, NSYSU

 This thesis presents a PLL based frequency synthesizer which is used to generate system clocks and sampling clocks for the front-end ASIC âIntegrated ExG, Vibration… (more)

Subjects/Keywords: Clock generator; PLL; Pulse Swallow; Synthesizer; Leakage-compensated

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lu, C. (2018). Design and implementation of a 20MHz/32MHz PLL frequency Synthesizer in 180nm CMOS. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623118-212500

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lu, Chieh-Feng. “Design and implementation of a 20MHz/32MHz PLL frequency Synthesizer in 180nm CMOS.” 2018. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623118-212500.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lu, Chieh-Feng. “Design and implementation of a 20MHz/32MHz PLL frequency Synthesizer in 180nm CMOS.” 2018. Web. 20 Sep 2020.

Vancouver:

Lu C. Design and implementation of a 20MHz/32MHz PLL frequency Synthesizer in 180nm CMOS. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623118-212500.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lu C. Design and implementation of a 20MHz/32MHz PLL frequency Synthesizer in 180nm CMOS. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623118-212500

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

14. Hsu, Chung-Jye. A PWM-based DC-DC Buck Converter with High-efficiency Light Load Mode Operation and SOC Estimation Circuit Using Coulomb Counting Method with Dynamic Voltage Calibration.

Degree: Master, Electrical Engineering, 2018, NSYSU

 The research topics of this thesis are related to two sub-circuits in a Battery Management System of the AUV research project, which are a PWM-based… (more)

Subjects/Keywords: battery; DC-DC converter; dynamic voltage; BMS; coulomb counting; power switches

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APA (6th Edition):

Hsu, C. (2018). A PWM-based DC-DC Buck Converter with High-efficiency Light Load Mode Operation and SOC Estimation Circuit Using Coulomb Counting Method with Dynamic Voltage Calibration. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631118-120005

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsu, Chung-Jye. “A PWM-based DC-DC Buck Converter with High-efficiency Light Load Mode Operation and SOC Estimation Circuit Using Coulomb Counting Method with Dynamic Voltage Calibration.” 2018. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631118-120005.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsu, Chung-Jye. “A PWM-based DC-DC Buck Converter with High-efficiency Light Load Mode Operation and SOC Estimation Circuit Using Coulomb Counting Method with Dynamic Voltage Calibration.” 2018. Web. 20 Sep 2020.

Vancouver:

Hsu C. A PWM-based DC-DC Buck Converter with High-efficiency Light Load Mode Operation and SOC Estimation Circuit Using Coulomb Counting Method with Dynamic Voltage Calibration. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631118-120005.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu C. A PWM-based DC-DC Buck Converter with High-efficiency Light Load Mode Operation and SOC Estimation Circuit Using Coulomb Counting Method with Dynamic Voltage Calibration. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631118-120005

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

15. Shih, Hsiang-Yu. 4-stage Pipeline ROM-less DDFS Using Equal Division Parabolic Polynomial Interpolation Method and Power Estimation for DDFS Designs Based on Switching Activity Analysis.

Degree: Master, Institute Of Electrical Engineering, 2018, NSYSU

 This thesis demonstrates two research topics for ROM-less DDFS (direct digital frequency synthesizer), including a 4-stage pipeline ROM-less DDFS design using equal division parabolic polynomial… (more)

Subjects/Keywords: DDFS; 2nd-order parabolic interpolation; pipeline structure; SFDR; switching activity; switching power estimation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shih, H. (2018). 4-stage Pipeline ROM-less DDFS Using Equal Division Parabolic Polynomial Interpolation Method and Power Estimation for DDFS Designs Based on Switching Activity Analysis. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631118-115435

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shih, Hsiang-Yu. “4-stage Pipeline ROM-less DDFS Using Equal Division Parabolic Polynomial Interpolation Method and Power Estimation for DDFS Designs Based on Switching Activity Analysis.” 2018. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631118-115435.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shih, Hsiang-Yu. “4-stage Pipeline ROM-less DDFS Using Equal Division Parabolic Polynomial Interpolation Method and Power Estimation for DDFS Designs Based on Switching Activity Analysis.” 2018. Web. 20 Sep 2020.

Vancouver:

Shih H. 4-stage Pipeline ROM-less DDFS Using Equal Division Parabolic Polynomial Interpolation Method and Power Estimation for DDFS Designs Based on Switching Activity Analysis. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631118-115435.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shih H. 4-stage Pipeline ROM-less DDFS Using Equal Division Parabolic Polynomial Interpolation Method and Power Estimation for DDFS Designs Based on Switching Activity Analysis. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0631118-115435

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

16. Huang, Hao-Chun. A Highly Sensitive Portable Microsystem for Rapid Marijuana Detection and A Peak Detector with Offset Cancellation.

Degree: Master, Electrical Engineering, 2018, NSYSU

 As early as in the 1960s, drugs abuse has long been a serious problem in the world.The most popular one is marijuana, where 160 million… (more)

Subjects/Keywords: peak detector; portable medical device; flexural plate wave microsonic sensor; resonant frequency shift; dynamic offset voltage cancellation

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APA (6th Edition):

Huang, H. (2018). A Highly Sensitive Portable Microsystem for Rapid Marijuana Detection and A Peak Detector with Offset Cancellation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629118-213302

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Hao-Chun. “A Highly Sensitive Portable Microsystem for Rapid Marijuana Detection and A Peak Detector with Offset Cancellation.” 2018. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629118-213302.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Hao-Chun. “A Highly Sensitive Portable Microsystem for Rapid Marijuana Detection and A Peak Detector with Offset Cancellation.” 2018. Web. 20 Sep 2020.

Vancouver:

Huang H. A Highly Sensitive Portable Microsystem for Rapid Marijuana Detection and A Peak Detector with Offset Cancellation. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629118-213302.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang H. A Highly Sensitive Portable Microsystem for Rapid Marijuana Detection and A Peak Detector with Offset Cancellation. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629118-213302

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

17. Shi, Po-Xu. Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator.

Degree: Master, Electrical Engineering, 2018, NSYSU

 This thesis realizes an application-specific integrated circuit (ASIC) implementation of adjustable frequency clock generator which combination of a one-bit quasi floating gate memory as reference… (more)

Subjects/Keywords: quasi floating gate memory; clock generator; adjustable frequency; application-specific integrated circuit; oscillator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shi, P. (2018). Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-144811

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shi, Po-Xu. “Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator.” 2018. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-144811.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shi, Po-Xu. “Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator.” 2018. Web. 20 Sep 2020.

Vancouver:

Shi P. Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-144811.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shi P. Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-144811

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

18. Yen, Huai-yu. Power Optimization for 3D Vertex Shader Using Clock Gating.

Degree: Master, Computer Science and Engineering, 2008, NSYSU

 With technology increasingly and the needs of high performance and multiple functionalities, power dissipation has be a bottleneck in microprocessors. And clock power is the… (more)

Subjects/Keywords: instruction schedule; 3D vertex shader; clock gating; Low power

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yen, H. (2008). Power Optimization for 3D Vertex Shader Using Clock Gating. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816108-003258

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yen, Huai-yu. “Power Optimization for 3D Vertex Shader Using Clock Gating.” 2008. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816108-003258.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yen, Huai-yu. “Power Optimization for 3D Vertex Shader Using Clock Gating.” 2008. Web. 20 Sep 2020.

Vancouver:

Yen H. Power Optimization for 3D Vertex Shader Using Clock Gating. [Internet] [Thesis]. NSYSU; 2008. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816108-003258.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yen H. Power Optimization for 3D Vertex Shader Using Clock Gating. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816108-003258

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

19. Wu, Zong-Lin. Low-Overhead Isolation Cells for Low-Power Multipliers.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

 With the rapid progress in manufacturing technology, the chip design is more and more complicated day by day. As a result, the circuit design with… (more)

Subjects/Keywords: low overhead isolation cell; standard cell; low-power multipliers

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APA (6th Edition):

Wu, Z. (2009). Low-Overhead Isolation Cells for Low-Power Multipliers. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Zong-Lin. “Low-Overhead Isolation Cells for Low-Power Multipliers.” 2009. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Zong-Lin. “Low-Overhead Isolation Cells for Low-Power Multipliers.” 2009. Web. 20 Sep 2020.

Vancouver:

Wu Z. Low-Overhead Isolation Cells for Low-Power Multipliers. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu Z. Low-Overhead Isolation Cells for Low-Power Multipliers. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

20. Yang, Cheng-Yen. IEEE 802.15.4 Protocol Stack Library Implementation,Hardware Design, and Applications in Medical Monitoring.

Degree: Master, Electrical Engineering, 2010, NSYSU

 Due to the rapid development of semiconductor technology, the number of transistors of integrated circuits in unit area increases by double in roughly every two… (more)

Subjects/Keywords: Protocol Stack Library; Clock-Gating; CSMA/CA; On-Chip-Bus; Medical Monitoring; Wireless Person Area Network; IEEE 802.15.4; Low power; Wireless Sensor Network; WISHBONE

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APA (6th Edition):

Yang, C. (2010). IEEE 802.15.4 Protocol Stack Library Implementation,Hardware Design, and Applications in Medical Monitoring. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712110-165927

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Cheng-Yen. “IEEE 802.15.4 Protocol Stack Library Implementation,Hardware Design, and Applications in Medical Monitoring.” 2010. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712110-165927.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Cheng-Yen. “IEEE 802.15.4 Protocol Stack Library Implementation,Hardware Design, and Applications in Medical Monitoring.” 2010. Web. 20 Sep 2020.

Vancouver:

Yang C. IEEE 802.15.4 Protocol Stack Library Implementation,Hardware Design, and Applications in Medical Monitoring. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712110-165927.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang C. IEEE 802.15.4 Protocol Stack Library Implementation,Hardware Design, and Applications in Medical Monitoring. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712110-165927

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

21. Chen, Chih-hung. 1MHz Bandwidth Switched-Current Sigma Delta Modulator.

Degree: Master, Electrical Engineering, 2010, NSYSU

 The thesis proposes an integrator with an OPAMP in the feedback loop to fulfill 1MHz bandwidth SI Sigma Delta modulator. The OPAMP is used to… (more)

Subjects/Keywords: delta-sigma modulator; sigma-delta modulator; switched-current circuit; integrator; sample and hole; current comparator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, C. (2010). 1MHz Bandwidth Switched-Current Sigma Delta Modulator. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901110-122544

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Chih-hung. “1MHz Bandwidth Switched-Current Sigma Delta Modulator.” 2010. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901110-122544.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Chih-hung. “1MHz Bandwidth Switched-Current Sigma Delta Modulator.” 2010. Web. 20 Sep 2020.

Vancouver:

Chen C. 1MHz Bandwidth Switched-Current Sigma Delta Modulator. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901110-122544.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen C. 1MHz Bandwidth Switched-Current Sigma Delta Modulator. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901110-122544

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

22. Lai, Kai-hsin. Bilinear Second Order Integral Bandpass Filter.

Degree: Master, Electrical Engineering, 2011, NSYSU

 Traditional transfer function of integrators have warping effect in high frequency, this isnât good for make filter circuit. In reference[3] they mention a new transfer… (more)

Subjects/Keywords: Filter; integrator; Modified; double sampling; bilinear

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lai, K. (2011). Bilinear Second Order Integral Bandpass Filter. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0125111-164403

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lai, Kai-hsin. “Bilinear Second Order Integral Bandpass Filter.” 2011. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0125111-164403.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lai, Kai-hsin. “Bilinear Second Order Integral Bandpass Filter.” 2011. Web. 20 Sep 2020.

Vancouver:

Lai K. Bilinear Second Order Integral Bandpass Filter. [Internet] [Thesis]. NSYSU; 2011. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0125111-164403.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lai K. Bilinear Second Order Integral Bandpass Filter. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0125111-164403

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

23. Lin, Shin-Yang. A CMOS LNA for 3.1-10.6GHz Ultra-Wideband.

Degree: Master, Electrical Engineering, 2011, NSYSU

 The objective of this thesis is aimed at the design of low noise amplifier (LNA) for an ultra-wideband (UWB) receiver system using standard 0.18um CMOS… (more)

Subjects/Keywords: low noise amplifier; input matching; Series-peaking; Resistive-feedback; Ultra-wideband; CMOS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, S. (2011). A CMOS LNA for 3.1-10.6GHz Ultra-Wideband. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0125111-154905

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Shin-Yang. “A CMOS LNA for 3.1-10.6GHz Ultra-Wideband.” 2011. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0125111-154905.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Shin-Yang. “A CMOS LNA for 3.1-10.6GHz Ultra-Wideband.” 2011. Web. 20 Sep 2020.

Vancouver:

Lin S. A CMOS LNA for 3.1-10.6GHz Ultra-Wideband. [Internet] [Thesis]. NSYSU; 2011. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0125111-154905.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin S. A CMOS LNA for 3.1-10.6GHz Ultra-Wideband. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0125111-154905

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

24. Wang, Deng-Shian. A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS.

Degree: Master, Electrical Engineering, 2013, NSYSU

 This thesis includes two designs: A high-voltage (HV) multiplexer and a successive-approximation register ADC for Battery Management Systems (BMS). The proposed designs are implemented by… (more)

Subjects/Keywords: BMS; high-voltage multiplexer; charge redistribution architecture; successive-approximation register ADC; high-voltage switch

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, D. (2013). A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0608113-213119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Deng-Shian. “A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS.” 2013. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0608113-213119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Deng-Shian. “A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS.” 2013. Web. 20 Sep 2020.

Vancouver:

Wang D. A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0608113-213119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang D. A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0608113-213119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

25. Hu , Yi. A Receiver with Over-Voltage Protection for FlexRay Systems and an 8:1 High-Voltage Analog Multiplexer for Battery Management Systems.

Degree: Master, Electrical Engineering, 2013, NSYSU

 The research of this thesis is mainly focused on automotive electronics including two topics, a Receiver (Rx) with over-voltage protection for FlexRay systems and an… (more)

Subjects/Keywords: over-voltage protection; HV switches; FlexRay Receiver; BMS; HV MUX

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hu , Y. (2013). A Receiver with Over-Voltage Protection for FlexRay Systems and an 8:1 High-Voltage Analog Multiplexer for Battery Management Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-151412

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hu , Yi. “A Receiver with Over-Voltage Protection for FlexRay Systems and an 8:1 High-Voltage Analog Multiplexer for Battery Management Systems.” 2013. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-151412.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hu , Yi. “A Receiver with Over-Voltage Protection for FlexRay Systems and an 8:1 High-Voltage Analog Multiplexer for Battery Management Systems.” 2013. Web. 20 Sep 2020.

Vancouver:

Hu Y. A Receiver with Over-Voltage Protection for FlexRay Systems and an 8:1 High-Voltage Analog Multiplexer for Battery Management Systems. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-151412.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hu Y. A Receiver with Over-Voltage Protection for FlexRay Systems and an 8:1 High-Voltage Analog Multiplexer for Battery Management Systems. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0610113-151412

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

26. Liao, Chiang-Hsiang. Development of A Rapid Readout System for CEA Detection and An SRAM with Leakage Sensor and Read Delay Compensation.

Degree: Master, Electrical Engineering, 2014, NSYSU

 This thesis is composed of a biomedical sensing system design and a novel circuit design of 5T SRAM (static random access memory, SRAM). The first… (more)

Subjects/Keywords: leakage current sensor; SRAM; readout circuit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liao, C. (2014). Development of A Rapid Readout System for CEA Detection and An SRAM with Leakage Sensor and Read Delay Compensation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135024

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liao, Chiang-Hsiang. “Development of A Rapid Readout System for CEA Detection and An SRAM with Leakage Sensor and Read Delay Compensation.” 2014. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135024.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liao, Chiang-Hsiang. “Development of A Rapid Readout System for CEA Detection and An SRAM with Leakage Sensor and Read Delay Compensation.” 2014. Web. 20 Sep 2020.

Vancouver:

Liao C. Development of A Rapid Readout System for CEA Detection and An SRAM with Leakage Sensor and Read Delay Compensation. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135024.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liao C. Development of A Rapid Readout System for CEA Detection and An SRAM with Leakage Sensor and Read Delay Compensation. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135024

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

27. Bai, Je-Wei. A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 In this thesis, a 10-bit, 80 MS/s analog-to-digital converter with a 1 V supply voltage is implemented by using the TSMC 90nm process technology. This… (more)

Subjects/Keywords: non-binary digital error correction; digital error correction; 2b/Cycle; Successive Approximation Register; Analog to Digital Converter

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bai, J. (2016). A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bai, Je-Wei. “A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction.” 2016. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bai, Je-Wei. “A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction.” 2016. Web. 20 Sep 2020.

Vancouver:

Bai J. A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bai J. A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

28. Sung, Ying-Ju. A 12-bit Digital-to-Analog Converter with the specified code and thermometer code decoder.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 With the continuous development of technology, mobile communication device has more and more demand for function, with the widespread use of smartphones and, increasingly, APP… (more)

Subjects/Keywords: digital-to-analog converter; the specified code; high precision; small area; high speed

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sung, Y. (2016). A 12-bit Digital-to-Analog Converter with the specified code and thermometer code decoder. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-160737

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sung, Ying-Ju. “A 12-bit Digital-to-Analog Converter with the specified code and thermometer code decoder.” 2016. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-160737.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sung, Ying-Ju. “A 12-bit Digital-to-Analog Converter with the specified code and thermometer code decoder.” 2016. Web. 20 Sep 2020.

Vancouver:

Sung Y. A 12-bit Digital-to-Analog Converter with the specified code and thermometer code decoder. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-160737.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sung Y. A 12-bit Digital-to-Analog Converter with the specified code and thermometer code decoder. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-160737

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

29. Liou, Shih-Hao. All-Digital SAR-Controlled Delay-Locked Loop with Tracking System Based on Thermometer Code.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 This All-Digital delay-locked loop uses TSMC90nm process. It uses digital phase detector and successive approximation register to control the digital delay line as well as… (more)

Subjects/Keywords: binary-weighted code; successive approximation register; delay lock loop; thermometer code; low power

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liou, S. (2016). All-Digital SAR-Controlled Delay-Locked Loop with Tracking System Based on Thermometer Code. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729116-130544

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liou, Shih-Hao. “All-Digital SAR-Controlled Delay-Locked Loop with Tracking System Based on Thermometer Code.” 2016. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729116-130544.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liou, Shih-Hao. “All-Digital SAR-Controlled Delay-Locked Loop with Tracking System Based on Thermometer Code.” 2016. Web. 20 Sep 2020.

Vancouver:

Liou S. All-Digital SAR-Controlled Delay-Locked Loop with Tracking System Based on Thermometer Code. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729116-130544.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liou S. All-Digital SAR-Controlled Delay-Locked Loop with Tracking System Based on Thermometer Code. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729116-130544

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

30. Chang, Chia-ming. A 10-bit Process-Calibrated Current-Steering D/A Converter and High Bandwidth and High Coversion Gain Power Detector for Frequency-Shift Readout Systems.

Degree: Master, Electrical Engineering, 2014, NSYSU

 Since the combination of antigens with the corresponding antibody will change the resonant frequency of certain MEMS sensors, this kind of technology is often utilized… (more)

Subjects/Keywords: current-steering; process-calibrated; DAC; power detector

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, C. (2014). A 10-bit Process-Calibrated Current-Steering D/A Converter and High Bandwidth and High Coversion Gain Power Detector for Frequency-Shift Readout Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-155610

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Chia-ming. “A 10-bit Process-Calibrated Current-Steering D/A Converter and High Bandwidth and High Coversion Gain Power Detector for Frequency-Shift Readout Systems.” 2014. Thesis, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-155610.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Chia-ming. “A 10-bit Process-Calibrated Current-Steering D/A Converter and High Bandwidth and High Coversion Gain Power Detector for Frequency-Shift Readout Systems.” 2014. Web. 20 Sep 2020.

Vancouver:

Chang C. A 10-bit Process-Calibrated Current-Steering D/A Converter and High Bandwidth and High Coversion Gain Power Detector for Frequency-Shift Readout Systems. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-155610.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang C. A 10-bit Process-Calibrated Current-Steering D/A Converter and High Bandwidth and High Coversion Gain Power Detector for Frequency-Shift Readout Systems. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-155610

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2] [3] [4]

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