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You searched for +publisher:"NSYSU" +contributor:("Ing-Jer Huang"). Showing records 1 – 30 of 70 total matches.

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NSYSU

1. Lin, Tsung-Chen. Design and Verification of ARM10 ICE Co-Processor.

Degree: Master, Computer Science and Engineering, 2011, NSYSU

 Embedded in circuit emulator (EICE) is the most common and widely used debugging techniques for microprocessors. Because the ICE is capable to provide diverse debugging… (more)

Subjects/Keywords: Coprocessor; Embedded in circuit emulator (EICE); Real-time system debug; Microprocessor; Static Debug

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, T. (2011). Design and Verification of ARM10 ICE Co-Processor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811111-035510

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Tsung-Chen. “Design and Verification of ARM10 ICE Co-Processor.” 2011. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811111-035510.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Tsung-Chen. “Design and Verification of ARM10 ICE Co-Processor.” 2011. Web. 22 Feb 2020.

Vancouver:

Lin T. Design and Verification of ARM10 ICE Co-Processor. [Internet] [Thesis]. NSYSU; 2011. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811111-035510.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin T. Design and Verification of ARM10 ICE Co-Processor. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811111-035510

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

2. Lin, Ding-Zhi. Integrated Circuit Designs for a Multi-signal Biomedical Signal Recording Chip.

Degree: Master, Electrical Engineering, 2018, NSYSU

 With the advance of mobile healthcare and the Internet-of-things increasing numbers of applications incorporate low-power miniature sensing devices for various types of input signal. In… (more)

Subjects/Keywords: biomedical chip; adjustable gain; switched capacitor amplifier; integrated circuit; temperature monitoring circuit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, D. (2018). Integrated Circuit Designs for a Multi-signal Biomedical Signal Recording Chip. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0029118-150639

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Ding-Zhi. “Integrated Circuit Designs for a Multi-signal Biomedical Signal Recording Chip.” 2018. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0029118-150639.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Ding-Zhi. “Integrated Circuit Designs for a Multi-signal Biomedical Signal Recording Chip.” 2018. Web. 22 Feb 2020.

Vancouver:

Lin D. Integrated Circuit Designs for a Multi-signal Biomedical Signal Recording Chip. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0029118-150639.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin D. Integrated Circuit Designs for a Multi-signal Biomedical Signal Recording Chip. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0029118-150639

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

3. Lin, Ching-Yuan. Performance Modeling for a 3D Graphics SoC.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

 The design of SoC is growing into more complicated, hence it is necessary to determine an efficient way to develop an SoC. If we can… (more)

Subjects/Keywords: 3D Graphics; Tile-based; analysis; SystemC; TLM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, C. (2009). Performance Modeling for a 3D Graphics SoC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Ching-Yuan. “Performance Modeling for a 3D Graphics SoC.” 2009. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Ching-Yuan. “Performance Modeling for a 3D Graphics SoC.” 2009. Web. 22 Feb 2020.

Vancouver:

Lin C. Performance Modeling for a 3D Graphics SoC. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin C. Performance Modeling for a 3D Graphics SoC. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

4. Wu, Cheng-Ta. SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 Nowadays, due to improvement of fabrication and IP design technology, the design complexity of System on Chip is increasing very fast. Thus we need huge… (more)

Subjects/Keywords: BUS; AXI; AHB; Verification; OpenGL ES2.0; Integration

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APA (6th Edition):

Wu, C. (2013). SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1015113-190908

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Cheng-Ta. “SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC.” 2013. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1015113-190908.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Cheng-Ta. “SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC.” 2013. Web. 22 Feb 2020.

Vancouver:

Wu C. SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1015113-190908.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu C. SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1015113-190908

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

5. DOW, HSU-KANG. A Simulator for a Novel GPU to Support the Verifying and Profiling in Real World Applications.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 This is a simulator created base on Attila, a modern GPU architecture and open source project with the power to run games and benchmarks. This… (more)

Subjects/Keywords: GPU; OpenGL ES; GLSL ES; Simulator; Attila

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

DOW, H. (2014). A Simulator for a Novel GPU to Support the Verifying and Profiling in Real World Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0027114-173404

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

DOW, HSU-KANG. “A Simulator for a Novel GPU to Support the Verifying and Profiling in Real World Applications.” 2014. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0027114-173404.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

DOW, HSU-KANG. “A Simulator for a Novel GPU to Support the Verifying and Profiling in Real World Applications.” 2014. Web. 22 Feb 2020.

Vancouver:

DOW H. A Simulator for a Novel GPU to Support the Verifying and Profiling in Real World Applications. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0027114-173404.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

DOW H. A Simulator for a Novel GPU to Support the Verifying and Profiling in Real World Applications. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0027114-173404

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

6. Lu, Yao-Ta. Design of Low-cost BVH Construction Circuit for Ray Tracing based on Surface Area Heuristic Metric.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 The acceleration of tree construction is a very important issue for real-time ray-tracing of dynamic scenes. This paper presents a low-cost design of bounding volume… (more)

Subjects/Keywords: ray-tracing; BVH; computer graphics; BVH tree construction; ray-tracing hardware

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lu, Y. (2014). Design of Low-cost BVH Construction Circuit for Ray Tracing based on Surface Area Heuristic Metric. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627114-221628

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lu, Yao-Ta. “Design of Low-cost BVH Construction Circuit for Ray Tracing based on Surface Area Heuristic Metric.” 2014. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627114-221628.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lu, Yao-Ta. “Design of Low-cost BVH Construction Circuit for Ray Tracing based on Surface Area Heuristic Metric.” 2014. Web. 22 Feb 2020.

Vancouver:

Lu Y. Design of Low-cost BVH Construction Circuit for Ray Tracing based on Surface Area Heuristic Metric. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627114-221628.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lu Y. Design of Low-cost BVH Construction Circuit for Ray Tracing based on Surface Area Heuristic Metric. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627114-221628

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

7. yang, Ho-chun. Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 With the increasing demand of embedded graphic processing unit (GPU), how to develop an efficient GPU has become more and more important. This thesis proposed… (more)

Subjects/Keywords: Unified GPU; Multithreading; Branch divergence; Multi-core; SIMT

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

yang, H. (2014). Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-141237

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

yang, Ho-chun. “Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture.” 2014. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-141237.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

yang, Ho-chun. “Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture.” 2014. Web. 22 Feb 2020.

Vancouver:

yang H. Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-141237.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

yang H. Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-141237

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

8. Lin, Chin-li. A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Although the rendering speed of modern GPUs is dramatically improved, it is still not fast enough for some applications such as real time rendering and… (more)

Subjects/Keywords: GPU; hardware; billboard; impostor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, C. (2014). A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Chin-li. “A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering.” 2014. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Chin-li. “A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering.” 2014. Web. 22 Feb 2020.

Vancouver:

Lin C. A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin C. A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

9. Wang, Huei-siang. Design of stochastic LDPC decoder for IEEE 802.16e standard.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 This thesis proposed an efficient design of stochastic low-density parity code ï¼LDPCï¼ decoder for IEEE 802.16e standard. Based on the proposed majority edge memory ï¼MEMï¼… (more)

Subjects/Keywords: FPGA; stochastic computing; stochastic decoding; low-density parity-checkï¼LDPCï¼codes; iterative decoding

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, H. (2014). Design of stochastic LDPC decoder for IEEE 802.16e standard. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801114-142617

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Huei-siang. “Design of stochastic LDPC decoder for IEEE 802.16e standard.” 2014. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801114-142617.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Huei-siang. “Design of stochastic LDPC decoder for IEEE 802.16e standard.” 2014. Web. 22 Feb 2020.

Vancouver:

Wang H. Design of stochastic LDPC decoder for IEEE 802.16e standard. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801114-142617.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang H. Design of stochastic LDPC decoder for IEEE 802.16e standard. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801114-142617

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

10. Hsu, Wen-yen. Battery Emulator Circuit for The Application of Energy Measurement.

Degree: Master, Electrical Engineering, 2015, NSYSU

 In recent years, electronic products became portable and have lowered power consumption because of the limited energy resource availability. The measurement of energy consumption of… (more)

Subjects/Keywords: capacitor changing; simulating battery lifetime; dynamic emulator; current measurement; energy consumption

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hsu, W. (2015). Battery Emulator Circuit for The Application of Energy Measurement. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0913115-130616

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsu, Wen-yen. “Battery Emulator Circuit for The Application of Energy Measurement.” 2015. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0913115-130616.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsu, Wen-yen. “Battery Emulator Circuit for The Application of Energy Measurement.” 2015. Web. 22 Feb 2020.

Vancouver:

Hsu W. Battery Emulator Circuit for The Application of Energy Measurement. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0913115-130616.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu W. Battery Emulator Circuit for The Application of Energy Measurement. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0913115-130616

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

11. Yu, Rui-Hsiu. A Piezoelectric Energy Harvester and MOS Floating Gate Memory towards Wearable Strain Metering.

Degree: Master, Electrical Engineering, 2015, NSYSU

 With increasing levels of health awareness among people, the importance of long-term medical monitoring has increased along with the need for body detection at any… (more)

Subjects/Keywords: Energy Harvesting; Floating gate memory; Piezoelectric; Long-term wearable monitoring; Wearable circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yu, R. (2015). A Piezoelectric Energy Harvester and MOS Floating Gate Memory towards Wearable Strain Metering. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0913115-134153

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yu, Rui-Hsiu. “A Piezoelectric Energy Harvester and MOS Floating Gate Memory towards Wearable Strain Metering.” 2015. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0913115-134153.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yu, Rui-Hsiu. “A Piezoelectric Energy Harvester and MOS Floating Gate Memory towards Wearable Strain Metering.” 2015. Web. 22 Feb 2020.

Vancouver:

Yu R. A Piezoelectric Energy Harvester and MOS Floating Gate Memory towards Wearable Strain Metering. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0913115-134153.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yu R. A Piezoelectric Energy Harvester and MOS Floating Gate Memory towards Wearable Strain Metering. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0913115-134153

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

12. Chang, Sheng-Chang. A GPU hardware-based method for automatic occlusion detection and optimization for objects and subobjects.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

 This thesis looks at how the GPUâs processing of objects can be simplified (from the programmerâs point of view) and improved (from the run-time point… (more)

Subjects/Keywords: GPU; Occlusion; Object; Subobjects; Hulls; Software and Hardware Modification

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, S. (2012). A GPU hardware-based method for automatic occlusion detection and optimization for objects and subobjects. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1228112-025111

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Sheng-Chang. “A GPU hardware-based method for automatic occlusion detection and optimization for objects and subobjects.” 2012. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1228112-025111.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Sheng-Chang. “A GPU hardware-based method for automatic occlusion detection and optimization for objects and subobjects.” 2012. Web. 22 Feb 2020.

Vancouver:

Chang S. A GPU hardware-based method for automatic occlusion detection and optimization for objects and subobjects. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1228112-025111.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang S. A GPU hardware-based method for automatic occlusion detection and optimization for objects and subobjects. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1228112-025111

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

13. Lin, Chun-Shou. Design and verification of an ARM10-like Processor and its System Integration.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

 With the advanced of the technique, we can design more IP in the same area space chip. The embedded system has more powerful about its… (more)

Subjects/Keywords: Integration; Embedded in circuit emulator (EICE); Microprocessor; Verification; Cache/MMU; Coprocessor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, C. (2012). Design and verification of an ARM10-like Processor and its System Integration. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0207112-161403

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Chun-Shou. “Design and verification of an ARM10-like Processor and its System Integration.” 2012. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0207112-161403.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Chun-Shou. “Design and verification of an ARM10-like Processor and its System Integration.” 2012. Web. 22 Feb 2020.

Vancouver:

Lin C. Design and verification of an ARM10-like Processor and its System Integration. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0207112-161403.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin C. Design and verification of an ARM10-like Processor and its System Integration. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0207112-161403

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

14. Huang, Tzu-Ming. SoC Integration and Verification of a 3D Graphics SoC.

Degree: Master, Computer Science and Engineering, 2011, NSYSU

 While consumer demand for electronic equipment and more mature systems integration capabilities, it makes the system complexity of chip design increasing significantly. Also accompany an… (more)

Subjects/Keywords: Verification; Bus Bridge; SoC; 3D Graphics; Integration

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, T. (2011). SoC Integration and Verification of a 3D Graphics SoC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726111-112303

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Tzu-Ming. “SoC Integration and Verification of a 3D Graphics SoC.” 2011. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726111-112303.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Tzu-Ming. “SoC Integration and Verification of a 3D Graphics SoC.” 2011. Web. 22 Feb 2020.

Vancouver:

Huang T. SoC Integration and Verification of a 3D Graphics SoC. [Internet] [Thesis]. NSYSU; 2011. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726111-112303.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang T. SoC Integration and Verification of a 3D Graphics SoC. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726111-112303

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

15. Liu, Yue-qu. Reconfigurable Design and Implementation of Modular-Construction Based FFT Hardware Architecture.

Degree: Master, Electrical Engineering, 2018, NSYSU

 In the 3GPP-LTE communication standard, it defines many kinds of Fast Fourier Transform(FFT) sizes. So, we design a high performance FFT architecture which makes good… (more)

Subjects/Keywords: fast Fourier transform (FFT); 3GPP-LTE; reconfigurable (RC); multi-mode; single-path delay feedback (SDF)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, Y. (2018). Reconfigurable Design and Implementation of Modular-Construction Based FFT Hardware Architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016118-164748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Yue-qu. “Reconfigurable Design and Implementation of Modular-Construction Based FFT Hardware Architecture.” 2018. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016118-164748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Yue-qu. “Reconfigurable Design and Implementation of Modular-Construction Based FFT Hardware Architecture.” 2018. Web. 22 Feb 2020.

Vancouver:

Liu Y. Reconfigurable Design and Implementation of Modular-Construction Based FFT Hardware Architecture. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016118-164748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu Y. Reconfigurable Design and Implementation of Modular-Construction Based FFT Hardware Architecture. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016118-164748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

16. Ke, Yi-Ju. Critical Signature Assertion and On-the-Fly Recovery for Control Flow Errors in Processors.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 For the real-time systems, the error detection and recovery of the transient fault have become an important issue to improve the reliability. In previous works,… (more)

Subjects/Keywords: Microprocessor; Fault-Tolerant; Signature; Checkpoint and Recovery; Data Error; Control Flow Error

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ke, Y. (2018). Critical Signature Assertion and On-the-Fly Recovery for Control Flow Errors in Processors. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0402118-084552

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ke, Yi-Ju. “Critical Signature Assertion and On-the-Fly Recovery for Control Flow Errors in Processors.” 2018. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0402118-084552.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ke, Yi-Ju. “Critical Signature Assertion and On-the-Fly Recovery for Control Flow Errors in Processors.” 2018. Web. 22 Feb 2020.

Vancouver:

Ke Y. Critical Signature Assertion and On-the-Fly Recovery for Control Flow Errors in Processors. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0402118-084552.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ke Y. Critical Signature Assertion and On-the-Fly Recovery for Control Flow Errors in Processors. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0402118-084552

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

17. Hung, Tsz-En. A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 The graphics processing units (GPUs) commonly used in mobile devices differ from those used in PCs, owing to cost and power constraints. Some embedded GPUs… (more)

Subjects/Keywords: GPU; Tile based rendering; Billboard textures; GPU memory modeling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hung, T. (2017). A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820117-170503

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hung, Tsz-En. “A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs.” 2017. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820117-170503.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hung, Tsz-En. “A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs.” 2017. Web. 22 Feb 2020.

Vancouver:

Hung T. A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820117-170503.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hung T. A Memory-Cost-Aware Method to Reuse Imposter Billboards for Improving the Performance of Object Rendering on Tile-Based GPUs. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820117-170503

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

18. Peng, Zih-Yun. Implementing a Worst-Case Execution Time ILP Memory Model for a Static Analysis Tool.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 Real-time systems impose deadlines on tasks. Hard real-time systems require a guarantee that no deadline is ever missed. Such a guarantee is impossible if a… (more)

Subjects/Keywords: Hard Real-Time; WCET; Static Analysis; Memory Model; SWEET; ARM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Peng, Z. (2017). Implementing a Worst-Case Execution Time ILP Memory Model for a Static Analysis Tool. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0517116-190203

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Peng, Zih-Yun. “Implementing a Worst-Case Execution Time ILP Memory Model for a Static Analysis Tool.” 2017. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0517116-190203.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Peng, Zih-Yun. “Implementing a Worst-Case Execution Time ILP Memory Model for a Static Analysis Tool.” 2017. Web. 22 Feb 2020.

Vancouver:

Peng Z. Implementing a Worst-Case Execution Time ILP Memory Model for a Static Analysis Tool. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0517116-190203.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Peng Z. Implementing a Worst-Case Execution Time ILP Memory Model for a Static Analysis Tool. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0517116-190203

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

19. Chiang, Cheng-lung. An Embedded Multi-Resolution AXI Bus Tracer for SOC Development.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 Debugging in the System-on-a-Chip (SoC) environment is a challenge since it was hard to observe their signals on a chip. How to obtain the chip… (more)

Subjects/Keywords: Debug; Trace; Reverse encoding; Compression; Bus

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chiang, C. (2010). An Embedded Multi-Resolution AXI Bus Tracer for SOC Development. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721110-002943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chiang, Cheng-lung. “An Embedded Multi-Resolution AXI Bus Tracer for SOC Development.” 2010. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721110-002943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chiang, Cheng-lung. “An Embedded Multi-Resolution AXI Bus Tracer for SOC Development.” 2010. Web. 22 Feb 2020.

Vancouver:

Chiang C. An Embedded Multi-Resolution AXI Bus Tracer for SOC Development. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721110-002943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chiang C. An Embedded Multi-Resolution AXI Bus Tracer for SOC Development. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721110-002943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

20. Huang, Shih-tung. Hardware/software co-verification for processor-OpenOCD integration.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 We usually use RVDS [18] (RealView Development Suite) and MUlTI-ICE (protocol converter) as ARM program debug environment by controlling ICE module for controlling CPU. But… (more)

Subjects/Keywords: OpenOCD (Open On-Chip Debugger); GNU Debugger; Co-verification; EICE (Embedded In-Circuit Emulator); JTAG

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, S. (2013). Hardware/software co-verification for processor-OpenOCD integration. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715113-211836

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Shih-tung. “Hardware/software co-verification for processor-OpenOCD integration.” 2013. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715113-211836.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Shih-tung. “Hardware/software co-verification for processor-OpenOCD integration.” 2013. Web. 22 Feb 2020.

Vancouver:

Huang S. Hardware/software co-verification for processor-OpenOCD integration. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715113-211836.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang S. Hardware/software co-verification for processor-OpenOCD integration. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715113-211836

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

21. Huang, Ching-Hua. Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 In recent years, the popularity of handheld smart devices.In order to the demand of consumer and rapid progress of the technological process; Although the design… (more)

Subjects/Keywords: Chip Tape-out; Logic Synthesis; Syetem-on-Chip; Three-dimensional Graphics; Layout

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, C. (2014). Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-111344

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Ching-Hua. “Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC.” 2014. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-111344.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Ching-Hua. “Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC.” 2014. Web. 22 Feb 2020.

Vancouver:

Huang C. Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-111344.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang C. Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-111344

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

22. Wu , Ting-Hsuan. Socket-based Software and Hardware performance co-monitoring in AXI interconnect SoC.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Embedded systems are contained in many kinds of hardware resources and software processes today. Since the SoC industry has shift its development goal from processor… (more)

Subjects/Keywords: Socket-based transaction state monitor; Performance monitoring; Performance analysis; Transaction; Software

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu , T. (2014). Socket-based Software and Hardware performance co-monitoring in AXI interconnect SoC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-150954

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu , Ting-Hsuan. “Socket-based Software and Hardware performance co-monitoring in AXI interconnect SoC.” 2014. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-150954.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu , Ting-Hsuan. “Socket-based Software and Hardware performance co-monitoring in AXI interconnect SoC.” 2014. Web. 22 Feb 2020.

Vancouver:

Wu T. Socket-based Software and Hardware performance co-monitoring in AXI interconnect SoC. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-150954.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu T. Socket-based Software and Hardware performance co-monitoring in AXI interconnect SoC. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-150954

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

23. Hou, Shao-Chieh. Integration of C Source Level Debugging and HW Tracing and Monitoring.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 With the increasing of manufacture and software design technology, embedded system now become more and more complex, time-to-market also become more short. For integrated a… (more)

Subjects/Keywords: Debugger; JTAG; Co-Debugging

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hou, S. (2014). Integration of C Source Level Debugging and HW Tracing and Monitoring. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-115349

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hou, Shao-Chieh. “Integration of C Source Level Debugging and HW Tracing and Monitoring.” 2014. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-115349.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hou, Shao-Chieh. “Integration of C Source Level Debugging and HW Tracing and Monitoring.” 2014. Web. 22 Feb 2020.

Vancouver:

Hou S. Integration of C Source Level Debugging and HW Tracing and Monitoring. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-115349.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hou S. Integration of C Source Level Debugging and HW Tracing and Monitoring. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-115349

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

24. Yang, Yun-Chung. A Reconfigurable Cache for Efficient Usage of the Tag RAM Space.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 In almost every typical SoCs (System-on-Chip) in modern days, the size of cache grows larger as new SoC fabrics enhanced to satisfy the variety of… (more)

Subjects/Keywords: Memory architecture; Cache

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, Y. (2014). A Reconfigurable Cache for Efficient Usage of the Tag RAM Space. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-114613

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Yun-Chung. “A Reconfigurable Cache for Efficient Usage of the Tag RAM Space.” 2014. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-114613.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Yun-Chung. “A Reconfigurable Cache for Efficient Usage of the Tag RAM Space.” 2014. Web. 22 Feb 2020.

Vancouver:

Yang Y. A Reconfigurable Cache for Efficient Usage of the Tag RAM Space. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-114613.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang Y. A Reconfigurable Cache for Efficient Usage of the Tag RAM Space. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-114613

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

25. Lee, Ping-Chun. Reconfigurable Performance/Protocol Monitoring Design Kit for On-Chip Interconnect Development.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Today, due to the process of semiconductor improve rapidly, the number of transistors and functions in the same area of a chip becomes more than… (more)

Subjects/Keywords: reconfigurable; bus protocol; monitor; area; performance

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APA (6th Edition):

Lee, P. (2014). Reconfigurable Performance/Protocol Monitoring Design Kit for On-Chip Interconnect Development. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-115527

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lee, Ping-Chun. “Reconfigurable Performance/Protocol Monitoring Design Kit for On-Chip Interconnect Development.” 2014. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-115527.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lee, Ping-Chun. “Reconfigurable Performance/Protocol Monitoring Design Kit for On-Chip Interconnect Development.” 2014. Web. 22 Feb 2020.

Vancouver:

Lee P. Reconfigurable Performance/Protocol Monitoring Design Kit for On-Chip Interconnect Development. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-115527.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee P. Reconfigurable Performance/Protocol Monitoring Design Kit for On-Chip Interconnect Development. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-115527

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

26. Li, Jyun-yan. Verification of Instruction Set Compatible Processors with a Dual Core Environment.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 For improving the performance of microprocessor becomes more and more complex with the microprocessor techniques improvement. This improvement leads to verify microprocessor behaviors that becoming… (more)

Subjects/Keywords: Dual Core Verification; Microprocessor; Synchronization; Chip-level Redundant Threading; Dual Modular Redundancy

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, J. (2014). Verification of Instruction Set Compatible Processors with a Dual Core Environment. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-160709

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Jyun-yan. “Verification of Instruction Set Compatible Processors with a Dual Core Environment.” 2014. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-160709.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Jyun-yan. “Verification of Instruction Set Compatible Processors with a Dual Core Environment.” 2014. Web. 22 Feb 2020.

Vancouver:

Li J. Verification of Instruction Set Compatible Processors with a Dual Core Environment. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-160709.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li J. Verification of Instruction Set Compatible Processors with a Dual Core Environment. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-160709

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

27. Chen, Chien-Chih. The Linux Porting and Integration Verification of An Academic 32-bit Processor.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

 For improving the performance and application of microprocessor, it is necessary to integrate pipelined core, exception control unit, cache unit and memory management unit (MMU).… (more)

Subjects/Keywords: microprocessor; cache transfer operation; page fault; operating system; integration verification; external interrupt

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, C. (2012). The Linux Porting and Integration Verification of An Academic 32-bit Processor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-214712

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Chien-Chih. “The Linux Porting and Integration Verification of An Academic 32-bit Processor.” 2012. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-214712.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Chien-Chih. “The Linux Porting and Integration Verification of An Academic 32-bit Processor.” 2012. Web. 22 Feb 2020.

Vancouver:

Chen C. The Linux Porting and Integration Verification of An Academic 32-bit Processor. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-214712.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen C. The Linux Porting and Integration Verification of An Academic 32-bit Processor. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-214712

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

28. Wang, Chun-Hao. Heterogeneous QEMU-SystemC Integration for Timed CPU/Cache/MMU/DRAM/Component Simulation: A case study in 3D Graphics SoC.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

 Nowadays the designs of HW/SW are extremely complex. HW/SW co-verification is really difficult, consequently the new design layer, Electronic-System Level (ESL), is proposed to replace… (more)

Subjects/Keywords: HW/SW co-verification; QEMU; SystemC; 3D graphic SoC; Performance Estimation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, C. (2012). Heterogeneous QEMU-SystemC Integration for Timed CPU/Cache/MMU/DRAM/Component Simulation: A case study in 3D Graphics SoC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1015112-234055

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Chun-Hao. “Heterogeneous QEMU-SystemC Integration for Timed CPU/Cache/MMU/DRAM/Component Simulation: A case study in 3D Graphics SoC.” 2012. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1015112-234055.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Chun-Hao. “Heterogeneous QEMU-SystemC Integration for Timed CPU/Cache/MMU/DRAM/Component Simulation: A case study in 3D Graphics SoC.” 2012. Web. 22 Feb 2020.

Vancouver:

Wang C. Heterogeneous QEMU-SystemC Integration for Timed CPU/Cache/MMU/DRAM/Component Simulation: A case study in 3D Graphics SoC. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1015112-234055.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang C. Heterogeneous QEMU-SystemC Integration for Timed CPU/Cache/MMU/DRAM/Component Simulation: A case study in 3D Graphics SoC. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1015112-234055

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

29. Chang, Yi-Hao. A Performance Monitoring Tool Suite for Software and SoC on-chip Bus: Using 3D Graphics SoC as an example.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

 Nowadays SoC involves both software and hardware designs, performance bottleneck may occur either in software/hardware or even both. But present performance monitoring tools usually evaluates… (more)

Subjects/Keywords: Sampling Techniques; Bus; Software; Performance analysis; Performance monitoring

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, Y. (2012). A Performance Monitoring Tool Suite for Software and SoC on-chip Bus: Using 3D Graphics SoC as an example. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0319112-161808

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Yi-Hao. “A Performance Monitoring Tool Suite for Software and SoC on-chip Bus: Using 3D Graphics SoC as an example.” 2012. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0319112-161808.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Yi-Hao. “A Performance Monitoring Tool Suite for Software and SoC on-chip Bus: Using 3D Graphics SoC as an example.” 2012. Web. 22 Feb 2020.

Vancouver:

Chang Y. A Performance Monitoring Tool Suite for Software and SoC on-chip Bus: Using 3D Graphics SoC as an example. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0319112-161808.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang Y. A Performance Monitoring Tool Suite for Software and SoC on-chip Bus: Using 3D Graphics SoC as an example. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0319112-161808

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

30. Hsu, Chao-Yi. Efficient Timed QEMU-SystemC Parallel Emulator for Multiprocessor Target on Multicore Host Platform.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 With the rapid development of multi-processor embedded system, design and verification of hardware/software become more complex. The developers of software and hardware integration raise the… (more)

Subjects/Keywords: Multiprocessor; SystemC; Performance Analysis; SH/HW Co-verification; QEMU

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hsu, C. (2018). Efficient Timed QEMU-SystemC Parallel Emulator for Multiprocessor Target on Multicore Host Platform. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0514118-221744

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsu, Chao-Yi. “Efficient Timed QEMU-SystemC Parallel Emulator for Multiprocessor Target on Multicore Host Platform.” 2018. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0514118-221744.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsu, Chao-Yi. “Efficient Timed QEMU-SystemC Parallel Emulator for Multiprocessor Target on Multicore Host Platform.” 2018. Web. 22 Feb 2020.

Vancouver:

Hsu C. Efficient Timed QEMU-SystemC Parallel Emulator for Multiprocessor Target on Multicore Host Platform. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0514118-221744.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu C. Efficient Timed QEMU-SystemC Parallel Emulator for Multiprocessor Target on Multicore Host Platform. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0514118-221744

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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