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You searched for +publisher:"NSYSU" +contributor:("Chung-Ping Chung"). Showing records 1 – 20 of 20 total matches.

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NSYSU

1. Lai, Yu-ren. Design of the Superscalar Dual-Core Architecture using Single-Issue Out-of-Order Instruction Pipe for Embedded System.

Degree: Master, Electrical Engineering, 2009, NSYSU

 With the improvement in VLSI technology, realization of multiple processor cores on a single chip becomes easier. Therefore, more and more users execute applications on… (more)

Subjects/Keywords: Dual-Core; Superscalar; Embedded System; Out-of-Order; Single-Issue

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lai, Y. (2009). Design of the Superscalar Dual-Core Architecture using Single-Issue Out-of-Order Instruction Pipe for Embedded System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729109-173040

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lai, Yu-ren. “Design of the Superscalar Dual-Core Architecture using Single-Issue Out-of-Order Instruction Pipe for Embedded System.” 2009. Thesis, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729109-173040.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lai, Yu-ren. “Design of the Superscalar Dual-Core Architecture using Single-Issue Out-of-Order Instruction Pipe for Embedded System.” 2009. Web. 06 May 2021.

Vancouver:

Lai Y. Design of the Superscalar Dual-Core Architecture using Single-Issue Out-of-Order Instruction Pipe for Embedded System. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729109-173040.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lai Y. Design of the Superscalar Dual-Core Architecture using Single-Issue Out-of-Order Instruction Pipe for Embedded System. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729109-173040

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

2. Lin, Tzu-chun. Implementation of Action Recognition Algorithm on Multiple-Streaming Multimedia Unit.

Degree: Master, Electrical Engineering, 2010, NSYSU

 Action recognition had become prosperous in development and been broadly applied in several sectors. From homeland security, personal property, home caring, even the smart environment… (more)

Subjects/Keywords: SIMD; Action Recognition; Embedded computer vision; MMX; Streaming Processing

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APA (6th Edition):

Lin, T. (2010). Implementation of Action Recognition Algorithm on Multiple-Streaming Multimedia Unit. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803110-142110

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Tzu-chun. “Implementation of Action Recognition Algorithm on Multiple-Streaming Multimedia Unit.” 2010. Thesis, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803110-142110.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Tzu-chun. “Implementation of Action Recognition Algorithm on Multiple-Streaming Multimedia Unit.” 2010. Web. 06 May 2021.

Vancouver:

Lin T. Implementation of Action Recognition Algorithm on Multiple-Streaming Multimedia Unit. [Internet] [Thesis]. NSYSU; 2010. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803110-142110.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin T. Implementation of Action Recognition Algorithm on Multiple-Streaming Multimedia Unit. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803110-142110

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

3. Lei, Kin-fong. Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems.

Degree: Master, Electrical Engineering, 2010, NSYSU

 In the multi-core systems, the data transfer between cores becomes a major challenge. The on-chip interconnect networks should be low latency, high throughput, scalability, better… (more)

Subjects/Keywords: On-Chip Interconnect Networks; Asynchronous Ring Bus; Multi-Core Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lei, K. (2010). Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lei, Kin-fong. “Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems.” 2010. Thesis, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lei, Kin-fong. “Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems.” 2010. Web. 06 May 2021.

Vancouver:

Lei K. Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems. [Internet] [Thesis]. NSYSU; 2010. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lei K. Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

4. Wu, Ming-Shiou. Dynamic Multi-channel Multi-path Routing Protocol for Wireless Mesh Networks.

Degree: Master, Electrical Engineering, 2010, NSYSU

 With the wireless mesh network in the embedded systems related applications booming in recent years, the demand of enhancing the overall end to end network… (more)

Subjects/Keywords: Routing Protocol; Multi-path; Multi-channel; Wireless Mesh Networks

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, M. (2010). Dynamic Multi-channel Multi-path Routing Protocol for Wireless Mesh Networks. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728110-113535

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Ming-Shiou. “Dynamic Multi-channel Multi-path Routing Protocol for Wireless Mesh Networks.” 2010. Thesis, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728110-113535.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Ming-Shiou. “Dynamic Multi-channel Multi-path Routing Protocol for Wireless Mesh Networks.” 2010. Web. 06 May 2021.

Vancouver:

Wu M. Dynamic Multi-channel Multi-path Routing Protocol for Wireless Mesh Networks. [Internet] [Thesis]. NSYSU; 2010. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728110-113535.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu M. Dynamic Multi-channel Multi-path Routing Protocol for Wireless Mesh Networks. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728110-113535

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

5. Pan, Po-Hsun. The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture.

Degree: Master, Electrical Engineering, 2011, NSYSU

 In recent years, automatic human action recognition has been widely researched within the computer vision and image processing communities. To identify human behavior which achieve… (more)

Subjects/Keywords: action recognition; SIMD; CELL; parallelize

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pan, P. (2011). The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823111-143005

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pan, Po-Hsun. “The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture.” 2011. Thesis, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823111-143005.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pan, Po-Hsun. “The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture.” 2011. Web. 06 May 2021.

Vancouver:

Pan P. The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture. [Internet] [Thesis]. NSYSU; 2011. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823111-143005.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pan P. The Optimal Design for Action Recognition Algorithm on Cell Processor Architecture. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823111-143005

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

6. Lian, Guo-sen. The Event-table-driven Control Program Generator of Microprocessor-based Environment.

Degree: Master, Electrical Engineering, 2011, NSYSU

 In the field of automatic control, using a microprocessor application system to monitor and control an automatic system is quite common and its usage rate… (more)

Subjects/Keywords: PLC; MCU; Event-table-driven; Control program generator

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APA (6th Edition):

Lian, G. (2011). The Event-table-driven Control Program Generator of Microprocessor-based Environment. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727111-221240

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lian, Guo-sen. “The Event-table-driven Control Program Generator of Microprocessor-based Environment.” 2011. Thesis, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727111-221240.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lian, Guo-sen. “The Event-table-driven Control Program Generator of Microprocessor-based Environment.” 2011. Web. 06 May 2021.

Vancouver:

Lian G. The Event-table-driven Control Program Generator of Microprocessor-based Environment. [Internet] [Thesis]. NSYSU; 2011. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727111-221240.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lian G. The Event-table-driven Control Program Generator of Microprocessor-based Environment. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727111-221240

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

7. Ku, Po-Yu. The Optimal Design for Face Detection Algorithm on Cell Processor Architecture.

Degree: Master, Electrical Engineering, 2011, NSYSU

 With the advance of facial recognition technology, many related applications such as the clearance of specific facilities, air port security, video camera surveillance, and personnel… (more)

Subjects/Keywords: Multiple Buffering; Modified Census Transform (MCT); SIMD; Synergistic Processor (SPE); Heterogeneous; PowerPC Processor Element (PPE)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ku, P. (2011). The Optimal Design for Face Detection Algorithm on Cell Processor Architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-172556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ku, Po-Yu. “The Optimal Design for Face Detection Algorithm on Cell Processor Architecture.” 2011. Thesis, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-172556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ku, Po-Yu. “The Optimal Design for Face Detection Algorithm on Cell Processor Architecture.” 2011. Web. 06 May 2021.

Vancouver:

Ku P. The Optimal Design for Face Detection Algorithm on Cell Processor Architecture. [Internet] [Thesis]. NSYSU; 2011. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-172556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ku P. The Optimal Design for Face Detection Algorithm on Cell Processor Architecture. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-172556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

8. Chen, Juei-Tsung. Design and Implement the Memory Unit with Reconfigurable Computing Unit.

Degree: Master, Electrical Engineering, 2011, NSYSU

 It has been confirmed that reconfigurable computing system has potential to accelerate in large amounts of data computing. However, current trend is towards combining a… (more)

Subjects/Keywords: Software-hardware co-work; Hardware Management Unit; Reconfigurable computing system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, J. (2011). Design and Implement the Memory Unit with Reconfigurable Computing Unit. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-172812

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Juei-Tsung. “Design and Implement the Memory Unit with Reconfigurable Computing Unit.” 2011. Thesis, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-172812.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Juei-Tsung. “Design and Implement the Memory Unit with Reconfigurable Computing Unit.” 2011. Web. 06 May 2021.

Vancouver:

Chen J. Design and Implement the Memory Unit with Reconfigurable Computing Unit. [Internet] [Thesis]. NSYSU; 2011. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-172812.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen J. Design and Implement the Memory Unit with Reconfigurable Computing Unit. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-172812

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

9. Chou, Yu-Liang. Study of the Hyperscalar Multi-core Architecture.

Degree: PhD, Electrical Engineering, 2011, NSYSU

 Current trends in processor design have migrated toward chip multiprocessors (CMPs). CMPs are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism… (more)

Subjects/Keywords: SIMD; chip multiprocessors; superscalar; dynamic multi-core; reconfigurable hardware; multimedia processing; hyperscalar

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chou, Y. (2011). Study of the Hyperscalar Multi-core Architecture. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907111-220723

Chicago Manual of Style (16th Edition):

Chou, Yu-Liang. “Study of the Hyperscalar Multi-core Architecture.” 2011. Doctoral Dissertation, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907111-220723.

MLA Handbook (7th Edition):

Chou, Yu-Liang. “Study of the Hyperscalar Multi-core Architecture.” 2011. Web. 06 May 2021.

Vancouver:

Chou Y. Study of the Hyperscalar Multi-core Architecture. [Internet] [Doctoral dissertation]. NSYSU; 2011. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907111-220723.

Council of Science Editors:

Chou Y. Study of the Hyperscalar Multi-core Architecture. [Doctoral Dissertation]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907111-220723


NSYSU

10. Yang, Kai-ming. A Ring-like Arbitration Strategy Schedule for Networks-On-Chips.

Degree: PhD, Electrical Engineering, 2013, NSYSU

 Multi-core systems in single chip exploit ILP (Instruction-Level Parallelism) and TLP (Thread-Level Parallelism) to improve the system performance. Therefore, efficiency of transferring data among cores… (more)

Subjects/Keywords: Distributed on-chip network arbitration strategy; Instruction and data stream buffer; Asynchronous circuits; Network-on-chip; Priority selector

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, K. (2013). A Ring-like Arbitration Strategy Schedule for Networks-On-Chips. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618113-150752

Chicago Manual of Style (16th Edition):

Yang, Kai-ming. “A Ring-like Arbitration Strategy Schedule for Networks-On-Chips.” 2013. Doctoral Dissertation, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618113-150752.

MLA Handbook (7th Edition):

Yang, Kai-ming. “A Ring-like Arbitration Strategy Schedule for Networks-On-Chips.” 2013. Web. 06 May 2021.

Vancouver:

Yang K. A Ring-like Arbitration Strategy Schedule for Networks-On-Chips. [Internet] [Doctoral dissertation]. NSYSU; 2013. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618113-150752.

Council of Science Editors:

Yang K. A Ring-like Arbitration Strategy Schedule for Networks-On-Chips. [Doctoral Dissertation]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618113-150752


NSYSU

11. Chen, Po-kai. ESL Model of the Hyper-scalar Processor on a Chip.

Degree: Master, Electrical Engineering, 2007, NSYSU

 This paper proposed a scalable chip multiprocessor architecture, which is called Hyper-scalar combined with the concept of superscalar and multithreaded architecture; hence, this architecture can… (more)

Subjects/Keywords: Data-Driven; Multi-Core; ESL

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, P. (2007). ESL Model of the Hyper-scalar Processor on a Chip. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820107-003959

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Po-kai. “ESL Model of the Hyper-scalar Processor on a Chip.” 2007. Thesis, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820107-003959.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Po-kai. “ESL Model of the Hyper-scalar Processor on a Chip.” 2007. Web. 06 May 2021.

Vancouver:

Chen P. ESL Model of the Hyper-scalar Processor on a Chip. [Internet] [Thesis]. NSYSU; 2007. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820107-003959.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen P. ESL Model of the Hyper-scalar Processor on a Chip. [Thesis]. NSYSU; 2007. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820107-003959

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

12. He, Zong-cian. Software-Hardware Interwork Mechanism of FMRPU.

Degree: Master, Electrical Engineering, 2007, NSYSU

 It has been proofed that Reconfigurable Computing System possesses the potential to promote system efficiency. Fine-Grain Reconfigurable Computing System, which integrates the co-design of software… (more)

Subjects/Keywords: multi-context; reconfigurable; fine-grain

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

He, Z. (2007). Software-Hardware Interwork Mechanism of FMRPU. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0828107-122819

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

He, Zong-cian. “Software-Hardware Interwork Mechanism of FMRPU.” 2007. Thesis, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0828107-122819.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

He, Zong-cian. “Software-Hardware Interwork Mechanism of FMRPU.” 2007. Web. 06 May 2021.

Vancouver:

He Z. Software-Hardware Interwork Mechanism of FMRPU. [Internet] [Thesis]. NSYSU; 2007. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0828107-122819.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

He Z. Software-Hardware Interwork Mechanism of FMRPU. [Thesis]. NSYSU; 2007. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0828107-122819

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

13. Hong, Shou-xi. Design of the Multimedia Processor Based on MMX Instruction Set.

Degree: Master, Electrical Engineering, 2007, NSYSU

 Today the application of the embedded system is more complex. Especially the multimedia function is most popular. But it is still difficult to work smooth… (more)

Subjects/Keywords: Multimedia instruction; MMX

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hong, S. (2007). Design of the Multimedia Processor Based on MMX Instruction Set. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726107-144416

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hong, Shou-xi. “Design of the Multimedia Processor Based on MMX Instruction Set.” 2007. Thesis, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726107-144416.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hong, Shou-xi. “Design of the Multimedia Processor Based on MMX Instruction Set.” 2007. Web. 06 May 2021.

Vancouver:

Hong S. Design of the Multimedia Processor Based on MMX Instruction Set. [Internet] [Thesis]. NSYSU; 2007. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726107-144416.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hong S. Design of the Multimedia Processor Based on MMX Instruction Set. [Thesis]. NSYSU; 2007. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726107-144416

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

14. Lee, Chun-Hsien. Implementation of Vectorization-Based VLIW DSP with Compact Instructions.

Degree: Master, Electrical Engineering, 2005, NSYSU

 The main goal of this thesis is to design and implement the high performance processor core for completing those digital signal processing algorithms applied at… (more)

Subjects/Keywords: FFT; Compressed Instruction; VLIW; DSP; Vector Instruction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lee, C. (2005). Implementation of Vectorization-Based VLIW DSP with Compact Instructions. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823105-181117

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lee, Chun-Hsien. “Implementation of Vectorization-Based VLIW DSP with Compact Instructions.” 2005. Thesis, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823105-181117.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lee, Chun-Hsien. “Implementation of Vectorization-Based VLIW DSP with Compact Instructions.” 2005. Web. 06 May 2021.

Vancouver:

Lee C. Implementation of Vectorization-Based VLIW DSP with Compact Instructions. [Internet] [Thesis]. NSYSU; 2005. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823105-181117.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee C. Implementation of Vectorization-Based VLIW DSP with Compact Instructions. [Thesis]. NSYSU; 2005. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823105-181117

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

15. Chen, Jau-You. An automatic optimization mechanism of circuit block partition for Fine-grain Multi-context Reconfigurable Process Unit.

Degree: Master, Electrical Engineering, 2006, NSYSU

 Due to the rapid development of todayâs multimedia communication systems, the complexity and scale of the systems increase day after day. For real-time computing of… (more)

Subjects/Keywords: placement; routing; FMRPU; block partition

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, J. (2006). An automatic optimization mechanism of circuit block partition for Fine-grain Multi-context Reconfigurable Process Unit. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726106-125353

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Jau-You. “An automatic optimization mechanism of circuit block partition for Fine-grain Multi-context Reconfigurable Process Unit.” 2006. Thesis, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726106-125353.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Jau-You. “An automatic optimization mechanism of circuit block partition for Fine-grain Multi-context Reconfigurable Process Unit.” 2006. Web. 06 May 2021.

Vancouver:

Chen J. An automatic optimization mechanism of circuit block partition for Fine-grain Multi-context Reconfigurable Process Unit. [Internet] [Thesis]. NSYSU; 2006. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726106-125353.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen J. An automatic optimization mechanism of circuit block partition for Fine-grain Multi-context Reconfigurable Process Unit. [Thesis]. NSYSU; 2006. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726106-125353

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

16. Yang, Kai-Ming. Improving the Fetching Performance of Instruction Stream Buffer for VLIW Architectures with Compressed Instructions.

Degree: Master, Electrical Engineering, 2006, NSYSU

 Because of the restriction on structure hazard and instruction data dependence, the quantity of NOP instructions fills up a program for VLIW Architectures. This problem… (more)

Subjects/Keywords: instruction stream buffer; zero overhead looping

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, K. (2006). Improving the Fetching Performance of Instruction Stream Buffer for VLIW Architectures with Compressed Instructions. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825106-113139

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Kai-Ming. “Improving the Fetching Performance of Instruction Stream Buffer for VLIW Architectures with Compressed Instructions.” 2006. Thesis, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825106-113139.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Kai-Ming. “Improving the Fetching Performance of Instruction Stream Buffer for VLIW Architectures with Compressed Instructions.” 2006. Web. 06 May 2021.

Vancouver:

Yang K. Improving the Fetching Performance of Instruction Stream Buffer for VLIW Architectures with Compressed Instructions. [Internet] [Thesis]. NSYSU; 2006. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825106-113139.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang K. Improving the Fetching Performance of Instruction Stream Buffer for VLIW Architectures with Compressed Instructions. [Thesis]. NSYSU; 2006. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825106-113139

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

17. Lin, Ren-Bang. FMRPU: Design of Fine-grain Multi-context Reconfigurable Processing Unit.

Degree: Master, Electrical Engineering, 2004, NSYSU

 At present the scale of multimedia and communication systems has become more and more complicated due to the fast development of them. In order to… (more)

Subjects/Keywords: fine-grain; multi-context; reconfigurable

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, R. (2004). FMRPU: Design of Fine-grain Multi-context Reconfigurable Processing Unit. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0713104-180405

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Ren-Bang. “FMRPU: Design of Fine-grain Multi-context Reconfigurable Processing Unit.” 2004. Thesis, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0713104-180405.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Ren-Bang. “FMRPU: Design of Fine-grain Multi-context Reconfigurable Processing Unit.” 2004. Web. 06 May 2021.

Vancouver:

Lin R. FMRPU: Design of Fine-grain Multi-context Reconfigurable Processing Unit. [Internet] [Thesis]. NSYSU; 2004. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0713104-180405.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin R. FMRPU: Design of Fine-grain Multi-context Reconfigurable Processing Unit. [Thesis]. NSYSU; 2004. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0713104-180405

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

18. Liang, Ming-Chang. Design and Implementation of a Configurable and Cost Effective Web Benchmark.

Degree: Master, Computer Science and Engineering, 2001, NSYSU

 As WWW service grow up rapidly and becomes the most popular information system on the internet, web site owner invest heavily to improve the performance… (more)

Subjects/Keywords: benchmark; cookie; cost effective; session

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liang, M. (2001). Design and Implementation of a Configurable and Cost Effective Web Benchmark. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0829101-205016

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liang, Ming-Chang. “Design and Implementation of a Configurable and Cost Effective Web Benchmark.” 2001. Thesis, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0829101-205016.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liang, Ming-Chang. “Design and Implementation of a Configurable and Cost Effective Web Benchmark.” 2001. Web. 06 May 2021.

Vancouver:

Liang M. Design and Implementation of a Configurable and Cost Effective Web Benchmark. [Internet] [Thesis]. NSYSU; 2001. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0829101-205016.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liang M. Design and Implementation of a Configurable and Cost Effective Web Benchmark. [Thesis]. NSYSU; 2001. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0829101-205016

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

19. Su, Yih-ching. Fine Granularity Video Compression Technique and Its Application to Robust Video Transmission over Wireless Internet.

Degree: PhD, Computer Science and Engineering, 2003, NSYSU

 This dissertation deals with (a) fine granularity video compression technique and (b) its application to robust video transmission over wireless Internet. First, two wavelet-domain motion… (more)

Subjects/Keywords: motion estimation; Gilbert Channel; MPEG-4; FPGA; Fine Granularity Scalability; Forward Error Correction; embeded coder; wavelet

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Su, Y. (2003). Fine Granularity Video Compression Technique and Its Application to Robust Video Transmission over Wireless Internet. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1222103-160305

Chicago Manual of Style (16th Edition):

Su, Yih-ching. “Fine Granularity Video Compression Technique and Its Application to Robust Video Transmission over Wireless Internet.” 2003. Doctoral Dissertation, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1222103-160305.

MLA Handbook (7th Edition):

Su, Yih-ching. “Fine Granularity Video Compression Technique and Its Application to Robust Video Transmission over Wireless Internet.” 2003. Web. 06 May 2021.

Vancouver:

Su Y. Fine Granularity Video Compression Technique and Its Application to Robust Video Transmission over Wireless Internet. [Internet] [Doctoral dissertation]. NSYSU; 2003. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1222103-160305.

Council of Science Editors:

Su Y. Fine Granularity Video Compression Technique and Its Application to Robust Video Transmission over Wireless Internet. [Doctoral Dissertation]. NSYSU; 2003. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1222103-160305


NSYSU

20. Liu, Feng-jung. Design and Analysis of a Highly Efficient File Server Group.

Degree: PhD, Computer Science and Engineering, 2005, NSYSU

 The IT community has increasingly come to view storage as a resource that should be shared among computer systems and managed independently of the computer… (more)

Subjects/Keywords: Data Consistency; Availability; Load-sharing; File Server

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, F. (2005). Design and Analysis of a Highly Efficient File Server Group. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0129105-124412

Chicago Manual of Style (16th Edition):

Liu, Feng-jung. “Design and Analysis of a Highly Efficient File Server Group.” 2005. Doctoral Dissertation, NSYSU. Accessed May 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0129105-124412.

MLA Handbook (7th Edition):

Liu, Feng-jung. “Design and Analysis of a Highly Efficient File Server Group.” 2005. Web. 06 May 2021.

Vancouver:

Liu F. Design and Analysis of a Highly Efficient File Server Group. [Internet] [Doctoral dissertation]. NSYSU; 2005. [cited 2021 May 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0129105-124412.

Council of Science Editors:

Liu F. Design and Analysis of a Highly Efficient File Server Group. [Doctoral Dissertation]. NSYSU; 2005. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0129105-124412

.