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You searched for +publisher:"NSYSU" +contributor:("Chung-Ho Chen"). Showing records 1 – 30 of 42 total matches.

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NSYSU

1. Lin, Jia-sian. Study of Software Implementation of a Multimedia Conference System.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 In this thesis, a multimedia conference system is proposed to support the high quality multimedia processing. This system adopts the client-server architecture and consists of… (more)

Subjects/Keywords: Simultaneous interpretation; Audio mixing; Mixer; Video streaming; Multimedia conference system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, J. (2016). Study of Software Implementation of a Multimedia Conference System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807116-170619

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Jia-sian. “Study of Software Implementation of a Multimedia Conference System.” 2016. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807116-170619.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Jia-sian. “Study of Software Implementation of a Multimedia Conference System.” 2016. Web. 22 Apr 2021.

Vancouver:

Lin J. Study of Software Implementation of a Multimedia Conference System. [Internet] [Thesis]. NSYSU; 2016. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807116-170619.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin J. Study of Software Implementation of a Multimedia Conference System. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807116-170619

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

2. Weng, Chia-Yang. Design Optimization of Hardware Function Evaluation Units with Truncated Multipliers and Squarers.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 Function evaluation is an important operation in the design of special function unit in graphics processing unit (GPU) and other applications in stereo vision and… (more)

Subjects/Keywords: function evaluation; polynomial approximation; uniform segmentation; digital arithmetic; truncated multiplier; truncated squarer

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APA (6th Edition):

Weng, C. (2017). Design Optimization of Hardware Function Evaluation Units with Truncated Multipliers and Squarers. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629117-231250

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Weng, Chia-Yang. “Design Optimization of Hardware Function Evaluation Units with Truncated Multipliers and Squarers.” 2017. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629117-231250.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Weng, Chia-Yang. “Design Optimization of Hardware Function Evaluation Units with Truncated Multipliers and Squarers.” 2017. Web. 22 Apr 2021.

Vancouver:

Weng C. Design Optimization of Hardware Function Evaluation Units with Truncated Multipliers and Squarers. [Internet] [Thesis]. NSYSU; 2017. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629117-231250.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Weng C. Design Optimization of Hardware Function Evaluation Units with Truncated Multipliers and Squarers. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629117-231250

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

3. Hsiao, Bo-chien. FPGA Implementations of Real Time 3D Stereo Matching Based on Dynamic Programming.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 Stereo vision is widely used in many computer vision applications including games, autonomous driving, object recognition, etc. Depth is the key information in stereo vision.… (more)

Subjects/Keywords: image rectification; dynamic programming; depth map; stereo matching; FPGA; stereo vision

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hsiao, B. (2017). FPGA Implementations of Real Time 3D Stereo Matching Based on Dynamic Programming. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0722117-115932

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsiao, Bo-chien. “FPGA Implementations of Real Time 3D Stereo Matching Based on Dynamic Programming.” 2017. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0722117-115932.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsiao, Bo-chien. “FPGA Implementations of Real Time 3D Stereo Matching Based on Dynamic Programming.” 2017. Web. 22 Apr 2021.

Vancouver:

Hsiao B. FPGA Implementations of Real Time 3D Stereo Matching Based on Dynamic Programming. [Internet] [Thesis]. NSYSU; 2017. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0722117-115932.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsiao B. FPGA Implementations of Real Time 3D Stereo Matching Based on Dynamic Programming. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0722117-115932

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

4. Liang, Hsiang-Hao. Design of Low-Power and Dynamically Reconfigurable Multi-Precision Special Function Units.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 Computation of special functions is widely used in many applications such as stereo vision, image processing, and communication. Piecewise polynomial approximation (PPA) is usually adopted… (more)

Subjects/Keywords: polynomial approximation; multi-precision; special function unit; digital arithmetic; function evaluation

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APA (6th Edition):

Liang, H. (2017). Design of Low-Power and Dynamically Reconfigurable Multi-Precision Special Function Units. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-224433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liang, Hsiang-Hao. “Design of Low-Power and Dynamically Reconfigurable Multi-Precision Special Function Units.” 2017. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-224433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liang, Hsiang-Hao. “Design of Low-Power and Dynamically Reconfigurable Multi-Precision Special Function Units.” 2017. Web. 22 Apr 2021.

Vancouver:

Liang H. Design of Low-Power and Dynamically Reconfigurable Multi-Precision Special Function Units. [Internet] [Thesis]. NSYSU; 2017. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-224433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liang H. Design of Low-Power and Dynamically Reconfigurable Multi-Precision Special Function Units. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728117-224433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

5. Yeah, Yu-Ren. Traversal and Intersection Acceleration of Ray-Tracing based on Coherence of Neighboring Rays.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 This thesis presents an efficient prediction-based ray-tracing scheme in order to accelerate rendering of high-fidelity three-dimensional (3D) graphics scenes. Since the neighboring rays normally exhibit… (more)

Subjects/Keywords: 3D graphics; Ray-tracing; BVH; tree traversal; ray intersection

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yeah, Y. (2018). Traversal and Intersection Acceleration of Ray-Tracing based on Coherence of Neighboring Rays. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803118-224153

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yeah, Yu-Ren. “Traversal and Intersection Acceleration of Ray-Tracing based on Coherence of Neighboring Rays.” 2018. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803118-224153.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yeah, Yu-Ren. “Traversal and Intersection Acceleration of Ray-Tracing based on Coherence of Neighboring Rays.” 2018. Web. 22 Apr 2021.

Vancouver:

Yeah Y. Traversal and Intersection Acceleration of Ray-Tracing based on Coherence of Neighboring Rays. [Internet] [Thesis]. NSYSU; 2018. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803118-224153.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yeah Y. Traversal and Intersection Acceleration of Ray-Tracing based on Coherence of Neighboring Rays. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803118-224153

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

6. Chou, Hung-I. System level power estimation for power manageable System-on-chip.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

 The modern handheld devices have become smaller and more complex nowadays. However, the requirements for its performance and functions have also become higher, which means… (more)

Subjects/Keywords: power management; low-power; framework; power estimation; SystemC; system level

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chou, H. (2009). System level power estimation for power manageable System-on-chip. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805109-102151

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chou, Hung-I. “System level power estimation for power manageable System-on-chip.” 2009. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805109-102151.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chou, Hung-I. “System level power estimation for power manageable System-on-chip.” 2009. Web. 22 Apr 2021.

Vancouver:

Chou H. System level power estimation for power manageable System-on-chip. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805109-102151.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chou H. System level power estimation for power manageable System-on-chip. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805109-102151

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

7. Lin, Keng-Hsien. Design of an Efficient Clipping Engine for OpenGL-ES 2.0 Vertex Shaders in 3D Graphics Systems.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

 In computer graphics technique, the 3D graphic pipeline flow has two processing modules: Geometry module and Rendering module. The geometry module supports vertex coordinate transformation,… (more)

Subjects/Keywords: Clipping algorithm; 3D graphics; Vertex Shader; OpenGL-ES

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, K. (2009). Design of an Efficient Clipping Engine for OpenGL-ES 2.0 Vertex Shaders in 3D Graphics Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-024820

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Keng-Hsien. “Design of an Efficient Clipping Engine for OpenGL-ES 2.0 Vertex Shaders in 3D Graphics Systems.” 2009. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-024820.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Keng-Hsien. “Design of an Efficient Clipping Engine for OpenGL-ES 2.0 Vertex Shaders in 3D Graphics Systems.” 2009. Web. 22 Apr 2021.

Vancouver:

Lin K. Design of an Efficient Clipping Engine for OpenGL-ES 2.0 Vertex Shaders in 3D Graphics Systems. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-024820.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin K. Design of an Efficient Clipping Engine for OpenGL-ES 2.0 Vertex Shaders in 3D Graphics Systems. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-024820

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

8. Chen, Kun-Chih. Design and Analysis of Table-based Arithmetic Units with Memory Reduction.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

 In many digital signal processing applications, we often need some special function units which can compute complicated arithmetic functions such as reciprocal and logarithm. Conventionally,… (more)

Subjects/Keywords: Newton-Raphson; Computer arithmetic; polynomial approximation; Non-uniform segmentation; Function approximation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, K. (2009). Design and Analysis of Table-based Arithmetic Units with Memory Reduction. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-041048

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Kun-Chih. “Design and Analysis of Table-based Arithmetic Units with Memory Reduction.” 2009. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-041048.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Kun-Chih. “Design and Analysis of Table-based Arithmetic Units with Memory Reduction.” 2009. Web. 22 Apr 2021.

Vancouver:

Chen K. Design and Analysis of Table-based Arithmetic Units with Memory Reduction. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-041048.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen K. Design and Analysis of Table-based Arithmetic Units with Memory Reduction. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-041048

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

9. Huang, Kuan-min. Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

 3D graphics pipeline can be divided into two subsystems: geometry subsystem and rendering subsystem. Hardware implementation of the transformation and lighting in the geometric subsystem… (more)

Subjects/Keywords: Vertex Shader; SIMD; Programmable

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, K. (2009). Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Kuan-min. “Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader.” 2009. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Kuan-min. “Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader.” 2009. Web. 22 Apr 2021.

Vancouver:

Huang K. Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang K. Design, Implementation, And Verification Of A Programmable Floating- And Fixed-Point Vertex Shader. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043304

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

10. Cheng, Yen-Chun. Table-Based Design of Arithmetic Function Units for Angle Rotation and Rectangular-to-Polar-Coordinate Conversion.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

 In this thesis, an efficiency method for reducing the rotation ROM size in table-based architecture is proposed. The original rotation can be divided into two… (more)

Subjects/Keywords: interpolation; CORDIC; Newton-Raphson; piecewise; Taylor-series expansion

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cheng, Y. (2009). Table-Based Design of Arithmetic Function Units for Angle Rotation and Rectangular-to-Polar-Coordinate Conversion. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043220

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cheng, Yen-Chun. “Table-Based Design of Arithmetic Function Units for Angle Rotation and Rectangular-to-Polar-Coordinate Conversion.” 2009. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043220.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cheng, Yen-Chun. “Table-Based Design of Arithmetic Function Units for Angle Rotation and Rectangular-to-Polar-Coordinate Conversion.” 2009. Web. 22 Apr 2021.

Vancouver:

Cheng Y. Table-Based Design of Arithmetic Function Units for Angle Rotation and Rectangular-to-Polar-Coordinate Conversion. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043220.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cheng Y. Table-Based Design of Arithmetic Function Units for Angle Rotation and Rectangular-to-Polar-Coordinate Conversion. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043220

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

11. Huang, Ching-Hua. Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 In recent years, the popularity of handheld smart devices.In order to the demand of consumer and rapid progress of the technological process; Although the design… (more)

Subjects/Keywords: Chip Tape-out; Logic Synthesis; Syetem-on-Chip; Three-dimensional Graphics; Layout

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, C. (2014). Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-111344

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Ching-Hua. “Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC.” 2014. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-111344.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Ching-Hua. “Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC.” 2014. Web. 22 Apr 2021.

Vancouver:

Huang C. Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC. [Internet] [Thesis]. NSYSU; 2014. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-111344.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang C. Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-111344

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

12. Wu , Ting-Hsuan. Socket-based Software and Hardware performance co-monitoring in AXI interconnect SoC.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Embedded systems are contained in many kinds of hardware resources and software processes today. Since the SoC industry has shift its development goal from processor… (more)

Subjects/Keywords: Socket-based transaction state monitor; Performance monitoring; Performance analysis; Transaction; Software

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu , T. (2014). Socket-based Software and Hardware performance co-monitoring in AXI interconnect SoC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-150954

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu , Ting-Hsuan. “Socket-based Software and Hardware performance co-monitoring in AXI interconnect SoC.” 2014. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-150954.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu , Ting-Hsuan. “Socket-based Software and Hardware performance co-monitoring in AXI interconnect SoC.” 2014. Web. 22 Apr 2021.

Vancouver:

Wu T. Socket-based Software and Hardware performance co-monitoring in AXI interconnect SoC. [Internet] [Thesis]. NSYSU; 2014. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-150954.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu T. Socket-based Software and Hardware performance co-monitoring in AXI interconnect SoC. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-150954

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

13. Ho, Chia-lun. Computer Vision Software and Hardware Design Based on OpenVX.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 OpenVX, an open, royalty-free, cross-platform standard, can be used to speed up computer vision applications in embedded systems. It can achieve performance and power-optimized processing… (more)

Subjects/Keywords: FPGA; Zedboard; computer vision; OpenVX; embedded system; face motion simulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ho, C. (2016). Computer Vision Software and Hardware Design Based on OpenVX. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0718116-085104

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ho, Chia-lun. “Computer Vision Software and Hardware Design Based on OpenVX.” 2016. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0718116-085104.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ho, Chia-lun. “Computer Vision Software and Hardware Design Based on OpenVX.” 2016. Web. 22 Apr 2021.

Vancouver:

Ho C. Computer Vision Software and Hardware Design Based on OpenVX. [Internet] [Thesis]. NSYSU; 2016. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0718116-085104.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ho C. Computer Vision Software and Hardware Design Based on OpenVX. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0718116-085104

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

14. Huang, Kuei-Chun. Design and Application of Special Function Unit in Dual-Precision.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 Most previous researches on function evaluation focused on optimization of table content generation, area, and delay for a specific function and accuracy. Therefore, the final… (more)

Subjects/Keywords: function evaluation; polynomial approximation; dual-precision; table lookup methods; uniform segmentation; special function unit; multipartite table methods; hierarchical multipartite table methods

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APA (6th Edition):

Huang, K. (2016). Design and Application of Special Function Unit in Dual-Precision. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730116-171534

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Kuei-Chun. “Design and Application of Special Function Unit in Dual-Precision.” 2016. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730116-171534.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Kuei-Chun. “Design and Application of Special Function Unit in Dual-Precision.” 2016. Web. 22 Apr 2021.

Vancouver:

Huang K. Design and Application of Special Function Unit in Dual-Precision. [Internet] [Thesis]. NSYSU; 2016. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730116-171534.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang K. Design and Application of Special Function Unit in Dual-Precision. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730116-171534

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

15. Li, Jyun-yan. Verification of Instruction Set Compatible Processors with a Dual Core Environment.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 For improving the performance of microprocessor becomes more and more complex with the microprocessor techniques improvement. This improvement leads to verify microprocessor behaviors that becoming… (more)

Subjects/Keywords: Dual Core Verification; Microprocessor; Synchronization; Chip-level Redundant Threading; Dual Modular Redundancy

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, J. (2014). Verification of Instruction Set Compatible Processors with a Dual Core Environment. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-160709

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Jyun-yan. “Verification of Instruction Set Compatible Processors with a Dual Core Environment.” 2014. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-160709.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Jyun-yan. “Verification of Instruction Set Compatible Processors with a Dual Core Environment.” 2014. Web. 22 Apr 2021.

Vancouver:

Li J. Verification of Instruction Set Compatible Processors with a Dual Core Environment. [Internet] [Thesis]. NSYSU; 2014. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-160709.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li J. Verification of Instruction Set Compatible Processors with a Dual Core Environment. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-160709

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

16. Wu, Chung-yueh. Implementation of Independent Small Cell Communication System.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 Because of the great advancement of communication technologies, people have more choices to contact with each other. The common communication modes nowadays include telecommunications service,… (more)

Subjects/Keywords: Communication app; VoIP; SIP; MQTT; Small cell

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APA (6th Edition):

Wu, C. (2016). Implementation of Independent Small Cell Communication System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801116-114611

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Chung-yueh. “Implementation of Independent Small Cell Communication System.” 2016. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801116-114611.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Chung-yueh. “Implementation of Independent Small Cell Communication System.” 2016. Web. 22 Apr 2021.

Vancouver:

Wu C. Implementation of Independent Small Cell Communication System. [Internet] [Thesis]. NSYSU; 2016. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801116-114611.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu C. Implementation of Independent Small Cell Communication System. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801116-114611

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

17. Lin, Jun-Hong. A Dynamic CRE and ABS Scheme to Enhance Network Capacity in LTE-Advanced Heterogeneous Networks.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 With the popularity of wireless multimedia service, the wireless network base station may be overloaded in high population density region. There is an economical way… (more)

Subjects/Keywords: CRE; ABS; eICIC; Interference; HetNet

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APA (6th Edition):

Lin, J. (2017). A Dynamic CRE and ABS Scheme to Enhance Network Capacity in LTE-Advanced Heterogeneous Networks. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0005117-101303

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Jun-Hong. “A Dynamic CRE and ABS Scheme to Enhance Network Capacity in LTE-Advanced Heterogeneous Networks.” 2017. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0005117-101303.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Jun-Hong. “A Dynamic CRE and ABS Scheme to Enhance Network Capacity in LTE-Advanced Heterogeneous Networks.” 2017. Web. 22 Apr 2021.

Vancouver:

Lin J. A Dynamic CRE and ABS Scheme to Enhance Network Capacity in LTE-Advanced Heterogeneous Networks. [Internet] [Thesis]. NSYSU; 2017. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0005117-101303.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin J. A Dynamic CRE and ABS Scheme to Enhance Network Capacity in LTE-Advanced Heterogeneous Networks. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0005117-101303

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

18. Chang, Yi-Hao. A Performance Monitoring Tool Suite for Software and SoC on-chip Bus: Using 3D Graphics SoC as an example.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

 Nowadays SoC involves both software and hardware designs, performance bottleneck may occur either in software/hardware or even both. But present performance monitoring tools usually evaluates… (more)

Subjects/Keywords: Sampling Techniques; Bus; Software; Performance analysis; Performance monitoring

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, Y. (2012). A Performance Monitoring Tool Suite for Software and SoC on-chip Bus: Using 3D Graphics SoC as an example. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0319112-161808

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Yi-Hao. “A Performance Monitoring Tool Suite for Software and SoC on-chip Bus: Using 3D Graphics SoC as an example.” 2012. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0319112-161808.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Yi-Hao. “A Performance Monitoring Tool Suite for Software and SoC on-chip Bus: Using 3D Graphics SoC as an example.” 2012. Web. 22 Apr 2021.

Vancouver:

Chang Y. A Performance Monitoring Tool Suite for Software and SoC on-chip Bus: Using 3D Graphics SoC as an example. [Internet] [Thesis]. NSYSU; 2012. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0319112-161808.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang Y. A Performance Monitoring Tool Suite for Software and SoC on-chip Bus: Using 3D Graphics SoC as an example. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0319112-161808

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

19. Wang, Ting-Wei. Interactive 3D Stereoscopic Fish Tank.

Degree: Master, Computer Science and Engineering, 2011, NSYSU

 This thesis presents a 3D stereoscopic interactive fish tank system that combines the 3D stereoscopy and âcontroller-freeâ components. Based on the characteristics of human vision,… (more)

Subjects/Keywords: Controller-free; Disparity map; Stereoscopy

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APA (6th Edition):

Wang, T. (2011). Interactive 3D Stereoscopic Fish Tank. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808111-104800

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Ting-Wei. “Interactive 3D Stereoscopic Fish Tank.” 2011. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808111-104800.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Ting-Wei. “Interactive 3D Stereoscopic Fish Tank.” 2011. Web. 22 Apr 2021.

Vancouver:

Wang T. Interactive 3D Stereoscopic Fish Tank. [Internet] [Thesis]. NSYSU; 2011. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808111-104800.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang T. Interactive 3D Stereoscopic Fish Tank. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808111-104800

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

20. Cheng, Ching-Wen. Low-Cost Design of a 3D Stereo Synthesizer Using Depth-Image-Based Rendering.

Degree: Master, Computer Science and Engineering, 2011, NSYSU

 In this thesis, we proposed a low cost stereoscopic image generation hardware using Depth Image Based Rendering (DIBR) method. Due to the unfavorable artifacts produced… (more)

Subjects/Keywords: depth information; 3D stereoscopic image generation; Depth Image Based Rendering (DIBR)

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APA (6th Edition):

Cheng, C. (2011). Low-Cost Design of a 3D Stereo Synthesizer Using Depth-Image-Based Rendering. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901111-161035

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cheng, Ching-Wen. “Low-Cost Design of a 3D Stereo Synthesizer Using Depth-Image-Based Rendering.” 2011. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901111-161035.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cheng, Ching-Wen. “Low-Cost Design of a 3D Stereo Synthesizer Using Depth-Image-Based Rendering.” 2011. Web. 22 Apr 2021.

Vancouver:

Cheng C. Low-Cost Design of a 3D Stereo Synthesizer Using Depth-Image-Based Rendering. [Internet] [Thesis]. NSYSU; 2011. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901111-161035.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cheng C. Low-Cost Design of a 3D Stereo Synthesizer Using Depth-Image-Based Rendering. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901111-161035

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

21. Yeh, Chia-Yu. Design of a Multi-Core Multi-thread Floating-Point Processor and Its Application in Computer Graphics.

Degree: Master, Computer Science and Engineering, 2011, NSYSU

 Graphics processing unit (GPU) designs usually adopts various computer architecture techniques to boost the computation speed, including single-instruction multiple data (SIMD), very-long-instruction word (VLIW), multi-threading,… (more)

Subjects/Keywords: multi-threading; graphics processing unit (GPU); vertex shader; SIMD; matrix-vector multiplication; OpenGL ES 2.0

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APA (6th Edition):

Yeh, C. (2011). Design of a Multi-Core Multi-thread Floating-Point Processor and Its Application in Computer Graphics. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0906111-035109

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yeh, Chia-Yu. “Design of a Multi-Core Multi-thread Floating-Point Processor and Its Application in Computer Graphics.” 2011. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0906111-035109.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yeh, Chia-Yu. “Design of a Multi-Core Multi-thread Floating-Point Processor and Its Application in Computer Graphics.” 2011. Web. 22 Apr 2021.

Vancouver:

Yeh C. Design of a Multi-Core Multi-thread Floating-Point Processor and Its Application in Computer Graphics. [Internet] [Thesis]. NSYSU; 2011. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0906111-035109.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yeh C. Design of a Multi-Core Multi-thread Floating-Point Processor and Its Application in Computer Graphics. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0906111-035109

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

22. Chang, Wei-Shun. A Video Surveillance Alarm System based on Human Behavior Analysis.

Degree: Master, Computer Science and Engineering, 2011, NSYSU

 Human behavior analysis is an important challenge in many domains, such as surveillance systems, video content retrieval, human interactive systems, medical diagnosis, etc. With the… (more)

Subjects/Keywords: image processing; intelligent surveillance system; computer vision; behavior analysis; depth camera

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APA (6th Edition):

Chang, W. (2011). A Video Surveillance Alarm System based on Human Behavior Analysis. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907111-162558

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Wei-Shun. “A Video Surveillance Alarm System based on Human Behavior Analysis.” 2011. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907111-162558.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Wei-Shun. “A Video Surveillance Alarm System based on Human Behavior Analysis.” 2011. Web. 22 Apr 2021.

Vancouver:

Chang W. A Video Surveillance Alarm System based on Human Behavior Analysis. [Internet] [Thesis]. NSYSU; 2011. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907111-162558.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang W. A Video Surveillance Alarm System based on Human Behavior Analysis. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907111-162558

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

23. Ke, Yi-Ju. Critical Signature Assertion and On-the-Fly Recovery for Control Flow Errors in Processors.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 For the real-time systems, the error detection and recovery of the transient fault have become an important issue to improve the reliability. In previous works,… (more)

Subjects/Keywords: Microprocessor; Fault-Tolerant; Signature; Checkpoint and Recovery; Data Error; Control Flow Error

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APA (6th Edition):

Ke, Y. (2018). Critical Signature Assertion and On-the-Fly Recovery for Control Flow Errors in Processors. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0402118-084552

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ke, Yi-Ju. “Critical Signature Assertion and On-the-Fly Recovery for Control Flow Errors in Processors.” 2018. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0402118-084552.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ke, Yi-Ju. “Critical Signature Assertion and On-the-Fly Recovery for Control Flow Errors in Processors.” 2018. Web. 22 Apr 2021.

Vancouver:

Ke Y. Critical Signature Assertion and On-the-Fly Recovery for Control Flow Errors in Processors. [Internet] [Thesis]. NSYSU; 2018. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0402118-084552.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ke Y. Critical Signature Assertion and On-the-Fly Recovery for Control Flow Errors in Processors. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0402118-084552

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

24. Wu, Pei-Hsuan. Architecture Design and Implementation of Deep Neural Network Hardware Accelerators.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 Deep Neural Networks (DNN) widely used in computer vision applications have superior performance in image classification and object detection. However, the huge amount of data… (more)

Subjects/Keywords: CNN hardware accelerator; deep neural network (DNN); convolutional neural network (CNN); machine learning

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, P. (2018). Architecture Design and Implementation of Deep Neural Network Hardware Accelerators. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-154714

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Pei-Hsuan. “Architecture Design and Implementation of Deep Neural Network Hardware Accelerators.” 2018. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-154714.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Pei-Hsuan. “Architecture Design and Implementation of Deep Neural Network Hardware Accelerators.” 2018. Web. 22 Apr 2021.

Vancouver:

Wu P. Architecture Design and Implementation of Deep Neural Network Hardware Accelerators. [Internet] [Thesis]. NSYSU; 2018. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-154714.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu P. Architecture Design and Implementation of Deep Neural Network Hardware Accelerators. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-154714

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

25. Hsu, Chao-Yi. Efficient Timed QEMU-SystemC Parallel Emulator for Multiprocessor Target on Multicore Host Platform.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 With the rapid development of multi-processor embedded system, design and verification of hardware/software become more complex. The developers of software and hardware integration raise the… (more)

Subjects/Keywords: Multiprocessor; SystemC; Performance Analysis; SH/HW Co-verification; QEMU

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hsu, C. (2018). Efficient Timed QEMU-SystemC Parallel Emulator for Multiprocessor Target on Multicore Host Platform. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0514118-221744

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsu, Chao-Yi. “Efficient Timed QEMU-SystemC Parallel Emulator for Multiprocessor Target on Multicore Host Platform.” 2018. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0514118-221744.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsu, Chao-Yi. “Efficient Timed QEMU-SystemC Parallel Emulator for Multiprocessor Target on Multicore Host Platform.” 2018. Web. 22 Apr 2021.

Vancouver:

Hsu C. Efficient Timed QEMU-SystemC Parallel Emulator for Multiprocessor Target on Multicore Host Platform. [Internet] [Thesis]. NSYSU; 2018. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0514118-221744.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu C. Efficient Timed QEMU-SystemC Parallel Emulator for Multiprocessor Target on Multicore Host Platform. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0514118-221744

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

26. Yang, Kai-ming. A Ring-like Arbitration Strategy Schedule for Networks-On-Chips.

Degree: PhD, Electrical Engineering, 2013, NSYSU

 Multi-core systems in single chip exploit ILP (Instruction-Level Parallelism) and TLP (Thread-Level Parallelism) to improve the system performance. Therefore, efficiency of transferring data among cores… (more)

Subjects/Keywords: Distributed on-chip network arbitration strategy; Instruction and data stream buffer; Asynchronous circuits; Network-on-chip; Priority selector

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, K. (2013). A Ring-like Arbitration Strategy Schedule for Networks-On-Chips. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618113-150752

Chicago Manual of Style (16th Edition):

Yang, Kai-ming. “A Ring-like Arbitration Strategy Schedule for Networks-On-Chips.” 2013. Doctoral Dissertation, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618113-150752.

MLA Handbook (7th Edition):

Yang, Kai-ming. “A Ring-like Arbitration Strategy Schedule for Networks-On-Chips.” 2013. Web. 22 Apr 2021.

Vancouver:

Yang K. A Ring-like Arbitration Strategy Schedule for Networks-On-Chips. [Internet] [Doctoral dissertation]. NSYSU; 2013. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618113-150752.

Council of Science Editors:

Yang K. A Ring-like Arbitration Strategy Schedule for Networks-On-Chips. [Doctoral Dissertation]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618113-150752


NSYSU

27. Tung, Ting-Chi. Design and Implementation of Vector Graphics Accelerator Equipped with a Tessellation Processor.

Degree: PhD, Computer Science and Engineering, 2014, NSYSU

 This dissertation presents an efficient and fast VLSI architecture of a vector graphics hardware accelerator. To render a vector graphics object, the contours of paths… (more)

Subjects/Keywords: Tessellation; Rasterization; Adaptive Forward Difference; Scan-line Buffer; Vector Graphics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tung, T. (2014). Design and Implementation of Vector Graphics Accelerator Equipped with a Tessellation Processor. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0109114-110239

Chicago Manual of Style (16th Edition):

Tung, Ting-Chi. “Design and Implementation of Vector Graphics Accelerator Equipped with a Tessellation Processor.” 2014. Doctoral Dissertation, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0109114-110239.

MLA Handbook (7th Edition):

Tung, Ting-Chi. “Design and Implementation of Vector Graphics Accelerator Equipped with a Tessellation Processor.” 2014. Web. 22 Apr 2021.

Vancouver:

Tung T. Design and Implementation of Vector Graphics Accelerator Equipped with a Tessellation Processor. [Internet] [Doctoral dissertation]. NSYSU; 2014. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0109114-110239.

Council of Science Editors:

Tung T. Design and Implementation of Vector Graphics Accelerator Equipped with a Tessellation Processor. [Doctoral Dissertation]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0109114-110239


NSYSU

28. Chen, Yi-Chieh. A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 We present an integrated development environment (IDE) with GUI for generating and evaluating the fault-tolerant microprocessor. Designer can select from hardware options (dual-core for microprocessor,… (more)

Subjects/Keywords: Fault-Tolerant; Microprocessor; Memory; Fault Injection; Fault Coverage

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, Y. (2015). A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1115115-082713

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Yi-Chieh. “A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches.” 2015. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1115115-082713.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Yi-Chieh. “A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches.” 2015. Web. 22 Apr 2021.

Vancouver:

Chen Y. A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches. [Internet] [Thesis]. NSYSU; 2015. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1115115-082713.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Y. A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1115115-082713

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

29. Chen, Tai-Feng. A Multi-Dimension Signature Compaction Method for Efficient SoC Error Identification.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 Signature is an effective lossy compression method to reduce signal trace size at the possible cost of trace precision and implementation cost for different kinds… (more)

Subjects/Keywords: Multiple Signature Compaction Method; Signature Based Tracing Methodology; System-on-a-Chip(SoC)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, T. (2016). A Multi-Dimension Signature Compaction Method for Efficient SoC Error Identification. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0620116-101925

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Tai-Feng. “A Multi-Dimension Signature Compaction Method for Efficient SoC Error Identification.” 2016. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0620116-101925.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Tai-Feng. “A Multi-Dimension Signature Compaction Method for Efficient SoC Error Identification.” 2016. Web. 22 Apr 2021.

Vancouver:

Chen T. A Multi-Dimension Signature Compaction Method for Efficient SoC Error Identification. [Internet] [Thesis]. NSYSU; 2016. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0620116-101925.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen T. A Multi-Dimension Signature Compaction Method for Efficient SoC Error Identification. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0620116-101925

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

30. Wang, Ling-yu. Integration design environment for configurable on-chip bus monitor.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 Nowadays, because the advance of the technology, a single chip can contain more and more Intellectual Property(IP). As the design increase with the IPs from… (more)

Subjects/Keywords: Automatically; Reconfigurable; Protocol Monitor; Performance Monitor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, L. (2017). Integration design environment for configurable on-chip bus monitor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725117-161146

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Ling-yu. “Integration design environment for configurable on-chip bus monitor.” 2017. Thesis, NSYSU. Accessed April 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725117-161146.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Ling-yu. “Integration design environment for configurable on-chip bus monitor.” 2017. Web. 22 Apr 2021.

Vancouver:

Wang L. Integration design environment for configurable on-chip bus monitor. [Internet] [Thesis]. NSYSU; 2017. [cited 2021 Apr 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725117-161146.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang L. Integration design environment for configurable on-chip bus monitor. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725117-161146

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2]

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