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You searched for +publisher:"NSYSU" +contributor:("Chuen-Yau Chen"). Showing records 1 – 27 of 27 total matches.

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NSYSU

1. Chang, Jia-hao. Design of Tessellation Unit for 3D Graphic Processor.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 Tessellation shader is one of the advanced graphics rendering functions supported in state-of-the-art graphics standard applications programming interfaces such as OpenGL 4.x and DirextX 11.… (more)

Subjects/Keywords: tessellation; tessellation primitive generation; OpenGL 4.x; tessellation unit; primitive assembly unit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, J. (2017). Design of Tessellation Unit for 3D Graphic Processor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Jia-hao. “Design of Tessellation Unit for 3D Graphic Processor.” 2017. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Jia-hao. “Design of Tessellation Unit for 3D Graphic Processor.” 2017. Web. 27 Sep 2020.

Vancouver:

Chang J. Design of Tessellation Unit for 3D Graphic Processor. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang J. Design of Tessellation Unit for 3D Graphic Processor. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

2. Lee, Hsin-mau. Designs, Implementations and Applications of Floating-Point Trigonometric Function Units.

Degree: Master, Computer Science and Engineering, 2008, NSYSU

 In addition to the previous pipelined floating-point CORDIC design, three different architectures supporting both CORDIC rotation mode and vectoring mode are proposed in this thesis.… (more)

Subjects/Keywords: Floating-point; CORDIC

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APA (6th Edition):

Lee, H. (2008). Designs, Implementations and Applications of Floating-Point Trigonometric Function Units. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lee, Hsin-mau. “Designs, Implementations and Applications of Floating-Point Trigonometric Function Units.” 2008. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lee, Hsin-mau. “Designs, Implementations and Applications of Floating-Point Trigonometric Function Units.” 2008. Web. 27 Sep 2020.

Vancouver:

Lee H. Designs, Implementations and Applications of Floating-Point Trigonometric Function Units. [Internet] [Thesis]. NSYSU; 2008. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee H. Designs, Implementations and Applications of Floating-Point Trigonometric Function Units. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-203251

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

3. Lin, Wei-Sen. Design of Unified Arithmetic Units for 3D Graphics Vertex Shader.

Degree: Master, Computer Science and Engineering, 2008, NSYSU

 Vertex shader, one of the core parts in 3D graphics systems, is to speed up the operations of coordinate transformation and lighting in 3D graphics… (more)

Subjects/Keywords: Vertex Shader; higher-order approximation; throughput of the matrix computation

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APA (6th Edition):

Lin, W. (2008). Design of Unified Arithmetic Units for 3D Graphics Vertex Shader. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-114207

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Wei-Sen. “Design of Unified Arithmetic Units for 3D Graphics Vertex Shader.” 2008. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-114207.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Wei-Sen. “Design of Unified Arithmetic Units for 3D Graphics Vertex Shader.” 2008. Web. 27 Sep 2020.

Vancouver:

Lin W. Design of Unified Arithmetic Units for 3D Graphics Vertex Shader. [Internet] [Thesis]. NSYSU; 2008. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-114207.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin W. Design of Unified Arithmetic Units for 3D Graphics Vertex Shader. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-114207

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

4. Fu, Chien-jung. Design of Various VLSI Sorting Accelerator Architectures.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

 In this thesis, various designs of VLSI sorter architectures are proposed. This thesis first presents a baseline serial sorter architecture built on a central memory… (more)

Subjects/Keywords: Sorter; Odd-Even merge sort

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APA (6th Edition):

Fu, C. (2009). Design of Various VLSI Sorting Accelerator Architectures. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831109-115655

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fu, Chien-jung. “Design of Various VLSI Sorting Accelerator Architectures.” 2009. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831109-115655.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fu, Chien-jung. “Design of Various VLSI Sorting Accelerator Architectures.” 2009. Web. 27 Sep 2020.

Vancouver:

Fu C. Design of Various VLSI Sorting Accelerator Architectures. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831109-115655.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fu C. Design of Various VLSI Sorting Accelerator Architectures. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831109-115655

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

5. Lin, Chueh-Ting. Multi-bank Memory-based Matrix-Transposer Circuit Generator.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

 A novel design methodology of parallel VLSI matrix transposer circuit based on a multi-bank memory architecture is presented. The proposed transposer design is especially suitable… (more)

Subjects/Keywords: Matrix Transposer

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APA (6th Edition):

Lin, C. (2009). Multi-bank Memory-based Matrix-Transposer Circuit Generator. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-113406

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Chueh-Ting. “Multi-bank Memory-based Matrix-Transposer Circuit Generator.” 2009. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-113406.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Chueh-Ting. “Multi-bank Memory-based Matrix-Transposer Circuit Generator.” 2009. Web. 27 Sep 2020.

Vancouver:

Lin C. Multi-bank Memory-based Matrix-Transposer Circuit Generator. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-113406.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin C. Multi-bank Memory-based Matrix-Transposer Circuit Generator. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-113406

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

6. Lee, Cheng-Han. Design, Analysis and Applications of Hybrid CORDIC Processor Architectures.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 In this thesis, we propose different CORDIC architectures which solve the problems of long-latency in traditional pipeline CORDIC and the large-area cost in table-based CORDIC.… (more)

Subjects/Keywords: Arithmetic Function Units; CORDIC; Taylor-series expansion

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APA (6th Edition):

Lee, C. (2010). Design, Analysis and Applications of Hybrid CORDIC Processor Architectures. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lee, Cheng-Han. “Design, Analysis and Applications of Hybrid CORDIC Processor Architectures.” 2010. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lee, Cheng-Han. “Design, Analysis and Applications of Hybrid CORDIC Processor Architectures.” 2010. Web. 27 Sep 2020.

Vancouver:

Lee C. Design, Analysis and Applications of Hybrid CORDIC Processor Architectures. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee C. Design, Analysis and Applications of Hybrid CORDIC Processor Architectures. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

7. Tsai, Cheng-Hsuan. Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, various new logic circuit design styles based on… (more)

Subjects/Keywords: CMOS logic; Logic Synthesizer; Standard Cell Library; ASIC Design Flow; Pass-Transition-Logic(PTL)

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APA (6th Edition):

Tsai, C. (2010). Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tsai, Cheng-Hsuan. “Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library.” 2010. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tsai, Cheng-Hsuan. “Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library.” 2010. Web. 27 Sep 2020.

Vancouver:

Tsai C. Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsai C. Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

8. Chiu, Chan-Feng. Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 This thesis focuses on efficient design of a vertex shader for per-vertex operations such as Transformation and Lighting in the OpenGL ES 2.0 graphics pipeline.… (more)

Subjects/Keywords: 3D Graph; Logarithmic Number System; Vertex Shader

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APA (6th Edition):

Chiu, C. (2010). Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chiu, Chan-Feng. “Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System.” 2010. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chiu, Chan-Feng. “Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System.” 2010. Web. 27 Sep 2020.

Vancouver:

Chiu C. Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chiu C. Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

9. Chen, Li-Yao. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 OpenGL ES 2.0 programmable 3D graphics pipeline is the current new standard for embedded graphics processor designs. The programmable vertex shader replaces the geometry operations… (more)

Subjects/Keywords: Integration; SOC; Programmable; SIMD; Vertex Shader

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, L. (2010). Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Li-Yao. “Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.” 2010. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Li-Yao. “Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.” 2010. Web. 27 Sep 2020.

Vancouver:

Chen L. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen L. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

10. Feng, Hao. A Memory-Efficient and Low-power Architecture for Tail-biting Convolution Code Decoder.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 In wireless communication system, the data will be interfered easily with noise during transmission, thus the transmitter usually uses convolution code to encode the data.… (more)

Subjects/Keywords: pre-traceback; low power; wireless communication; error detection; tail-biting convolutional code; Viterbi decoder

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APA (6th Edition):

Feng, H. (2014). A Memory-Efficient and Low-power Architecture for Tail-biting Convolution Code Decoder. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715114-133649

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Feng, Hao. “A Memory-Efficient and Low-power Architecture for Tail-biting Convolution Code Decoder.” 2014. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715114-133649.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Feng, Hao. “A Memory-Efficient and Low-power Architecture for Tail-biting Convolution Code Decoder.” 2014. Web. 27 Sep 2020.

Vancouver:

Feng H. A Memory-Efficient and Low-power Architecture for Tail-biting Convolution Code Decoder. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715114-133649.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Feng H. A Memory-Efficient and Low-power Architecture for Tail-biting Convolution Code Decoder. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715114-133649

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

11. Lu, Ren-yao. High-performance High-radix Word-based Montgomery Modular Multipliers.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Nowadays, with the evolution of the internet,network becomes an important role in human's life. Because more and more E-commerce and electronic transaction are implemented in… (more)

Subjects/Keywords: Public-key Cryptosystems; RSA Cryptosystems; High-radix Word-based Montgomery Modular Multiplier; Montgomery Modular Multiplier

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APA (6th Edition):

Lu, R. (2014). High-performance High-radix Word-based Montgomery Modular Multipliers. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0718114-165103

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lu, Ren-yao. “High-performance High-radix Word-based Montgomery Modular Multipliers.” 2014. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0718114-165103.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lu, Ren-yao. “High-performance High-radix Word-based Montgomery Modular Multipliers.” 2014. Web. 27 Sep 2020.

Vancouver:

Lu R. High-performance High-radix Word-based Montgomery Modular Multipliers. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0718114-165103.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lu R. High-performance High-radix Word-based Montgomery Modular Multipliers. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0718114-165103

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

12. Lin, Hong. Design of Ray Tracing Circuit with Hybrid Single and Packet Ray Traversal.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Ray-tracing can render more realistic images than the traditional depth-buffer based rendering approach such that many people expect it can be gradually applied to embedded… (more)

Subjects/Keywords: Ray-tracing; Packet ray; Single ray; Hybrid traversal

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APA (6th Edition):

Lin, H. (2014). Design of Ray Tracing Circuit with Hybrid Single and Packet Ray Traversal. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810114-165952

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Hong. “Design of Ray Tracing Circuit with Hybrid Single and Packet Ray Traversal.” 2014. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810114-165952.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Hong. “Design of Ray Tracing Circuit with Hybrid Single and Packet Ray Traversal.” 2014. Web. 27 Sep 2020.

Vancouver:

Lin H. Design of Ray Tracing Circuit with Hybrid Single and Packet Ray Traversal. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810114-165952.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin H. Design of Ray Tracing Circuit with Hybrid Single and Packet Ray Traversal. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810114-165952

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

13. Li, Jin-wei. Design of some DSP circuits based on stochastic computation.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Stochastic computing (SC) has recently gained attention due to its fault-tolerance property. Different from the ordinary binary computing, this unconventional approach represents numbers using the… (more)

Subjects/Keywords: discrete cosine transform; tail-biting convolution; low-density parity-check; stochastic decoding; stochastic computing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, J. (2014). Design of some DSP circuits based on stochastic computation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811114-025841

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Jin-wei. “Design of some DSP circuits based on stochastic computation.” 2014. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811114-025841.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Jin-wei. “Design of some DSP circuits based on stochastic computation.” 2014. Web. 27 Sep 2020.

Vancouver:

Li J. Design of some DSP circuits based on stochastic computation. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811114-025841.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li J. Design of some DSP circuits based on stochastic computation. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811114-025841

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

14. Lin, Yang-yi. Integration and Verification of A Multi-Function Texture Unit with Graphics Processor Units.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 With the increasing demand of graphics applications in mobile devices, how to design an efficient embedded graphics processor unit (GPU) has become a hot issue.… (more)

Subjects/Keywords: multi-function texture unit; vector graphics accelerator; 3D graphics processor; RTL; FPGA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, Y. (2014). Integration and Verification of A Multi-Function Texture Unit with Graphics Processor Units. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811114-082500

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Yang-yi. “Integration and Verification of A Multi-Function Texture Unit with Graphics Processor Units.” 2014. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811114-082500.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Yang-yi. “Integration and Verification of A Multi-Function Texture Unit with Graphics Processor Units.” 2014. Web. 27 Sep 2020.

Vancouver:

Lin Y. Integration and Verification of A Multi-Function Texture Unit with Graphics Processor Units. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811114-082500.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin Y. Integration and Verification of A Multi-Function Texture Unit with Graphics Processor Units. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811114-082500

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

15. Tong, Ting-Chi. Bandwidth Optimized Integrated Predictive Pixel Compensator of H.264 Decoder.

Degree: Master, Computer Science and Engineering, 2008, NSYSU

 In this thesis, a high-efficient integrated pixel compensator architecture for the H.264/AVC standard has been proposed which can provide both inter and intra prediction functions… (more)

Subjects/Keywords: Predictive Pixel Compensator; Inter Prediction; Intra Prediction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tong, T. (2008). Bandwidth Optimized Integrated Predictive Pixel Compensator of H.264 Decoder. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807108-200335

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tong, Ting-Chi. “Bandwidth Optimized Integrated Predictive Pixel Compensator of H.264 Decoder.” 2008. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807108-200335.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tong, Ting-Chi. “Bandwidth Optimized Integrated Predictive Pixel Compensator of H.264 Decoder.” 2008. Web. 27 Sep 2020.

Vancouver:

Tong T. Bandwidth Optimized Integrated Predictive Pixel Compensator of H.264 Decoder. [Internet] [Thesis]. NSYSU; 2008. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807108-200335.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tong T. Bandwidth Optimized Integrated Predictive Pixel Compensator of H.264 Decoder. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807108-200335

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

16. Yeh, Jia-huei. An Adaptive Fuzzy Proportional-Integral Predictor for Power Management of 3D Graphics System-On-Chip.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 As time goes by rapid development of 3D graphics technique and 3C portable product output, 3D graphics have been widely applied to handheld devices, such… (more)

Subjects/Keywords: Power Management; Dynamic Voltage Frequency Scaling(DVFS); Proportional- Integral Controller; Fuzzy Controller

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yeh, J. (2010). An Adaptive Fuzzy Proportional-Integral Predictor for Power Management of 3D Graphics System-On-Chip. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802110-133640

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yeh, Jia-huei. “An Adaptive Fuzzy Proportional-Integral Predictor for Power Management of 3D Graphics System-On-Chip.” 2010. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802110-133640.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yeh, Jia-huei. “An Adaptive Fuzzy Proportional-Integral Predictor for Power Management of 3D Graphics System-On-Chip.” 2010. Web. 27 Sep 2020.

Vancouver:

Yeh J. An Adaptive Fuzzy Proportional-Integral Predictor for Power Management of 3D Graphics System-On-Chip. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802110-133640.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yeh J. An Adaptive Fuzzy Proportional-Integral Predictor for Power Management of 3D Graphics System-On-Chip. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802110-133640

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

17. Yeh, Wei-ting. A Low-power Convolutional Decoder with Error Detection Ability.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 In wireless communication systems, we may encounter many problems. One of the main issues is noise interference. To overcome the problem, the sender can use… (more)

Subjects/Keywords: Modulo Normalization; Dynamic Decoding Ability; Viterbi Decoder; Error Detection

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yeh, W. (2010). A Low-power Convolutional Decoder with Error Detection Ability. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803110-152658

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yeh, Wei-ting. “A Low-power Convolutional Decoder with Error Detection Ability.” 2010. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803110-152658.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yeh, Wei-ting. “A Low-power Convolutional Decoder with Error Detection Ability.” 2010. Web. 27 Sep 2020.

Vancouver:

Yeh W. A Low-power Convolutional Decoder with Error Detection Ability. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803110-152658.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yeh W. A Low-power Convolutional Decoder with Error Detection Ability. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803110-152658

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

18. Tsao, Kai-hsiang. Performance Optimization and Low Power Design of a Programmable 3D Graphics Processor.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Low-Power High-Speed graphics processing unit (GPU) is one of the key hardware components in modern mobile devices such as smart phones. In this thesis, we… (more)

Subjects/Keywords: OpenGL; Graphics; SIMD; Processing; Hazard; Architecture; Forwarding; Low Power; GPU

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tsao, K. (2014). Performance Optimization and Low Power Design of a Programmable 3D Graphics Processor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-134846

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tsao, Kai-hsiang. “Performance Optimization and Low Power Design of a Programmable 3D Graphics Processor.” 2014. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-134846.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tsao, Kai-hsiang. “Performance Optimization and Low Power Design of a Programmable 3D Graphics Processor.” 2014. Web. 27 Sep 2020.

Vancouver:

Tsao K. Performance Optimization and Low Power Design of a Programmable 3D Graphics Processor. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-134846.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsao K. Performance Optimization and Low Power Design of a Programmable 3D Graphics Processor. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-134846

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

19. Wu, Bo-sheng. Acceleration of Image Feature Extraction Algorithms.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 The description of local features of images has been successfully applied to many areas, including wide baseline matching, object recognition, texture recognition, image retrieval, robot… (more)

Subjects/Keywords: scale-invariant feature transform; Speeded-Up Robust Feature; hardware acceleration; image feature extraction; OpenCL; GPGPU

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, B. (2014). Acceleration of Image Feature Extraction Algorithms. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810114-020324

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Bo-sheng. “Acceleration of Image Feature Extraction Algorithms.” 2014. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810114-020324.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Bo-sheng. “Acceleration of Image Feature Extraction Algorithms.” 2014. Web. 27 Sep 2020.

Vancouver:

Wu B. Acceleration of Image Feature Extraction Algorithms. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810114-020324.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu B. Acceleration of Image Feature Extraction Algorithms. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810114-020324

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

20. HSU, CHUN-TO. Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Read-only memory (ROM) plays an important role In modern System-on-Chip (SoC) designs. Due to the regularity of ROM structure, ROM components are usually generated through… (more)

Subjects/Keywords: RTL Compiler; ROM generator; Programmable Logic Array (PLA); ROM Compiler

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

HSU, C. (2014). Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726114-101438

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

HSU, CHUN-TO. “Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM.” 2014. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726114-101438.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

HSU, CHUN-TO. “Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM.” 2014. Web. 27 Sep 2020.

Vancouver:

HSU C. Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726114-101438.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

HSU C. Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726114-101438

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

21. Lu, Bo-Han. Enhanced Verification of Lane-Based Front Vehicle Detection System in Daytime and Nighttime.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 In this thesis, we present a front-vehicle detection system in both daytime and night time. The key philosophy is simplicity in order to reduce computation… (more)

Subjects/Keywords: vehicle detection; driver assisted system (DAS); lane detection

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lu, B. (2014). Enhanced Verification of Lane-Based Front Vehicle Detection System in Daytime and Nighttime. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-140100

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lu, Bo-Han. “Enhanced Verification of Lane-Based Front Vehicle Detection System in Daytime and Nighttime.” 2014. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-140100.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lu, Bo-Han. “Enhanced Verification of Lane-Based Front Vehicle Detection System in Daytime and Nighttime.” 2014. Web. 27 Sep 2020.

Vancouver:

Lu B. Enhanced Verification of Lane-Based Front Vehicle Detection System in Daytime and Nighttime. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-140100.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lu B. Enhanced Verification of Lane-Based Front Vehicle Detection System in Daytime and Nighttime. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-140100

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

22. Lin, Chi-Guang. Bus Interface Design Between Different Clock Domains and Its Application to OpenGL-ES 2.0 3D Graphics Systems.

Degree: Master, Computer Science and Engineering, 2011, NSYSU

 Asynchronous bus interface units to AMBA AHB are designed so that an OpenGL ES 2.0 vertex shader can communicate with other hardware units via AHB… (more)

Subjects/Keywords: vertex shader; Open Core Protocol; OpenGL ES 2.0; AHB; asynchronous bus interface

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, C. (2011). Bus Interface Design Between Different Clock Domains and Its Application to OpenGL-ES 2.0 3D Graphics Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726111-142933

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Chi-Guang. “Bus Interface Design Between Different Clock Domains and Its Application to OpenGL-ES 2.0 3D Graphics Systems.” 2011. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726111-142933.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Chi-Guang. “Bus Interface Design Between Different Clock Domains and Its Application to OpenGL-ES 2.0 3D Graphics Systems.” 2011. Web. 27 Sep 2020.

Vancouver:

Lin C. Bus Interface Design Between Different Clock Domains and Its Application to OpenGL-ES 2.0 3D Graphics Systems. [Internet] [Thesis]. NSYSU; 2011. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726111-142933.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin C. Bus Interface Design Between Different Clock Domains and Its Application to OpenGL-ES 2.0 3D Graphics Systems. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726111-142933

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

23. Chen, Chun-Chi. A Generalized Design Method for High-radix Word-based Montgomery Modular Multipliers.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 With the rapid development of the Internet, human can not live without the Internet today.Moreover,the trading behavior through the Internet is more frequently. Therefore,much attention… (more)

Subjects/Keywords: Montgomery Modular Multiplier; RSA Cryptosystems; Public-key Cryptosystems; High-radix Word-based Montgomery Modular Multiplier

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, C. (2015). A Generalized Design Method for High-radix Word-based Montgomery Modular Multipliers. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0630115-155954

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Chun-Chi. “A Generalized Design Method for High-radix Word-based Montgomery Modular Multipliers.” 2015. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0630115-155954.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Chun-Chi. “A Generalized Design Method for High-radix Word-based Montgomery Modular Multipliers.” 2015. Web. 27 Sep 2020.

Vancouver:

Chen C. A Generalized Design Method for High-radix Word-based Montgomery Modular Multipliers. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0630115-155954.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen C. A Generalized Design Method for High-radix Word-based Montgomery Modular Multipliers. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0630115-155954

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

24. Hsu, Li-wei. A Variable-precision Architecture for Special Function and Floating-point Multiply-add-fused Operation.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 This thesis presents a variable-precision floating-point arithmetic unit based on IEEE-754 single precision floating standard. This arithmetic unit combines special function interpolator and floating-point multiply-add-fused.… (more)

Subjects/Keywords: A Variable-precision floating point multiply-add-fused; low power; A Variable-precision function interpolator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hsu, L. (2015). A Variable-precision Architecture for Special Function and Floating-point Multiply-add-fused Operation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0630115-162031

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsu, Li-wei. “A Variable-precision Architecture for Special Function and Floating-point Multiply-add-fused Operation.” 2015. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0630115-162031.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsu, Li-wei. “A Variable-precision Architecture for Special Function and Floating-point Multiply-add-fused Operation.” 2015. Web. 27 Sep 2020.

Vancouver:

Hsu L. A Variable-precision Architecture for Special Function and Floating-point Multiply-add-fused Operation. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0630115-162031.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu L. A Variable-precision Architecture for Special Function and Floating-point Multiply-add-fused Operation. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0630115-162031

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

25. Tsai, Ming-chi. Design of Vertex and Per-Fragment Processor for 3D Graphics Rendering.

Degree: Master, Computer Science and Engineering, 2007, NSYSU

 For the past few years, with the rapid advance of VLSI and multimedia technology, the applications of three-dimensional (3D) graphic applications have been widely and… (more)

Subjects/Keywords: per-fragment processor; vertex processor; 3d graphic rendering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tsai, M. (2007). Design of Vertex and Per-Fragment Processor for 3D Graphics Rendering. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904107-153556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tsai, Ming-chi. “Design of Vertex and Per-Fragment Processor for 3D Graphics Rendering.” 2007. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904107-153556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tsai, Ming-chi. “Design of Vertex and Per-Fragment Processor for 3D Graphics Rendering.” 2007. Web. 27 Sep 2020.

Vancouver:

Tsai M. Design of Vertex and Per-Fragment Processor for 3D Graphics Rendering. [Internet] [Thesis]. NSYSU; 2007. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904107-153556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsai M. Design of Vertex and Per-Fragment Processor for 3D Graphics Rendering. [Thesis]. NSYSU; 2007. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904107-153556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

26. Lin, Huang-lun. Advanced Texture Unit Design for 3D Rendering System.

Degree: Master, Computer Science and Engineering, 2007, NSYSU

 In order to achieve more realistic visual effect, the texturing mapping has become a very important and popular technique used in three-dimensional (3D) graphic. Many… (more)

Subjects/Keywords: texture mapping; texture unit; tri-linear filtering; texture cache; bi-linear filtering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, H. (2007). Advanced Texture Unit Design for 3D Rendering System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0905107-125938

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Huang-lun. “Advanced Texture Unit Design for 3D Rendering System.” 2007. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0905107-125938.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Huang-lun. “Advanced Texture Unit Design for 3D Rendering System.” 2007. Web. 27 Sep 2020.

Vancouver:

Lin H. Advanced Texture Unit Design for 3D Rendering System. [Internet] [Thesis]. NSYSU; 2007. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0905107-125938.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin H. Advanced Texture Unit Design for 3D Rendering System. [Thesis]. NSYSU; 2007. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0905107-125938

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

27. Wang, Jhih-Jian. Design and Implementation of a Low-cost DVB Channel Decoder.

Degree: Master, Computer Science and Engineering, 2005, NSYSU

 In this thesis, a highly efficient implementation of the channel decoder for terrestrial digital video broadcast (DVBT) standard is proposed. DVB-T channel decoder is mainly… (more)

Subjects/Keywords: DVB; channel decoder; convolutional deinterleaver; symbol deinterleaver; bit deinterleaver

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, J. (2005). Design and Implementation of a Low-cost DVB Channel Decoder. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0906105-052428

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Jhih-Jian. “Design and Implementation of a Low-cost DVB Channel Decoder.” 2005. Thesis, NSYSU. Accessed September 27, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0906105-052428.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Jhih-Jian. “Design and Implementation of a Low-cost DVB Channel Decoder.” 2005. Web. 27 Sep 2020.

Vancouver:

Wang J. Design and Implementation of a Low-cost DVB Channel Decoder. [Internet] [Thesis]. NSYSU; 2005. [cited 2020 Sep 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0906105-052428.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang J. Design and Implementation of a Low-cost DVB Channel Decoder. [Thesis]. NSYSU; 2005. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0906105-052428

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.