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You searched for +publisher:"NSYSU" +contributor:("Chris Lee"). Showing records 1 – 2 of 2 total matches.

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NSYSU

1. Wu, Cheng-Ta. SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

Nowadays, due to improvement of fabrication and IP design technology, the design complexity of System on Chip is increasing very fast. Thus we need huge amount of test pattern to verify the SOC, so how to verify the system effectively is very important. In this thesis, we take the 3DG OpenGL ES2.0 SoC which was developed by our 3DG design group as example, introducing how to build a verification platform with unified method through each level from System Modeling Level to FPGA Emulation Level. Furthermore, we use the automatic verification mechanism to improve the effectiveness of the test pattern and correctness of comparison results. And in order to improve the performance of 3DG OpenGL ES2.0 SoC, we change the original adopted AHB system bus into high performance AXI system bus. We use coreConsultant (developed by Synopsys) to generate the related IP modules, so we can save development and verification time of modules under AXI environment, and we will also introduce the flow of IP generation and synthesis in this thesis. Advisors/Committee Members: Chris Lee (chair), Kuen-Jong Lee (chair), Ing-Jer Huang (committee member), Yun-Nan Chang (chair).

Subjects/Keywords: BUS; AXI; AHB; Verification; OpenGL ES2.0; Integration

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, C. (2013). SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1015113-190908

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Cheng-Ta. “SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC.” 2013. Thesis, NSYSU. Accessed October 14, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1015113-190908.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Cheng-Ta. “SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC.” 2013. Web. 14 Oct 2019.

Vancouver:

Wu C. SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Oct 14]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1015113-190908.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu C. SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1015113-190908

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

2. Huang, Shih-tung. Hardware/software co-verification for processor-OpenOCD integration.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

We usually use RVDS [18] (RealView Development Suite) and MUlTI-ICE (protocol converter) as ARM program debug environment by controlling ICE module for controlling CPU. But now we have another choice, ie the debug tool chain that Eclipse, GDB and OpenOCD (Open On-Chip Debugger) combination. We achieve program debugging by using a protocol converter called ft2232 that FIDI Company produced to connect ICE module with JTAG port. However, for ARM7-like CPU, ie. SYS32TM, ICE can control the CPU module that our laboratory develops. No matter the ARM RVDS or OpenOCD can not observate the interactive of debugger and ICE, it such that the verification of ICE and debugger is a difficult thing. In order to solve this problem, we consider PLI (Program Level Interface) to communicate with the RTL simulator and then connect to OpenOCD, or use the Platform Architect itself co-simulation environment connected OpenOCD. Finally, we chose Platform Architect environment and find the JTAGSC [4] as a protocol converter that come from embecosm EAN5 that can put into the Platform Architect environment. To achieve the purpose of co-verification, we ued shared memory mechanism to communication with OpenOCD and Platform Architect environment that JTAGSC had put into. Advisors/Committee Members: Chris Lee (chair), Yun-Nan Chang (chair), Tong-Yu Hsieh (chair), Kuen-Jong Lee (chair), Ing-Jer Huang (committee member).

Subjects/Keywords: OpenOCD (Open On-Chip Debugger); GNU Debugger; Co-verification; EICE (Embedded In-Circuit Emulator); JTAG

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, S. (2013). Hardware/software co-verification for processor-OpenOCD integration. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715113-211836

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Shih-tung. “Hardware/software co-verification for processor-OpenOCD integration.” 2013. Thesis, NSYSU. Accessed October 14, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715113-211836.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Shih-tung. “Hardware/software co-verification for processor-OpenOCD integration.” 2013. Web. 14 Oct 2019.

Vancouver:

Huang S. Hardware/software co-verification for processor-OpenOCD integration. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Oct 14]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715113-211836.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang S. Hardware/software co-verification for processor-OpenOCD integration. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715113-211836

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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