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You searched for +publisher:"NSYSU" +contributor:("Bin-Da Liu"). Showing records 1 – 3 of 3 total matches.

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NSYSU

1. Tsai, Ming-Yu. An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors.

Degree: PhD, Computer Science and Engineering, 2009, NSYSU

The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, in the past two decades, various new logic circuit design styles based on pass-transistor logic (PTL) have been proposed. Compared with CMOS circuits, these PTL-based circuits are claimed to have better results in area, speed, and power in some particular applications, such as adder and multiplier designs. Since most current automatic logic synthesis tools (such as Synopsys Design Compiler) are based on conventional CMOS standard cell library, the corresponding logic minimization for CMOS logic cannot be directly employed to generate efficient PTL circuits. In this dissertation, we develop two novel PTL synthesizers that can efficiently generate PTL-based circuits. One is based on pure PTL cells; the other mixes CMOS and PTL cells in the standard cell library to achieve better performance in area, speed, and power. Since PTL-based circuits are constructed by only a few basic PTL cells, the layouts in PTL cells can be easily updated to design large SoC systems as the process technology migrates rapidly in current Nano technology era. The proposed PTL logic synthesis flows employ the popular Synopsys Design Compiler (DC) to perform logic translation and minimization based on the standard cell library composed of PTL and CMOS cells, thus, the PTL design flow can be easily embedded in the standard cell-based ASIC design flow. In this dissertation, we also discuss PTL-based designs of some fundamental hardware components. Furthermore, the proposed PTL cell library is used to synthesize large processor systems in applications of computer arithmetic and 3D graphics. Advisors/Committee Members: Bin-Da Liu (chair), Tso-Bing Juang (committee member), Shen-Fu Hsiao (committee member), Pei-Yin Chen (chair), Yuan-Sun Chu (chair), Chen-Hao Chang (chair), Yu-Jung Huang (chair).

Subjects/Keywords: 3D Graphics Processors; Arithmetic Units; Standard Cell Library; ASIC Cell-Based Design Flow; Logic Synthesizer; Pass-Transistor-Logic (PTL); CMOS logic

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APA (6th Edition):

Tsai, M. (2009). An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529

Chicago Manual of Style (16th Edition):

Tsai, Ming-Yu. “An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors.” 2009. Doctoral Dissertation, NSYSU. Accessed July 21, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529.

MLA Handbook (7th Edition):

Tsai, Ming-Yu. “An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors.” 2009. Web. 21 Jul 2019.

Vancouver:

Tsai M. An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors. [Internet] [Doctoral dissertation]. NSYSU; 2009. [cited 2019 Jul 21]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529.

Council of Science Editors:

Tsai M. An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors. [Doctoral Dissertation]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529


NSYSU

2. Wen, Chia-Sheng. Table Based Design for Function Evaluation and Error Correcting Codes.

Degree: PhD, Computer Science and Engineering, 2012, NSYSU

Lookup-table (LUT)-based method is a common approach used in all kinds of research topics. In this dissertation, we present several new designs for table-based function evaluation and table-based error correcting coding. In Chapter 3, a new function evaluation method, called two-level approximation, is presented where piecewise degree-one polynomials are used for initial approximation in the first level, followed by the refined approximation for the shared normalized difference functions in the second level. In Chapter 4, we present a new non-uniform segmentation method that searches for the optimal segmentation scheme with the different design goals of minimizing either ROM, total area, or delay. In Chapter 5, a new design methodology for table-based function evaluation is presented. Unlike previous approaches that usually determine the bit widths by assigning allowable errors for individual hardware components, the total error budget of our new design is considered jointly in order to optimized the bit widths of all the hardware components, leading to significant improvements in both area and delay. Finally, in Chapter 6, the similar table-based concept is used in the design of error correcting encoder using the modified polynomial of the Lagrange interpolation formula, resulting in smaller critical path delay and lower power consumption. Advisors/Committee Members: Shen-Fu Hsiao (committee member), Bin-Da Liu (chair), Pei-Yung Hsiao (chair), Tso-Bing Juang (chair), Yan-Haw Chen (committee member), Trieu-Kien Truong (chair).

Subjects/Keywords: function evaluation; piecewise polynomial approximation; Reed-Solomon code; table-based methods; error correcting coding

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wen, C. (2012). Table Based Design for Function Evaluation and Error Correcting Codes. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723112-012802

Chicago Manual of Style (16th Edition):

Wen, Chia-Sheng. “Table Based Design for Function Evaluation and Error Correcting Codes.” 2012. Doctoral Dissertation, NSYSU. Accessed July 21, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723112-012802.

MLA Handbook (7th Edition):

Wen, Chia-Sheng. “Table Based Design for Function Evaluation and Error Correcting Codes.” 2012. Web. 21 Jul 2019.

Vancouver:

Wen C. Table Based Design for Function Evaluation and Error Correcting Codes. [Internet] [Doctoral dissertation]. NSYSU; 2012. [cited 2019 Jul 21]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723112-012802.

Council of Science Editors:

Wen C. Table Based Design for Function Evaluation and Error Correcting Codes. [Doctoral Dissertation]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723112-012802


NSYSU

3. Chen, Ming-Chih. Low Cost Design of Advanced Encryption Standard (AES) Algorithm Using Efficient Common Sub-expression Elimination Methods.

Degree: PhD, Computer Science and Engineering, 2005, NSYSU

In this dissertation, we propose area-efficient Advanced Encryption Standard (AES) processor designs by applying four new common-subexpression-elimination (CSE) algorithms to the sub-functions that realize the various transformations in AES encryption and decryption. The first category of sub-functions is derived by combining adjacent transformations in each AES round into a new transformation. The other category of sub-functions is from the integrated transformations in the AES encryption and decryption process with shared common operations. Then the proposed bit-level CSE algorithm reduces further the area cost of realizing the sub-functions by extracting the common factors in the bit-level expressions of these sub-functions. The separate area-reduction effects of combinations, integrations and CSE optimization mentioned above are analyzed in order to examine the efficiency of each technique. Cell-based implementation results show that the area reduction rates of the AES processors with our proposed CSE methods achieve significant area improvement compared with Synopsys optimization results. Advisors/Committee Members: Bin-Da Liu (chair), Ming-Hwa Sheu (chair), Chua-Chin Wang (chair), Jiun-In Guo (chair), Shen-Fu Hsiao (committee member), Jau-Der Shih (chair).

Subjects/Keywords: Logic Optimization; AES; VLSI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, M. (2005). Low Cost Design of Advanced Encryption Standard (AES) Algorithm Using Efficient Common Sub-expression Elimination Methods. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1005105-143759

Chicago Manual of Style (16th Edition):

Chen, Ming-Chih. “Low Cost Design of Advanced Encryption Standard (AES) Algorithm Using Efficient Common Sub-expression Elimination Methods.” 2005. Doctoral Dissertation, NSYSU. Accessed July 21, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1005105-143759.

MLA Handbook (7th Edition):

Chen, Ming-Chih. “Low Cost Design of Advanced Encryption Standard (AES) Algorithm Using Efficient Common Sub-expression Elimination Methods.” 2005. Web. 21 Jul 2019.

Vancouver:

Chen M. Low Cost Design of Advanced Encryption Standard (AES) Algorithm Using Efficient Common Sub-expression Elimination Methods. [Internet] [Doctoral dissertation]. NSYSU; 2005. [cited 2019 Jul 21]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1005105-143759.

Council of Science Editors:

Chen M. Low Cost Design of Advanced Encryption Standard (AES) Algorithm Using Efficient Common Sub-expression Elimination Methods. [Doctoral Dissertation]. NSYSU; 2005. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1005105-143759

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