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You searched for +publisher:"Indian Institute of Science" +contributor:("Amrutur, Bharadwaj"). Showing records 1 – 22 of 22 total matches.

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Indian Institute of Science

1. Pandey, Jagadish Narayan. Low Power LO Generation Based On Frequency Multiplication Technique.

Degree: 2007, Indian Institute of Science

 TO achieve high level of integration in order to reduce cost, heterodyne architecture has made way for low-IF and zero-IF (direct conversion) receiver architectures. However,… (more)

Subjects/Keywords: Frequency Multiplexing; Local Oscillator (LO); Signal Processing; Quadrature Generation; Local Oscillator (LO) Pulling; Local Oscillator Signals; Frequency Multiplication; Frequency Multiplier; Communication Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pandey, J. N. (2007). Low Power LO Generation Based On Frequency Multiplication Technique. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/356

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pandey, Jagadish Narayan. “Low Power LO Generation Based On Frequency Multiplication Technique.” 2007. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://hdl.handle.net/2005/356.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pandey, Jagadish Narayan. “Low Power LO Generation Based On Frequency Multiplication Technique.” 2007. Web. 08 Apr 2020.

Vancouver:

Pandey JN. Low Power LO Generation Based On Frequency Multiplication Technique. [Internet] [Thesis]. Indian Institute of Science; 2007. [cited 2020 Apr 08]. Available from: http://hdl.handle.net/2005/356.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pandey JN. Low Power LO Generation Based On Frequency Multiplication Technique. [Thesis]. Indian Institute of Science; 2007. Available from: http://hdl.handle.net/2005/356

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

2. Vivekanandham, Rajesh. Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors.

Degree: 2006, Indian Institute of Science

 A Large instruction window is a key requirement to exploit greater Instruction Level Parallelism in out-of-order superscalar processors. Along with the instruction window size, the… (more)

Subjects/Keywords: Parallel Processing (Computer Science); Queing Processes; Queue Design; Scalable Low Power Issue Queue (SLIQ) Microarchitecture; Scalable Low Power Store Queue (SLSQ) Microarchitecture; Superscalar Processors; Large Instruction Window; Computer Science

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APA (6th Edition):

Vivekanandham, R. (2006). Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/413

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vivekanandham, Rajesh. “Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors.” 2006. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://hdl.handle.net/2005/413.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vivekanandham, Rajesh. “Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors.” 2006. Web. 08 Apr 2020.

Vancouver:

Vivekanandham R. Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2020 Apr 08]. Available from: http://hdl.handle.net/2005/413.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vivekanandham R. Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/413

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

3. Raghavendra, R G. Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector.

Degree: 2009, Indian Institute of Science

 Phase Locked Loop (PLL) is an integral component of clock generation circuits. A third order Charge Pump PLL (CPPLL) is most widely employed PLL architecture… (more)

Subjects/Keywords: Special Devices (Computer Engineering); Analog Frequency Detector; Charge Pump Phase Locked Loop; Phase Locked Loop (PLL); Phase Locked Loop Filters; Phase Locked Loop Filter Design; Summer-Less Dual Charge Pump Based Loop Filters; Loop Filter Design; Computer Engineering

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APA (6th Edition):

Raghavendra, R. G. (2009). Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1006

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Raghavendra, R G. “Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector.” 2009. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://hdl.handle.net/2005/1006.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Raghavendra, R G. “Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector.” 2009. Web. 08 Apr 2020.

Vancouver:

Raghavendra RG. Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector. [Internet] [Thesis]. Indian Institute of Science; 2009. [cited 2020 Apr 08]. Available from: http://hdl.handle.net/2005/1006.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Raghavendra RG. Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector. [Thesis]. Indian Institute of Science; 2009. Available from: http://hdl.handle.net/2005/1006

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

4. Das, Bishnu Prasad. Random Local Delay Variability : On-chip Measurement And Modeling.

Degree: 2009, Indian Institute of Science

 This thesis focuses on random local delay variability measurement and its modeling. It explains a circuit technique to measure the individual logic gate delay in… (more)

Subjects/Keywords: Electronic Gates - Design; On-chip Management And Construction; Electronic Gate Delay - Modeling; Random Local Delay Variation; On-chip Gate Delay Measurement; Process Voltage And Temperature Gate Delay Model; Electronic Gate Delay - Measurement; Statistical Static Timing Analysis (SSTA); Gate Delay Variability Measurement; Delay Variability; On-chip Measurement; Gate Delay Models; Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Das, B. P. (2009). Random Local Delay Variability : On-chip Measurement And Modeling. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1008

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Das, Bishnu Prasad. “Random Local Delay Variability : On-chip Measurement And Modeling.” 2009. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://hdl.handle.net/2005/1008.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Das, Bishnu Prasad. “Random Local Delay Variability : On-chip Measurement And Modeling.” 2009. Web. 08 Apr 2020.

Vancouver:

Das BP. Random Local Delay Variability : On-chip Measurement And Modeling. [Internet] [Thesis]. Indian Institute of Science; 2009. [cited 2020 Apr 08]. Available from: http://hdl.handle.net/2005/1008.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Das BP. Random Local Delay Variability : On-chip Measurement And Modeling. [Thesis]. Indian Institute of Science; 2009. Available from: http://hdl.handle.net/2005/1008

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

5. Sreejith, K. A Workload Based Lookup Table For Minimal Power Operation Under Supply And Body Bias Control.

Degree: 2009, Indian Institute of Science

 Dynamic Voltage Scaling (DVS) and Adaptive body bias (ABB) techniques respectively try to reduce the dynamic and static power components of an integrated circuit. Ideally,… (more)

Subjects/Keywords: Analog Devices; Electric Power; Electric Circuits; Electronic Circuits; Minimal Power Operation; Electric Power Consumption; Integrated Circuits; Dynamic Voltage Scaling (DVS); Adaptive Body Bias (ABB); Minimal Power Operation; Power Electronics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sreejith, K. (2009). A Workload Based Lookup Table For Minimal Power Operation Under Supply And Body Bias Control. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1030

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sreejith, K. “A Workload Based Lookup Table For Minimal Power Operation Under Supply And Body Bias Control.” 2009. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://hdl.handle.net/2005/1030.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sreejith, K. “A Workload Based Lookup Table For Minimal Power Operation Under Supply And Body Bias Control.” 2009. Web. 08 Apr 2020.

Vancouver:

Sreejith K. A Workload Based Lookup Table For Minimal Power Operation Under Supply And Body Bias Control. [Internet] [Thesis]. Indian Institute of Science; 2009. [cited 2020 Apr 08]. Available from: http://hdl.handle.net/2005/1030.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sreejith K. A Workload Based Lookup Table For Minimal Power Operation Under Supply And Body Bias Control. [Thesis]. Indian Institute of Science; 2009. Available from: http://hdl.handle.net/2005/1030

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

6. Janakiraman, V. Statistical Leakage Analysis Framework Using Artificial Neural Networks Considering Process And Environmental Variations.

Degree: 2011, Indian Institute of Science

 Leakage current and process variations are two primary hurdles in modern VLSI design. It depends exponentially on process and environmental parameters and hence small variations… (more)

Subjects/Keywords: Neural Networks; Artificial Intelligence; Statistical Leakage Analysis (SLA); Leakage Modelling; Artificial Neural Network (ANN); Leakage Models; Statistical Leakage Characterization; Leakage Current; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Janakiraman, V. (2011). Statistical Leakage Analysis Framework Using Artificial Neural Networks Considering Process And Environmental Variations. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2098

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Janakiraman, V. “Statistical Leakage Analysis Framework Using Artificial Neural Networks Considering Process And Environmental Variations.” 2011. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://hdl.handle.net/2005/2098.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Janakiraman, V. “Statistical Leakage Analysis Framework Using Artificial Neural Networks Considering Process And Environmental Variations.” 2011. Web. 08 Apr 2020.

Vancouver:

Janakiraman V. Statistical Leakage Analysis Framework Using Artificial Neural Networks Considering Process And Environmental Variations. [Internet] [Thesis]. Indian Institute of Science; 2011. [cited 2020 Apr 08]. Available from: http://hdl.handle.net/2005/2098.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Janakiraman V. Statistical Leakage Analysis Framework Using Artificial Neural Networks Considering Process And Environmental Variations. [Thesis]. Indian Institute of Science; 2011. Available from: http://hdl.handle.net/2005/2098

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

7. Siva Rama Krishna, V. Towards Development Of Low Cost Electrochemical Biosensor For Detecting Percentage Glycated Hemoglobin.

Degree: 2012, Indian Institute of Science

 There is an ever growing demand for low cost biosensors in medical diagnostics. A well known commercially successful example is glucose biosensors which are used… (more)

Subjects/Keywords: Medical Diagnostics; Electrochemical Diagnosis; Biosensors; Glycated Hemoglobin (GHb); Electrochemical Biosensors; Glycated Hemoglobin - Electrochemical Detection; Erythrocytes - Lysis; Glycated Hemoglobin - Biosensors; Glycated Hemoglobin Sensor; Pathology

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Siva Rama Krishna, V. (2012). Towards Development Of Low Cost Electrochemical Biosensor For Detecting Percentage Glycated Hemoglobin. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2340

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Siva Rama Krishna, V. “Towards Development Of Low Cost Electrochemical Biosensor For Detecting Percentage Glycated Hemoglobin.” 2012. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://hdl.handle.net/2005/2340.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Siva Rama Krishna, V. “Towards Development Of Low Cost Electrochemical Biosensor For Detecting Percentage Glycated Hemoglobin.” 2012. Web. 08 Apr 2020.

Vancouver:

Siva Rama Krishna V. Towards Development Of Low Cost Electrochemical Biosensor For Detecting Percentage Glycated Hemoglobin. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2020 Apr 08]. Available from: http://hdl.handle.net/2005/2340.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Siva Rama Krishna V. Towards Development Of Low Cost Electrochemical Biosensor For Detecting Percentage Glycated Hemoglobin. [Thesis]. Indian Institute of Science; 2012. Available from: http://hdl.handle.net/2005/2340

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

8. Gorur, Pushkar. Bitrate Reduction Techniques for Low-Complexity Surveillance Video Coding.

Degree: 2016, Indian Institute of Science

 High resolution surveillance video cameras are invaluable resources for effective crime prevention and forensic investigations. However, increasing communication bandwidth requirements of high definition surveillance videos… (more)

Subjects/Keywords: Bitrate Reduction; Surveillance Video Coding; Video Surveillance; Gaussian Mixture Model (GMM); Pedestrian Surveillance Cameras; Region of Interest (ROI) Video Coding; Surveillance Video Cameras; Video Coding; Encoding; Computational Complexity Reduction; H.264 Surveillance Coding; Gaussian Mixture Model Algorithm; Electrical Communication Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gorur, P. (2016). Bitrate Reduction Techniques for Low-Complexity Surveillance Video Coding. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2681

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gorur, Pushkar. “Bitrate Reduction Techniques for Low-Complexity Surveillance Video Coding.” 2016. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://hdl.handle.net/2005/2681.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gorur, Pushkar. “Bitrate Reduction Techniques for Low-Complexity Surveillance Video Coding.” 2016. Web. 08 Apr 2020.

Vancouver:

Gorur P. Bitrate Reduction Techniques for Low-Complexity Surveillance Video Coding. [Internet] [Thesis]. Indian Institute of Science; 2016. [cited 2020 Apr 08]. Available from: http://hdl.handle.net/2005/2681.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gorur P. Bitrate Reduction Techniques for Low-Complexity Surveillance Video Coding. [Thesis]. Indian Institute of Science; 2016. Available from: http://hdl.handle.net/2005/2681

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

9. Janakiraman, V. Statistical Leakage Analysis Framework Using Artificial Neural Networks Considering Process And Environmental Variations.

Degree: 2011, Indian Institute of Science

 Leakage current and process variations are two primary hurdles in modern VLSI design. It depends exponentially on process and environmental parameters and hence small variations… (more)

Subjects/Keywords: Neural Networks; Artificial Intelligence; Statistical Leakage Analysis (SLA); Leakage Modelling; Artificial Neural Network (ANN); Leakage Models; Statistical Leakage Characterization; Leakage Current; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Janakiraman, V. (2011). Statistical Leakage Analysis Framework Using Artificial Neural Networks Considering Process And Environmental Variations. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2098 ; http://etd.ncsi.iisc.ernet.in/abstracts/2699/G24437-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Janakiraman, V. “Statistical Leakage Analysis Framework Using Artificial Neural Networks Considering Process And Environmental Variations.” 2011. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://etd.iisc.ernet.in/handle/2005/2098 ; http://etd.ncsi.iisc.ernet.in/abstracts/2699/G24437-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Janakiraman, V. “Statistical Leakage Analysis Framework Using Artificial Neural Networks Considering Process And Environmental Variations.” 2011. Web. 08 Apr 2020.

Vancouver:

Janakiraman V. Statistical Leakage Analysis Framework Using Artificial Neural Networks Considering Process And Environmental Variations. [Internet] [Thesis]. Indian Institute of Science; 2011. [cited 2020 Apr 08]. Available from: http://etd.iisc.ernet.in/handle/2005/2098 ; http://etd.ncsi.iisc.ernet.in/abstracts/2699/G24437-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Janakiraman V. Statistical Leakage Analysis Framework Using Artificial Neural Networks Considering Process And Environmental Variations. [Thesis]. Indian Institute of Science; 2011. Available from: http://etd.iisc.ernet.in/handle/2005/2098 ; http://etd.ncsi.iisc.ernet.in/abstracts/2699/G24437-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

10. Siva Rama Krishna, V. Towards Development Of Low Cost Electrochemical Biosensor For Detecting Percentage Glycated Hemoglobin.

Degree: 2012, Indian Institute of Science

 There is an ever growing demand for low cost biosensors in medical diagnostics. A well known commercially successful example is glucose biosensors which are used… (more)

Subjects/Keywords: Medical Diagnostics; Electrochemical Diagnosis; Biosensors; Glycated Hemoglobin (GHb); Electrochemical Biosensors; Glycated Hemoglobin - Electrochemical Detection; Erythrocytes - Lysis; Glycated Hemoglobin - Biosensors; Glycated Hemoglobin Sensor; Pathology

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Siva Rama Krishna, V. (2012). Towards Development Of Low Cost Electrochemical Biosensor For Detecting Percentage Glycated Hemoglobin. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2340 ; http://etd.ncsi.iisc.ernet.in/abstracts/3010/G25329-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Siva Rama Krishna, V. “Towards Development Of Low Cost Electrochemical Biosensor For Detecting Percentage Glycated Hemoglobin.” 2012. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://etd.iisc.ernet.in/handle/2005/2340 ; http://etd.ncsi.iisc.ernet.in/abstracts/3010/G25329-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Siva Rama Krishna, V. “Towards Development Of Low Cost Electrochemical Biosensor For Detecting Percentage Glycated Hemoglobin.” 2012. Web. 08 Apr 2020.

Vancouver:

Siva Rama Krishna V. Towards Development Of Low Cost Electrochemical Biosensor For Detecting Percentage Glycated Hemoglobin. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2020 Apr 08]. Available from: http://etd.iisc.ernet.in/handle/2005/2340 ; http://etd.ncsi.iisc.ernet.in/abstracts/3010/G25329-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Siva Rama Krishna V. Towards Development Of Low Cost Electrochemical Biosensor For Detecting Percentage Glycated Hemoglobin. [Thesis]. Indian Institute of Science; 2012. Available from: http://etd.iisc.ernet.in/handle/2005/2340 ; http://etd.ncsi.iisc.ernet.in/abstracts/3010/G25329-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

11. Manikandan, R R. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.

Degree: 2015, Indian Institute of Science

 There has been a huge rise in interest in the design of energy efficient wireless sensor networks (WSN) and body area networks (BAN) with the… (more)

Subjects/Keywords: Transmitter Architecture; Radio Frequency (RF) Transmitter Circuits; Energy Efficient Wireless Transmitters; Wireless Sensor Networks; Phase-Locked Loop (PLL); Frequency Synthesizer Circuits; Wireless Communication; Charge Pump Phase-Locked Loop (CP-PLL); Analog Integrated Circuits; Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits; Charge Pump Circuits; Electronic Circuits; Spur Suppression Technique; Energy Efficient Transmitters; Communication Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Manikandan, R. R. (2015). Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2656 ; http://etd.ncsi.iisc.ernet.in/abstracts/3467/G26869-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Manikandan, R R. “Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.” 2015. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://etd.iisc.ernet.in/handle/2005/2656 ; http://etd.ncsi.iisc.ernet.in/abstracts/3467/G26869-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Manikandan, R R. “Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.” 2015. Web. 08 Apr 2020.

Vancouver:

Manikandan RR. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. [Internet] [Thesis]. Indian Institute of Science; 2015. [cited 2020 Apr 08]. Available from: http://etd.iisc.ernet.in/handle/2005/2656 ; http://etd.ncsi.iisc.ernet.in/abstracts/3467/G26869-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Manikandan RR. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. [Thesis]. Indian Institute of Science; 2015. Available from: http://etd.iisc.ernet.in/handle/2005/2656 ; http://etd.ncsi.iisc.ernet.in/abstracts/3467/G26869-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

12. Gorur, Pushkar. Bitrate Reduction Techniques for Low-Complexity Surveillance Video Coding.

Degree: 2016, Indian Institute of Science

 High resolution surveillance video cameras are invaluable resources for effective crime prevention and forensic investigations. However, increasing communication bandwidth requirements of high definition surveillance videos… (more)

Subjects/Keywords: Bitrate Reduction; Surveillance Video Coding; Video Surveillance; Gaussian Mixture Model (GMM); Pedestrian Surveillance Cameras; Region of Interest (ROI) Video Coding; Surveillance Video Cameras; Video Coding; Encoding; Computational Complexity Reduction; H.264 Surveillance Coding; Gaussian Mixture Model Algorithm; Electrical Communication Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gorur, P. (2016). Bitrate Reduction Techniques for Low-Complexity Surveillance Video Coding. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2681 ; http://etd.ncsi.iisc.ernet.in/abstracts/3502/G27564-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gorur, Pushkar. “Bitrate Reduction Techniques for Low-Complexity Surveillance Video Coding.” 2016. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://etd.iisc.ernet.in/handle/2005/2681 ; http://etd.ncsi.iisc.ernet.in/abstracts/3502/G27564-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gorur, Pushkar. “Bitrate Reduction Techniques for Low-Complexity Surveillance Video Coding.” 2016. Web. 08 Apr 2020.

Vancouver:

Gorur P. Bitrate Reduction Techniques for Low-Complexity Surveillance Video Coding. [Internet] [Thesis]. Indian Institute of Science; 2016. [cited 2020 Apr 08]. Available from: http://etd.iisc.ernet.in/handle/2005/2681 ; http://etd.ncsi.iisc.ernet.in/abstracts/3502/G27564-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gorur P. Bitrate Reduction Techniques for Low-Complexity Surveillance Video Coding. [Thesis]. Indian Institute of Science; 2016. Available from: http://etd.iisc.ernet.in/handle/2005/2681 ; http://etd.ncsi.iisc.ernet.in/abstracts/3502/G27564-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

13. Manikandan, R R. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.

Degree: 2015, Indian Institute of Science

 There has been a huge rise in interest in the design of energy efficient wireless sensor networks (WSN) and body area networks (BAN) with the… (more)

Subjects/Keywords: Transmitter Architecture; Radio Frequency (RF) Transmitter Circuits; Energy Efficient Wireless Transmitters; Wireless Sensor Networks; Phase-Locked Loop (PLL); Frequency Synthesizer Circuits; Wireless Communication; Charge Pump Phase-Locked Loop (CP-PLL); Analog Integrated Circuits; Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits; Charge Pump Circuits; Electronic Circuits; Spur Suppression Technique; Energy Efficient Transmitters; Communication Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Manikandan, R. R. (2015). Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2656

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Manikandan, R R. “Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.” 2015. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://hdl.handle.net/2005/2656.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Manikandan, R R. “Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.” 2015. Web. 08 Apr 2020.

Vancouver:

Manikandan RR. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. [Internet] [Thesis]. Indian Institute of Science; 2015. [cited 2020 Apr 08]. Available from: http://hdl.handle.net/2005/2656.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Manikandan RR. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. [Thesis]. Indian Institute of Science; 2015. Available from: http://hdl.handle.net/2005/2656

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

14. Chaturvedi, Vikram. Low Power and Low Area Techniques for Neural Recording Application.

Degree: 2012, Indian Institute of Science

 Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and to elucidate human neurophysiology. The advent of multi-channel micro-electrode arrays has… (more)

Subjects/Keywords: Neural Signal Processing; Nervous System - Electric Signals; Brain Machine Interface; Neural Recording System; Neural Recording Front End; Neural Low Noise Amplifiers; Successive Approximation Analog to Digital Converter; Neural Recording Application; Neural Recording Front End (NRFE).; FlipDAC; Quaternary Capacitor Switching; ANALOG-TO-DIGITAL Converter (ADC); SAR ADC Design; Neural Physiology

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chaturvedi, V. (2012). Low Power and Low Area Techniques for Neural Recording Application. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/3167

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chaturvedi, Vikram. “Low Power and Low Area Techniques for Neural Recording Application.” 2012. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://hdl.handle.net/2005/3167.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chaturvedi, Vikram. “Low Power and Low Area Techniques for Neural Recording Application.” 2012. Web. 08 Apr 2020.

Vancouver:

Chaturvedi V. Low Power and Low Area Techniques for Neural Recording Application. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2020 Apr 08]. Available from: http://hdl.handle.net/2005/3167.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chaturvedi V. Low Power and Low Area Techniques for Neural Recording Application. [Thesis]. Indian Institute of Science; 2012. Available from: http://hdl.handle.net/2005/3167

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

15. Ghosal, Kaushik. Power Scaling Mechanism for Low Power Wireless Receivers.

Degree: 2015, Indian Institute of Science

 LOW power operation for wireless radio receivers has been gaining importance lately on account of the recent spurt of growth in the usage of ubiquitous… (more)

Subjects/Keywords: Power Scalable Wireless Receivers; Low Power Wireless Receivers; Low Noise Amplifier (LNA); Wireless Radio Receivers; Power Scalable Receiver Architecture; Received Signal Quality Indicator; Power Scalabe Receiver Control Policy; Power Scaling Mechanism; Power Scalable Receiver; Power Scalable Receiver System; Variable Gain Amplifier (VGA); Power Scaling Methodology; Power-Scalable RF CMOS Receiver; Electrical Communicatin Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ghosal, K. (2015). Power Scaling Mechanism for Low Power Wireless Receivers. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3767 ; http://etd.iisc.ernet.in/abstracts/4638/G26966-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ghosal, Kaushik. “Power Scaling Mechanism for Low Power Wireless Receivers.” 2015. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://etd.iisc.ernet.in/2005/3767 ; http://etd.iisc.ernet.in/abstracts/4638/G26966-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ghosal, Kaushik. “Power Scaling Mechanism for Low Power Wireless Receivers.” 2015. Web. 08 Apr 2020.

Vancouver:

Ghosal K. Power Scaling Mechanism for Low Power Wireless Receivers. [Internet] [Thesis]. Indian Institute of Science; 2015. [cited 2020 Apr 08]. Available from: http://etd.iisc.ernet.in/2005/3767 ; http://etd.iisc.ernet.in/abstracts/4638/G26966-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ghosal K. Power Scaling Mechanism for Low Power Wireless Receivers. [Thesis]. Indian Institute of Science; 2015. Available from: http://etd.iisc.ernet.in/2005/3767 ; http://etd.iisc.ernet.in/abstracts/4638/G26966-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

16. Vasudevamurthy, Rajath. Time-based All-Digital Technique for Analog Built-in Self Test.

Degree: 2013, Indian Institute of Science

 A scheme for Built-in-Self-Test (BIST) of analog signals with minimal area overhead, for measuring on-chip voltages in an all-digital manner is presented in this thesis.… (more)

Subjects/Keywords: Electronic Circuits; On-Chip Analog Test Voltages; Electronic Circuit Design; Analog Circuits; Built-in Self Test (BIST); Time-to-Digital Converters; Analog Routing; Analog Built-in Self Test; Time Based Analog-to-Digital Converter; Analog-to-Digital Converters; Integrated Circuit; Analog IP Test; Electronic Engineering

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APA (6th Edition):

Vasudevamurthy, R. (2013). Time-based All-Digital Technique for Analog Built-in Self Test. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2841

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vasudevamurthy, Rajath. “Time-based All-Digital Technique for Analog Built-in Self Test.” 2013. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://hdl.handle.net/2005/2841.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vasudevamurthy, Rajath. “Time-based All-Digital Technique for Analog Built-in Self Test.” 2013. Web. 08 Apr 2020.

Vancouver:

Vasudevamurthy R. Time-based All-Digital Technique for Analog Built-in Self Test. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2020 Apr 08]. Available from: http://hdl.handle.net/2005/2841.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vasudevamurthy R. Time-based All-Digital Technique for Analog Built-in Self Test. [Thesis]. Indian Institute of Science; 2013. Available from: http://hdl.handle.net/2005/2841

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

17. Basavaraj, T. NoC Design & Optimization of Multicore Media Processors.

Degree: 2013, Indian Institute of Science

 Network on Chips[1][2][3][4] are critical elements of modern System on Chip(SoC) as well as Chip Multiprocessor(CMP)designs. Network on Chips (NoCs) help manage high complexity of… (more)

Subjects/Keywords: Network-On-Chip (NOC); Quality of Service (QOS); Label Switched Network On Chip (LS-NoC); Chip Multiprocessor Designs; Multicore Media Processors; Network-On-Chip (NOC) - Design and Construction; System on Chip (SoC); Link Microarchitectural Exploration, Network-on-Chip (NOC); Tile Exploration - Chip Multiprocessors (CMP); Ford-Fulkerson’s MaxFlow Algorithm; Flow Algorithm; Network-on-Chips; On-Chip Interconnection Networks; Microarchitecture Exploration; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Basavaraj, T. (2013). NoC Design & Optimization of Multicore Media Processors. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Basavaraj, T. “NoC Design & Optimization of Multicore Media Processors.” 2013. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Basavaraj, T. “NoC Design & Optimization of Multicore Media Processors.” 2013. Web. 08 Apr 2020.

Vancouver:

Basavaraj T. NoC Design & Optimization of Multicore Media Processors. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2020 Apr 08]. Available from: http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Basavaraj T. NoC Design & Optimization of Multicore Media Processors. [Thesis]. Indian Institute of Science; 2013. Available from: http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

18. Raghavan, Mohan. First-Spike-Latency Codes : Significance, Relation to Neuronal Network Structure and Application to Physiological Recordings.

Degree: 2013, Indian Institute of Science

 Over the last decade advances in multineuron simultaneous recording techniques have produced huge amounts of data. This has led to the investigation of probable temporal… (more)

Subjects/Keywords: Neuronal Network Structure; First-Spike-Latency Codes; Neuronal Network Structure - Spike Latency Codes; Spike Latency - Neuronal Networks; Spatio Temporal Spike Latency; Synconset Waves; Synconset Chains; Hippocampal Neuronal Cell Culture; Neurons - Mathematical Modelling; Neuronal Cell Culture; Electrophysiology - Spike Latency; Neural Networks; Neural Coding; Spiking Onsets; Epileptogenic Network Structures; Neuronal Networks; Neuroscience

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Raghavan, M. (2013). First-Spike-Latency Codes : Significance, Relation to Neuronal Network Structure and Application to Physiological Recordings. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3393 ; http://etd.iisc.ernet.in/abstracts/4259/G25855-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Raghavan, Mohan. “First-Spike-Latency Codes : Significance, Relation to Neuronal Network Structure and Application to Physiological Recordings.” 2013. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://etd.iisc.ernet.in/2005/3393 ; http://etd.iisc.ernet.in/abstracts/4259/G25855-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Raghavan, Mohan. “First-Spike-Latency Codes : Significance, Relation to Neuronal Network Structure and Application to Physiological Recordings.” 2013. Web. 08 Apr 2020.

Vancouver:

Raghavan M. First-Spike-Latency Codes : Significance, Relation to Neuronal Network Structure and Application to Physiological Recordings. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2020 Apr 08]. Available from: http://etd.iisc.ernet.in/2005/3393 ; http://etd.iisc.ernet.in/abstracts/4259/G25855-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Raghavan M. First-Spike-Latency Codes : Significance, Relation to Neuronal Network Structure and Application to Physiological Recordings. [Thesis]. Indian Institute of Science; 2013. Available from: http://etd.iisc.ernet.in/2005/3393 ; http://etd.iisc.ernet.in/abstracts/4259/G25855-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

19. Dwivedi, Satyam. Low Power Receiver Architecture And Algorithms For Low Data Rate Wireless Personal Area Networks.

Degree: 2010, Indian Institute of Science

 Sensor nodes in a sensor network is power constrained. Transceiver electronics of a node in sensor network consume a good share of total power consumed… (more)

Subjects/Keywords: Wireless Receiving Sets; Algorithms; Personal Receiving Sets; Wireless Personal Area Networks; Wireless Sensor Networks; Power Receiver Architecture; Power Scalable Receiver; IEEE 802.15.4; Low Power Radio Receiver; Low Power Receiver Architecture; Communication Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dwivedi, S. (2010). Low Power Receiver Architecture And Algorithms For Low Data Rate Wireless Personal Area Networks. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2228

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dwivedi, Satyam. “Low Power Receiver Architecture And Algorithms For Low Data Rate Wireless Personal Area Networks.” 2010. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://hdl.handle.net/2005/2228.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dwivedi, Satyam. “Low Power Receiver Architecture And Algorithms For Low Data Rate Wireless Personal Area Networks.” 2010. Web. 08 Apr 2020.

Vancouver:

Dwivedi S. Low Power Receiver Architecture And Algorithms For Low Data Rate Wireless Personal Area Networks. [Internet] [Thesis]. Indian Institute of Science; 2010. [cited 2020 Apr 08]. Available from: http://hdl.handle.net/2005/2228.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dwivedi S. Low Power Receiver Architecture And Algorithms For Low Data Rate Wireless Personal Area Networks. [Thesis]. Indian Institute of Science; 2010. Available from: http://hdl.handle.net/2005/2228

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

20. Dwivedi, Satyam. Low Power Receiver Architecture And Algorithms For Low Data Rate Wireless Personal Area Networks.

Degree: 2010, Indian Institute of Science

 Sensor nodes in a sensor network is power constrained. Transceiver electronics of a node in sensor network consume a good share of total power consumed… (more)

Subjects/Keywords: Wireless Receiving Sets; Algorithms; Personal Receiving Sets; Wireless Personal Area Networks; Wireless Sensor Networks; Power Receiver Architecture; Power Scalable Receiver; IEEE 802.15.4; Low Power Radio Receiver; Low Power Receiver Architecture; Communication Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dwivedi, S. (2010). Low Power Receiver Architecture And Algorithms For Low Data Rate Wireless Personal Area Networks. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2228 ; http://etd.ncsi.iisc.ernet.in/abstracts/2841/G24790-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dwivedi, Satyam. “Low Power Receiver Architecture And Algorithms For Low Data Rate Wireless Personal Area Networks.” 2010. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://etd.iisc.ernet.in/handle/2005/2228 ; http://etd.ncsi.iisc.ernet.in/abstracts/2841/G24790-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dwivedi, Satyam. “Low Power Receiver Architecture And Algorithms For Low Data Rate Wireless Personal Area Networks.” 2010. Web. 08 Apr 2020.

Vancouver:

Dwivedi S. Low Power Receiver Architecture And Algorithms For Low Data Rate Wireless Personal Area Networks. [Internet] [Thesis]. Indian Institute of Science; 2010. [cited 2020 Apr 08]. Available from: http://etd.iisc.ernet.in/handle/2005/2228 ; http://etd.ncsi.iisc.ernet.in/abstracts/2841/G24790-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dwivedi S. Low Power Receiver Architecture And Algorithms For Low Data Rate Wireless Personal Area Networks. [Thesis]. Indian Institute of Science; 2010. Available from: http://etd.iisc.ernet.in/handle/2005/2228 ; http://etd.ncsi.iisc.ernet.in/abstracts/2841/G24790-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

21. Mandke, Aparna. Power Efficient Last Level Cache for Chip Multiprocessors.

Degree: 2013, Indian Institute of Science

 The number of processor cores and on-chip cache size has been increasing on chip multiprocessors (CMPs). As a result, leakage power dissipated in the on-chip… (more)

Subjects/Keywords: Processor Architecture; Chip Multiprocessor; Cache Memory; Cache; Genetic Algorithms; Leakage Power Optimization; Working Set Size Optimization; Near Optimal Remap Configuration; Thread Contention Predictors; On-Chip Cache; Cache Architecture; NUCA; SNUCA; Non-Uniform Cache Architecture; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mandke, A. (2013). Power Efficient Last Level Cache for Chip Multiprocessors. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2802

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mandke, Aparna. “Power Efficient Last Level Cache for Chip Multiprocessors.” 2013. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://hdl.handle.net/2005/2802.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mandke, Aparna. “Power Efficient Last Level Cache for Chip Multiprocessors.” 2013. Web. 08 Apr 2020.

Vancouver:

Mandke A. Power Efficient Last Level Cache for Chip Multiprocessors. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2020 Apr 08]. Available from: http://hdl.handle.net/2005/2802.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mandke A. Power Efficient Last Level Cache for Chip Multiprocessors. [Thesis]. Indian Institute of Science; 2013. Available from: http://hdl.handle.net/2005/2802

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

22. Mandke, Aparna. Power Efficient Last Level Cache for Chip Multiprocessors.

Degree: 2013, Indian Institute of Science

 The number of processor cores and on-chip cache size has been increasing on chip multiprocessors (CMPs). As a result, leakage power dissipated in the on-chip… (more)

Subjects/Keywords: Processor Architecture; Chip Multiprocessor; Cache Memory; Cache; Genetic Algorithms; Leakage Power Optimization; Working Set Size Optimization; Near Optimal Remap Configuration; Thread Contention Predictors; On-Chip Cache; Cache Architecture; NUCA; SNUCA; Non-Uniform Cache Architecture; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mandke, A. (2013). Power Efficient Last Level Cache for Chip Multiprocessors. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2802 ; http://etd.ncsi.iisc.ernet.in/abstracts/3574/G25417-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mandke, Aparna. “Power Efficient Last Level Cache for Chip Multiprocessors.” 2013. Thesis, Indian Institute of Science. Accessed April 08, 2020. http://etd.iisc.ernet.in/handle/2005/2802 ; http://etd.ncsi.iisc.ernet.in/abstracts/3574/G25417-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mandke, Aparna. “Power Efficient Last Level Cache for Chip Multiprocessors.” 2013. Web. 08 Apr 2020.

Vancouver:

Mandke A. Power Efficient Last Level Cache for Chip Multiprocessors. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2020 Apr 08]. Available from: http://etd.iisc.ernet.in/handle/2005/2802 ; http://etd.ncsi.iisc.ernet.in/abstracts/3574/G25417-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mandke A. Power Efficient Last Level Cache for Chip Multiprocessors. [Thesis]. Indian Institute of Science; 2013. Available from: http://etd.iisc.ernet.in/handle/2005/2802 ; http://etd.ncsi.iisc.ernet.in/abstracts/3574/G25417-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.