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You searched for +publisher:"Georgia Tech" +contributor:("Yalamanchili, Sudhakar"). Showing records 1 – 30 of 123 total matches.

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Georgia Tech

1. Gupta, Meghana. Code generation and adaptive control divergence management for light weight SIMT processors.

Degree: MS, Computer Science, 2016, Georgia Tech

 The energy costs of data movement are limiting the performance scaling of future generations of high performance computing architectures targeted to data intensive applications. The… (more)

Subjects/Keywords: Compiler; SIMT; Control divergence

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APA (6th Edition):

Gupta, M. (2016). Code generation and adaptive control divergence management for light weight SIMT processors. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55044

Chicago Manual of Style (16th Edition):

Gupta, Meghana. “Code generation and adaptive control divergence management for light weight SIMT processors.” 2016. Masters Thesis, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/55044.

MLA Handbook (7th Edition):

Gupta, Meghana. “Code generation and adaptive control divergence management for light weight SIMT processors.” 2016. Web. 22 Sep 2019.

Vancouver:

Gupta M. Code generation and adaptive control divergence management for light weight SIMT processors. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/55044.

Council of Science Editors:

Gupta M. Code generation and adaptive control divergence management for light weight SIMT processors. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55044


Georgia Tech

2. VanDerheyden, Andrew Louis. Characterization of thermal coupling in chip multiprocessors.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 For semiconductor processors temperature increases leakage current, which in turn in- creases the temperature of the processor. This increase in heat is seen by other… (more)

Subjects/Keywords: Thermal management; Thermal characterization; Thermal coupling; High performance processors; Thermal analysis

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APA (6th Edition):

VanDerheyden, A. L. (2014). Characterization of thermal coupling in chip multiprocessors. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51892

Chicago Manual of Style (16th Edition):

VanDerheyden, Andrew Louis. “Characterization of thermal coupling in chip multiprocessors.” 2014. Masters Thesis, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/51892.

MLA Handbook (7th Edition):

VanDerheyden, Andrew Louis. “Characterization of thermal coupling in chip multiprocessors.” 2014. Web. 22 Sep 2019.

Vancouver:

VanDerheyden AL. Characterization of thermal coupling in chip multiprocessors. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/51892.

Council of Science Editors:

VanDerheyden AL. Characterization of thermal coupling in chip multiprocessors. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51892


Georgia Tech

3. Young, Vinson. Hardware-assisted security: bloom cache – scalable low-overhead control flow integrity checking.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 Computers were not built with security in mind. As such, security has and still often takes a back seat to performance. However, in an era… (more)

Subjects/Keywords: Security; Bloom filter; Control flow hijacking; Memory; Control flow integrity

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APA (6th Edition):

Young, V. (2014). Hardware-assisted security: bloom cache – scalable low-overhead control flow integrity checking. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53994

Chicago Manual of Style (16th Edition):

Young, Vinson. “Hardware-assisted security: bloom cache – scalable low-overhead control flow integrity checking.” 2014. Masters Thesis, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/53994.

MLA Handbook (7th Edition):

Young, Vinson. “Hardware-assisted security: bloom cache – scalable low-overhead control flow integrity checking.” 2014. Web. 22 Sep 2019.

Vancouver:

Young V. Hardware-assisted security: bloom cache – scalable low-overhead control flow integrity checking. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/53994.

Council of Science Editors:

Young V. Hardware-assisted security: bloom cache – scalable low-overhead control flow integrity checking. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/53994


Georgia Tech

4. Bharadwaj, Vedula Venkata. Scaling address translation in multi-core architectures using low-latency interconnects.

Degree: MS, Electrical and Computer Engineering, 2017, Georgia Tech

 Modern systems employ structures known as Translation Lookaside Buffers(TLB) to accelerate the address translation mechanism. As workloads use ever-increasing memory footprints, TLBs are becoming critical… (more)

Subjects/Keywords: TLB; NUTRA; SMART; Interconnect; Distributed; NUCA

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APA (6th Edition):

Bharadwaj, V. V. (2017). Scaling address translation in multi-core architectures using low-latency interconnects. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59300

Chicago Manual of Style (16th Edition):

Bharadwaj, Vedula Venkata. “Scaling address translation in multi-core architectures using low-latency interconnects.” 2017. Masters Thesis, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/59300.

MLA Handbook (7th Edition):

Bharadwaj, Vedula Venkata. “Scaling address translation in multi-core architectures using low-latency interconnects.” 2017. Web. 22 Sep 2019.

Vancouver:

Bharadwaj VV. Scaling address translation in multi-core architectures using low-latency interconnects. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/59300.

Council of Science Editors:

Bharadwaj VV. Scaling address translation in multi-core architectures using low-latency interconnects. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59300


Georgia Tech

5. Saeed, Ifrah. A portable relational algebra library for high performance data-intensive query processing.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 A growing number of industries are turning to data warehousing applications such as forecasting and risk assessment to process large volumes of data. These data… (more)

Subjects/Keywords: Data-intensive query processing; RA operators; OpenCL; GPUs; CPUs; Graphics processing units; Data warehousing; Big data; Relation algebras

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APA (6th Edition):

Saeed, I. (2014). A portable relational algebra library for high performance data-intensive query processing. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51967

Chicago Manual of Style (16th Edition):

Saeed, Ifrah. “A portable relational algebra library for high performance data-intensive query processing.” 2014. Masters Thesis, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/51967.

MLA Handbook (7th Edition):

Saeed, Ifrah. “A portable relational algebra library for high performance data-intensive query processing.” 2014. Web. 22 Sep 2019.

Vancouver:

Saeed I. A portable relational algebra library for high performance data-intensive query processing. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/51967.

Council of Science Editors:

Saeed I. A portable relational algebra library for high performance data-intensive query processing. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51967


Georgia Tech

6. Carlo, Sergio. Load-Aware Power Conversion and Integration for Heterogeneous Systems.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 In this thesis we develop a holistic co-design approach to optimize the conversion systems in order to perform relevant trade-offs taking into account system-level converter,… (more)

Subjects/Keywords: Power conversion 3D single inductor multiple output SIMO control design power management

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APA (6th Edition):

Carlo, S. (2015). Load-Aware Power Conversion and Integration for Heterogeneous Systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56182

Chicago Manual of Style (16th Edition):

Carlo, Sergio. “Load-Aware Power Conversion and Integration for Heterogeneous Systems.” 2015. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/56182.

MLA Handbook (7th Edition):

Carlo, Sergio. “Load-Aware Power Conversion and Integration for Heterogeneous Systems.” 2015. Web. 22 Sep 2019.

Vancouver:

Carlo S. Load-Aware Power Conversion and Integration for Heterogeneous Systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/56182.

Council of Science Editors:

Carlo S. Load-Aware Power Conversion and Integration for Heterogeneous Systems. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56182


Georgia Tech

7. Balakrishnan, Anant. Analysis and optimization of global interconnects for many-core architectures.

Degree: MS, Electrical and Computer Engineering, 2010, Georgia Tech

 The objective of this thesis is to develop circuit-aware interconnect technology optimization for network-on-chip based many-core architectures. The dimensions of global interconnects in many-core chips… (more)

Subjects/Keywords: Circuit optimization; Routing; Delay estimation; Multiprocessor interconnections; Networks on a chip; Moore's law; Semiconductors

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APA (6th Edition):

Balakrishnan, A. (2010). Analysis and optimization of global interconnects for many-core architectures. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/39632

Chicago Manual of Style (16th Edition):

Balakrishnan, Anant. “Analysis and optimization of global interconnects for many-core architectures.” 2010. Masters Thesis, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/39632.

MLA Handbook (7th Edition):

Balakrishnan, Anant. “Analysis and optimization of global interconnects for many-core architectures.” 2010. Web. 22 Sep 2019.

Vancouver:

Balakrishnan A. Analysis and optimization of global interconnects for many-core architectures. [Internet] [Masters thesis]. Georgia Tech; 2010. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/39632.

Council of Science Editors:

Balakrishnan A. Analysis and optimization of global interconnects for many-core architectures. [Masters Thesis]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/39632


Georgia Tech

8. Na, Taesik. Energy efficient, secure and noise robust deep learning for the internet of things.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The objective of this research is to design an energy efficient, secure and noise robust deep learning system for the Internet of Things (IoTs). The… (more)

Subjects/Keywords: Deep learning; Adversarial machine learning; Energy efficient training; Noise robust machine learning; IoT

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APA (6th Edition):

Na, T. (2018). Energy efficient, secure and noise robust deep learning for the internet of things. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60293

Chicago Manual of Style (16th Edition):

Na, Taesik. “Energy efficient, secure and noise robust deep learning for the internet of things.” 2018. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/60293.

MLA Handbook (7th Edition):

Na, Taesik. “Energy efficient, secure and noise robust deep learning for the internet of things.” 2018. Web. 22 Sep 2019.

Vancouver:

Na T. Energy efficient, secure and noise robust deep learning for the internet of things. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/60293.

Council of Science Editors:

Na T. Energy efficient, secure and noise robust deep learning for the internet of things. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60293


Georgia Tech

9. Ko, Jong Hwan. Resource-aware and robust image processing for intelligent sensor systems.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The objective of this research is to design resource-aware and robust image processing algorithms, system architecture, and hardware implementation for intelligent image sensor systems in… (more)

Subjects/Keywords: Image processing; Deep learning; Sensor systems

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APA (6th Edition):

Ko, J. H. (2018). Resource-aware and robust image processing for intelligent sensor systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60198

Chicago Manual of Style (16th Edition):

Ko, Jong Hwan. “Resource-aware and robust image processing for intelligent sensor systems.” 2018. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/60198.

MLA Handbook (7th Edition):

Ko, Jong Hwan. “Resource-aware and robust image processing for intelligent sensor systems.” 2018. Web. 22 Sep 2019.

Vancouver:

Ko JH. Resource-aware and robust image processing for intelligent sensor systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/60198.

Council of Science Editors:

Ko JH. Resource-aware and robust image processing for intelligent sensor systems. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60198


Georgia Tech

10. Hassan, Syed Minhaj. Exploiting on-chip memory concurrency in 3d manycore architectures.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The objective of this thesis is to optimize the uncore of 3D many-core architectures. More specifically, we note that technology trends point to large increases… (more)

Subjects/Keywords: 3D memory systems; Network-on-chip; 3D system thermal analysis; Memory-level parallelism; DRAM

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APA (6th Edition):

Hassan, S. M. (2016). Exploiting on-chip memory concurrency in 3d manycore architectures. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56251

Chicago Manual of Style (16th Edition):

Hassan, Syed Minhaj. “Exploiting on-chip memory concurrency in 3d manycore architectures.” 2016. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/56251.

MLA Handbook (7th Edition):

Hassan, Syed Minhaj. “Exploiting on-chip memory concurrency in 3d manycore architectures.” 2016. Web. 22 Sep 2019.

Vancouver:

Hassan SM. Exploiting on-chip memory concurrency in 3d manycore architectures. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/56251.

Council of Science Editors:

Hassan SM. Exploiting on-chip memory concurrency in 3d manycore architectures. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56251


Georgia Tech

11. Farooqui, Naila. Runtime specialization for heterogeneous CPU-GPU platforms.

Degree: PhD, Computer Science, 2015, Georgia Tech

 Heterogeneous parallel architectures like those comprised of CPUs and GPUs are a tantalizing compute fabric for performance-hungry developers. While these platforms enable order-of-magnitude performance increases… (more)

Subjects/Keywords: Dynamic instrumentation; Dynamic compilation; GPU computing; Heterogeneous computing; Profile-guided optimizations; Program analysis; Workload characterization; Compiler; Runtime; Multicore; CUDA; OpenCL; SIMD

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APA (6th Edition):

Farooqui, N. (2015). Runtime specialization for heterogeneous CPU-GPU platforms. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54915

Chicago Manual of Style (16th Edition):

Farooqui, Naila. “Runtime specialization for heterogeneous CPU-GPU platforms.” 2015. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/54915.

MLA Handbook (7th Edition):

Farooqui, Naila. “Runtime specialization for heterogeneous CPU-GPU platforms.” 2015. Web. 22 Sep 2019.

Vancouver:

Farooqui N. Runtime specialization for heterogeneous CPU-GPU platforms. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/54915.

Council of Science Editors:

Farooqui N. Runtime specialization for heterogeneous CPU-GPU platforms. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/54915


Georgia Tech

12. Dong, Zhenjiang. Optimizing parallel simulation of multi-core system.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 Multi-core design for CPU is the recent trend and we believe the trend will continue in near future. Researchers and industry architects utilize simulation to… (more)

Subjects/Keywords: Parallel simulation; Multicore-system

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APA (6th Edition):

Dong, Z. (2015). Optimizing parallel simulation of multi-core system. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54920

Chicago Manual of Style (16th Edition):

Dong, Zhenjiang. “Optimizing parallel simulation of multi-core system.” 2015. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/54920.

MLA Handbook (7th Edition):

Dong, Zhenjiang. “Optimizing parallel simulation of multi-core system.” 2015. Web. 22 Sep 2019.

Vancouver:

Dong Z. Optimizing parallel simulation of multi-core system. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/54920.

Council of Science Editors:

Dong Z. Optimizing parallel simulation of multi-core system. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/54920


Georgia Tech

13. Kumar, Tushar. Characterizing and controlling program behavior using execution-time variance.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 Immersive applications, such as computer gaming, computer vision and video codecs, are an important emerging class of applications with QoS requirements that are difficult to… (more)

Subjects/Keywords: Profiling; QoS tuning; Adaptive control; Optimal control; Gain scheduling; LQR; Machine learning; System identification; Parameter estimation; Online training; Multimedia; Video; Gaming; Computer vision; Statistical analysis; Best effort; Probabilistic; Program analysis; Linear fit; Dynamic tuning

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APA (6th Edition):

Kumar, T. (2016). Characterizing and controlling program behavior using execution-time variance. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55000

Chicago Manual of Style (16th Edition):

Kumar, Tushar. “Characterizing and controlling program behavior using execution-time variance.” 2016. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/55000.

MLA Handbook (7th Edition):

Kumar, Tushar. “Characterizing and controlling program behavior using execution-time variance.” 2016. Web. 22 Sep 2019.

Vancouver:

Kumar T. Characterizing and controlling program behavior using execution-time variance. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/55000.

Council of Science Editors:

Kumar T. Characterizing and controlling program behavior using execution-time variance. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55000


Georgia Tech

14. Wan, Zhimin. Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling.

Degree: PhD, Mechanical Engineering, 2016, Georgia Tech

 Microfluidic convection cooling is a promising technique for future high power microprocessors, radio-frequency (RF) transceivers, solid-state lasers, and light emitting diodes (LED). Three-dimensional (3D) stacking… (more)

Subjects/Keywords: Microfluidic cooling; Pin fin; 3D ICs; Microfabrication; Flow boiling

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APA (6th Edition):

Wan, Z. (2016). Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55480

Chicago Manual of Style (16th Edition):

Wan, Zhimin. “Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling.” 2016. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/55480.

MLA Handbook (7th Edition):

Wan, Zhimin. “Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling.” 2016. Web. 22 Sep 2019.

Vancouver:

Wan Z. Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/55480.

Council of Science Editors:

Wan Z. Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55480


Georgia Tech

15. Chae, Kwanyeob. Design methodologies for robust low-power digital systems under static and dynamic variations.

Degree: PhD, Electrical and Computer Engineering, 2013, Georgia Tech

 Variability affects the performance and power of a circuit. Along with static variations, dynamic variations, which occur during chip operation, necessitate a safety margin. The… (more)

Subjects/Keywords: Adaptive circuit; Resilient design; Static variation; Dynamic variation; Error prevention

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APA (6th Edition):

Chae, K. (2013). Design methodologies for robust low-power digital systems under static and dynamic variations. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52174

Chicago Manual of Style (16th Edition):

Chae, Kwanyeob. “Design methodologies for robust low-power digital systems under static and dynamic variations.” 2013. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/52174.

MLA Handbook (7th Edition):

Chae, Kwanyeob. “Design methodologies for robust low-power digital systems under static and dynamic variations.” 2013. Web. 22 Sep 2019.

Vancouver:

Chae K. Design methodologies for robust low-power digital systems under static and dynamic variations. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/52174.

Council of Science Editors:

Chae K. Design methodologies for robust low-power digital systems under static and dynamic variations. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/52174


Georgia Tech

16. Ahmed, Safayet N. Adaptive CPU-budget allocation for soft-real-time applications.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 The focus of this dissertation is adaptive CPU-budget allocation for periodic soft-real-time applications. The presented algorithms are developed in the context of a power-management framework.… (more)

Subjects/Keywords: Real-time; Soft real time; CPU scheduling; Prediction; Power management

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APA (6th Edition):

Ahmed, S. N. (2014). Adaptive CPU-budget allocation for soft-real-time applications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52215

Chicago Manual of Style (16th Edition):

Ahmed, Safayet N. “Adaptive CPU-budget allocation for soft-real-time applications.” 2014. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/52215.

MLA Handbook (7th Edition):

Ahmed, Safayet N. “Adaptive CPU-budget allocation for soft-real-time applications.” 2014. Web. 22 Sep 2019.

Vancouver:

Ahmed SN. Adaptive CPU-budget allocation for soft-real-time applications. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/52215.

Council of Science Editors:

Ahmed SN. Adaptive CPU-budget allocation for soft-real-time applications. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/52215


Georgia Tech

17. Ravichandran, Kaushik. Programming frameworks for performance driven speculative parallelization.

Degree: PhD, Computer Science, 2014, Georgia Tech

 Effectively utilizing available parallelism is becoming harder and harder as systems evolve to many-core processors with many tens of cores per chip. Automatically extracting parallelism… (more)

Subjects/Keywords: Speculation; Transactional memory

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APA (6th Edition):

Ravichandran, K. (2014). Programming frameworks for performance driven speculative parallelization. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52985

Chicago Manual of Style (16th Edition):

Ravichandran, Kaushik. “Programming frameworks for performance driven speculative parallelization.” 2014. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/52985.

MLA Handbook (7th Edition):

Ravichandran, Kaushik. “Programming frameworks for performance driven speculative parallelization.” 2014. Web. 22 Sep 2019.

Vancouver:

Ravichandran K. Programming frameworks for performance driven speculative parallelization. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/52985.

Council of Science Editors:

Ravichandran K. Programming frameworks for performance driven speculative parallelization. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/52985


Georgia Tech

18. Roy, Indranil. Algorithmic techniques for the micron automata processor.

Degree: PhD, Computational Science and Engineering, 2015, Georgia Tech

 Our research is the first in-depth study in the use of the Micron Automata Processor, a novel re-configurable streaming co-processor which is purpose-built to execute… (more)

Subjects/Keywords: Automata processing; Bioinformatics; High performance algorithm design

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APA (6th Edition):

Roy, I. (2015). Algorithmic techniques for the micron automata processor. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53845

Chicago Manual of Style (16th Edition):

Roy, Indranil. “Algorithmic techniques for the micron automata processor.” 2015. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/53845.

MLA Handbook (7th Edition):

Roy, Indranil. “Algorithmic techniques for the micron automata processor.” 2015. Web. 22 Sep 2019.

Vancouver:

Roy I. Algorithmic techniques for the micron automata processor. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/53845.

Council of Science Editors:

Roy I. Algorithmic techniques for the micron automata processor. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53845


Georgia Tech

19. Natarajan, Jayaram. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 One of the challenges faced today in the design of microprocessors is to obtain power, performance scalability and reliability at the same time with technology… (more)

Subjects/Keywords: Microprocessor; Low power; Process variation; Timing variation tolerant; Timing margins; Better than worse-case design; Error resilient pipeline; Reliability

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APA (6th Edition):

Natarajan, J. (2016). Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55577

Chicago Manual of Style (16th Edition):

Natarajan, Jayaram. “Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.” 2016. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/55577.

MLA Handbook (7th Edition):

Natarajan, Jayaram. “Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.” 2016. Web. 22 Sep 2019.

Vancouver:

Natarajan J. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/55577.

Council of Science Editors:

Natarajan J. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55577


Georgia Tech

20. Lee, Sangho. Mitigating the performance impact of memory bloat.

Degree: PhD, Computer Science, 2015, Georgia Tech

 Memory bloat is loosely defined as an excessive memory usage by an application during its execution. Due to the complexity of efficient memory management that… (more)

Subjects/Keywords: Memory bloat; optimization

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APA (6th Edition):

Lee, S. (2015). Mitigating the performance impact of memory bloat. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56174

Chicago Manual of Style (16th Edition):

Lee, Sangho. “Mitigating the performance impact of memory bloat.” 2015. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/56174.

MLA Handbook (7th Edition):

Lee, Sangho. “Mitigating the performance impact of memory bloat.” 2015. Web. 22 Sep 2019.

Vancouver:

Lee S. Mitigating the performance impact of memory bloat. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/56174.

Council of Science Editors:

Lee S. Mitigating the performance impact of memory bloat. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56174


Georgia Tech

21. Song, Taigon. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The objective of this research is to study and develop computer-aided-design (CAD) methodologies for reliability in chip-package co-designed three-dimensional integrated circuit (3D IC) systems. 3D… (more)

Subjects/Keywords: 3D IC; Design Methodologies

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APA (6th Edition):

Song, T. (2015). CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56188

Chicago Manual of Style (16th Edition):

Song, Taigon. “CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.” 2015. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/56188.

MLA Handbook (7th Edition):

Song, Taigon. “CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.” 2015. Web. 22 Sep 2019.

Vancouver:

Song T. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/56188.

Council of Science Editors:

Song T. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56188


Georgia Tech

22. Wang, Jin. Acceleration and optimization of dynamic parallelism for irregular applications on GPUs.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The objective of this thesis is the development, implementation and optimization of a GPU execution model extension that efficiently supports time-varying, nested, fine-grained dynamic parallelism… (more)

Subjects/Keywords: General-purpose GPU; Dynamic parallelism; Irregular applications

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APA (6th Edition):

Wang, J. (2016). Acceleration and optimization of dynamic parallelism for irregular applications on GPUs. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56294

Chicago Manual of Style (16th Edition):

Wang, Jin. “Acceleration and optimization of dynamic parallelism for irregular applications on GPUs.” 2016. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/56294.

MLA Handbook (7th Edition):

Wang, Jin. “Acceleration and optimization of dynamic parallelism for irregular applications on GPUs.” 2016. Web. 22 Sep 2019.

Vancouver:

Wang J. Acceleration and optimization of dynamic parallelism for irregular applications on GPUs. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/56294.

Council of Science Editors:

Wang J. Acceleration and optimization of dynamic parallelism for irregular applications on GPUs. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56294


Georgia Tech

23. Ghosh, Mrinmoy. Microarchitectural techniques to reduce energy consumption in the memory hierarchy.

Degree: PhD, Electrical and Computer Engineering, 2009, Georgia Tech

 This thesis states that dynamic profiling of the memory reference stream can improve energy and performance in the memory hierarchy. The research presented in this… (more)

Subjects/Keywords: Energy; Cache; Dram; Microarchitecture; Memory management (Computer science) Power supply; Computer architecture

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APA (6th Edition):

Ghosh, M. (2009). Microarchitectural techniques to reduce energy consumption in the memory hierarchy. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/28265

Chicago Manual of Style (16th Edition):

Ghosh, Mrinmoy. “Microarchitectural techniques to reduce energy consumption in the memory hierarchy.” 2009. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/28265.

MLA Handbook (7th Edition):

Ghosh, Mrinmoy. “Microarchitectural techniques to reduce energy consumption in the memory hierarchy.” 2009. Web. 22 Sep 2019.

Vancouver:

Ghosh M. Microarchitectural techniques to reduce energy consumption in the memory hierarchy. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/28265.

Council of Science Editors:

Ghosh M. Microarchitectural techniques to reduce energy consumption in the memory hierarchy. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/28265


Georgia Tech

24. Kim, Pilho. E-model: event-based graph data model theory and implementation.

Degree: PhD, Electrical and Computer Engineering, 2009, Georgia Tech

 The necessity of managing disparate data models is increasing within all IT areas. Emerging hybrid relational-XML systems are under development in this context to support… (more)

Subjects/Keywords: Database architectures; Multimedia databases; Modeling structured; Textual and multimedia data; Graphs and networks; Linked representations; Modeling and management; Data models; Database models; Schema and subschema; Data translation; Database design; Data structures (Computer science); Databases; Multimedia systems; Application program interfaces (Computer software)

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APA (6th Edition):

Kim, P. (2009). E-model: event-based graph data model theory and implementation. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/29608

Chicago Manual of Style (16th Edition):

Kim, Pilho. “E-model: event-based graph data model theory and implementation.” 2009. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/29608.

MLA Handbook (7th Edition):

Kim, Pilho. “E-model: event-based graph data model theory and implementation.” 2009. Web. 22 Sep 2019.

Vancouver:

Kim P. E-model: event-based graph data model theory and implementation. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/29608.

Council of Science Editors:

Kim P. E-model: event-based graph data model theory and implementation. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/29608


Georgia Tech

25. Woo, Dong Hyuk. Designing heterogeneous many-core processors to provide high performance under limited chip power budget.

Degree: PhD, Electrical and Computer Engineering, 2010, Georgia Tech

 This thesis describes the efficient design of a future many-core processor that can provide higher performance under the limited chip power budget. To achieve such… (more)

Subjects/Keywords: Heterogeneous many-core architecture; Heterogeneous computing; Parallel processing (Electronic computers); Multiprocessors; Microprocessors; High performance processors

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APA (6th Edition):

Woo, D. H. (2010). Designing heterogeneous many-core processors to provide high performance under limited chip power budget. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/37294

Chicago Manual of Style (16th Edition):

Woo, Dong Hyuk. “Designing heterogeneous many-core processors to provide high performance under limited chip power budget.” 2010. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/37294.

MLA Handbook (7th Edition):

Woo, Dong Hyuk. “Designing heterogeneous many-core processors to provide high performance under limited chip power budget.” 2010. Web. 22 Sep 2019.

Vancouver:

Woo DH. Designing heterogeneous many-core processors to provide high performance under limited chip power budget. [Internet] [Doctoral dissertation]. Georgia Tech; 2010. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/37294.

Council of Science Editors:

Woo DH. Designing heterogeneous many-core processors to provide high performance under limited chip power budget. [Doctoral Dissertation]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/37294


Georgia Tech

26. Kani, Nickvash. Modeling of magnetization dynamics and applications to spin-based logic and memory devices.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 The objective of this research is to develop models to better evaluate the performance and reliability of proposed spin-based boolean devices. This research will focus… (more)

Subjects/Keywords: Nanomagnet; Dipolar coupling; Spin-transfer torque; Magnetic tunnel junction; Spin-switch; Spintronics; Straintronics; Magnetization dynamics

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APA (6th Edition):

Kani, N. (2017). Modeling of magnetization dynamics and applications to spin-based logic and memory devices. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59242

Chicago Manual of Style (16th Edition):

Kani, Nickvash. “Modeling of magnetization dynamics and applications to spin-based logic and memory devices.” 2017. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/59242.

MLA Handbook (7th Edition):

Kani, Nickvash. “Modeling of magnetization dynamics and applications to spin-based logic and memory devices.” 2017. Web. 22 Sep 2019.

Vancouver:

Kani N. Modeling of magnetization dynamics and applications to spin-based logic and memory devices. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/59242.

Council of Science Editors:

Kani N. Modeling of magnetization dynamics and applications to spin-based logic and memory devices. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59242


Georgia Tech

27. Kim, Duckhwan. Neurocube: Energy-efficient programmable digital deep learning accelerator based on processor in memory platform.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 Deep learning, machine learning algorithm based on artificial neural network, shows great success in numerous pattern recognition problems, such as image recognition or speech recognition.… (more)

Subjects/Keywords: Deep learning; Deep learning accelerator; Processor in memory; Near memory process

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APA (6th Edition):

Kim, D. (2017). Neurocube: Energy-efficient programmable digital deep learning accelerator based on processor in memory platform. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60660

Chicago Manual of Style (16th Edition):

Kim, Duckhwan. “Neurocube: Energy-efficient programmable digital deep learning accelerator based on processor in memory platform.” 2017. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/60660.

MLA Handbook (7th Edition):

Kim, Duckhwan. “Neurocube: Energy-efficient programmable digital deep learning accelerator based on processor in memory platform.” 2017. Web. 22 Sep 2019.

Vancouver:

Kim D. Neurocube: Energy-efficient programmable digital deep learning accelerator based on processor in memory platform. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/60660.

Council of Science Editors:

Kim D. Neurocube: Energy-efficient programmable digital deep learning accelerator based on processor in memory platform. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/60660


Georgia Tech

28. Yazdan Bakhsh, Amir. Neuro-general computing an acceleration-approximation approach.

Degree: PhD, Computer Science, 2018, Georgia Tech

 A growing number of commercial and enterprise systems rely on compute and power intensive tasks. While the demand of these tasks is growing, the performance… (more)

Subjects/Keywords: Approximate computing; Machine learning; Generative adversarial networks; Convolutional neural networks; CNN; Transposed convolution; Access-execute architecture; GAN; DNN; MIMD; SIMD; Accelerator

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APA (6th Edition):

Yazdan Bakhsh, A. (2018). Neuro-general computing an acceleration-approximation approach. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60224

Chicago Manual of Style (16th Edition):

Yazdan Bakhsh, Amir. “Neuro-general computing an acceleration-approximation approach.” 2018. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/60224.

MLA Handbook (7th Edition):

Yazdan Bakhsh, Amir. “Neuro-general computing an acceleration-approximation approach.” 2018. Web. 22 Sep 2019.

Vancouver:

Yazdan Bakhsh A. Neuro-general computing an acceleration-approximation approach. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/60224.

Council of Science Editors:

Yazdan Bakhsh A. Neuro-general computing an acceleration-approximation approach. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60224


Georgia Tech

29. Hein, Eric Robert. Near-data processing for dynamic graph analytics.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 Massive data rates in cybersecurity, simulation, and social media analysis applications are driving rapid advances in the field of streaming graph analytics. The data structures… (more)

Subjects/Keywords: Computer architecture; Streaming graph analytics; Graph algorithms; High-performance computing; Near-data processing

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APA (6th Edition):

Hein, E. R. (2018). Near-data processing for dynamic graph analytics. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60228

Chicago Manual of Style (16th Edition):

Hein, Eric Robert. “Near-data processing for dynamic graph analytics.” 2018. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/60228.

MLA Handbook (7th Edition):

Hein, Eric Robert. “Near-data processing for dynamic graph analytics.” 2018. Web. 22 Sep 2019.

Vancouver:

Hein ER. Near-data processing for dynamic graph analytics. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/60228.

Council of Science Editors:

Hein ER. Near-data processing for dynamic graph analytics. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60228


Georgia Tech

30. Rao, Karthik. Coordinated management of the processor and memory for optimizing energy efficiency.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 Energy efficiency is a key design goal for future computing systems. With diverse components interacting with each other on the System-on-Chip (SoC), dynamically managing performance,… (more)

Subjects/Keywords: Feedback control; Optimization; Adaptive control; 3D stacked architecture; Thermal management; Energy efficiency; Android

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APA (6th Edition):

Rao, K. (2018). Coordinated management of the processor and memory for optimizing energy efficiency. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60234

Chicago Manual of Style (16th Edition):

Rao, Karthik. “Coordinated management of the processor and memory for optimizing energy efficiency.” 2018. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/60234.

MLA Handbook (7th Edition):

Rao, Karthik. “Coordinated management of the processor and memory for optimizing energy efficiency.” 2018. Web. 22 Sep 2019.

Vancouver:

Rao K. Coordinated management of the processor and memory for optimizing energy efficiency. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/60234.

Council of Science Editors:

Rao K. Coordinated management of the processor and memory for optimizing energy efficiency. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60234

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