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You searched for +publisher:"Georgia Tech" +contributor:("Yalamanchili, Sudhakar"). Showing records 1 – 30 of 126 total matches.

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Georgia Tech

1. VanDerheyden, Andrew Louis. Characterization of thermal coupling in chip multiprocessors.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 For semiconductor processors temperature increases leakage current, which in turn in- creases the temperature of the processor. This increase in heat is seen by other… (more)

Subjects/Keywords: Thermal management; Thermal characterization; Thermal coupling; High performance processors; Thermal analysis

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APA (6th Edition):

VanDerheyden, A. L. (2014). Characterization of thermal coupling in chip multiprocessors. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51892

Chicago Manual of Style (16th Edition):

VanDerheyden, Andrew Louis. “Characterization of thermal coupling in chip multiprocessors.” 2014. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/51892.

MLA Handbook (7th Edition):

VanDerheyden, Andrew Louis. “Characterization of thermal coupling in chip multiprocessors.” 2014. Web. 26 Oct 2020.

Vancouver:

VanDerheyden AL. Characterization of thermal coupling in chip multiprocessors. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/51892.

Council of Science Editors:

VanDerheyden AL. Characterization of thermal coupling in chip multiprocessors. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51892


Georgia Tech

2. Bharadwaj, Vedula Venkata. Scaling address translation in multi-core architectures using low-latency interconnects.

Degree: MS, Electrical and Computer Engineering, 2017, Georgia Tech

 Modern systems employ structures known as Translation Lookaside Buffers(TLB) to accelerate the address translation mechanism. As workloads use ever-increasing memory footprints, TLBs are becoming critical… (more)

Subjects/Keywords: TLB; NUTRA; SMART; Interconnect; Distributed; NUCA

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APA (6th Edition):

Bharadwaj, V. V. (2017). Scaling address translation in multi-core architectures using low-latency interconnects. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59300

Chicago Manual of Style (16th Edition):

Bharadwaj, Vedula Venkata. “Scaling address translation in multi-core architectures using low-latency interconnects.” 2017. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/59300.

MLA Handbook (7th Edition):

Bharadwaj, Vedula Venkata. “Scaling address translation in multi-core architectures using low-latency interconnects.” 2017. Web. 26 Oct 2020.

Vancouver:

Bharadwaj VV. Scaling address translation in multi-core architectures using low-latency interconnects. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/59300.

Council of Science Editors:

Bharadwaj VV. Scaling address translation in multi-core architectures using low-latency interconnects. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59300


Georgia Tech

3. Young, Vinson. Hardware-assisted security: bloom cache – scalable low-overhead control flow integrity checking.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 Computers were not built with security in mind. As such, security has and still often takes a back seat to performance. However, in an era… (more)

Subjects/Keywords: Security; Bloom filter; Control flow hijacking; Memory; Control flow integrity

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APA (6th Edition):

Young, V. (2014). Hardware-assisted security: bloom cache – scalable low-overhead control flow integrity checking. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53994

Chicago Manual of Style (16th Edition):

Young, Vinson. “Hardware-assisted security: bloom cache – scalable low-overhead control flow integrity checking.” 2014. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/53994.

MLA Handbook (7th Edition):

Young, Vinson. “Hardware-assisted security: bloom cache – scalable low-overhead control flow integrity checking.” 2014. Web. 26 Oct 2020.

Vancouver:

Young V. Hardware-assisted security: bloom cache – scalable low-overhead control flow integrity checking. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/53994.

Council of Science Editors:

Young V. Hardware-assisted security: bloom cache – scalable low-overhead control flow integrity checking. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/53994


Georgia Tech

4. Gupta, Meghana. Code generation and adaptive control divergence management for light weight SIMT processors.

Degree: MS, Computer Science, 2016, Georgia Tech

 The energy costs of data movement are limiting the performance scaling of future generations of high performance computing architectures targeted to data intensive applications. The… (more)

Subjects/Keywords: Compiler; SIMT; Control divergence

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APA (6th Edition):

Gupta, M. (2016). Code generation and adaptive control divergence management for light weight SIMT processors. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55044

Chicago Manual of Style (16th Edition):

Gupta, Meghana. “Code generation and adaptive control divergence management for light weight SIMT processors.” 2016. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/55044.

MLA Handbook (7th Edition):

Gupta, Meghana. “Code generation and adaptive control divergence management for light weight SIMT processors.” 2016. Web. 26 Oct 2020.

Vancouver:

Gupta M. Code generation and adaptive control divergence management for light weight SIMT processors. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/55044.

Council of Science Editors:

Gupta M. Code generation and adaptive control divergence management for light weight SIMT processors. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55044


Georgia Tech

5. Saeed, Ifrah. A portable relational algebra library for high performance data-intensive query processing.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 A growing number of industries are turning to data warehousing applications such as forecasting and risk assessment to process large volumes of data. These data… (more)

Subjects/Keywords: Data-intensive query processing; RA operators; OpenCL; GPUs; CPUs; Graphics processing units; Data warehousing; Big data; Relation algebras

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APA (6th Edition):

Saeed, I. (2014). A portable relational algebra library for high performance data-intensive query processing. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51967

Chicago Manual of Style (16th Edition):

Saeed, Ifrah. “A portable relational algebra library for high performance data-intensive query processing.” 2014. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/51967.

MLA Handbook (7th Edition):

Saeed, Ifrah. “A portable relational algebra library for high performance data-intensive query processing.” 2014. Web. 26 Oct 2020.

Vancouver:

Saeed I. A portable relational algebra library for high performance data-intensive query processing. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/51967.

Council of Science Editors:

Saeed I. A portable relational algebra library for high performance data-intensive query processing. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51967


Georgia Tech

6. Na, Taesik. Energy efficient, secure and noise robust deep learning for the internet of things.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The objective of this research is to design an energy efficient, secure and noise robust deep learning system for the Internet of Things (IoTs). The… (more)

Subjects/Keywords: Deep learning; Adversarial machine learning; Energy efficient training; Noise robust machine learning; IoT

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APA (6th Edition):

Na, T. (2018). Energy efficient, secure and noise robust deep learning for the internet of things. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60293

Chicago Manual of Style (16th Edition):

Na, Taesik. “Energy efficient, secure and noise robust deep learning for the internet of things.” 2018. Doctoral Dissertation, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/60293.

MLA Handbook (7th Edition):

Na, Taesik. “Energy efficient, secure and noise robust deep learning for the internet of things.” 2018. Web. 26 Oct 2020.

Vancouver:

Na T. Energy efficient, secure and noise robust deep learning for the internet of things. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/60293.

Council of Science Editors:

Na T. Energy efficient, secure and noise robust deep learning for the internet of things. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60293


Georgia Tech

7. Carlo, Sergio. Load-Aware Power Conversion and Integration for Heterogeneous Systems.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 In this thesis we develop a holistic co-design approach to optimize the conversion systems in order to perform relevant trade-offs taking into account system-level converter,… (more)

Subjects/Keywords: Power conversion 3D single inductor multiple output SIMO control design power management

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APA (6th Edition):

Carlo, S. (2015). Load-Aware Power Conversion and Integration for Heterogeneous Systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56182

Chicago Manual of Style (16th Edition):

Carlo, Sergio. “Load-Aware Power Conversion and Integration for Heterogeneous Systems.” 2015. Doctoral Dissertation, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/56182.

MLA Handbook (7th Edition):

Carlo, Sergio. “Load-Aware Power Conversion and Integration for Heterogeneous Systems.” 2015. Web. 26 Oct 2020.

Vancouver:

Carlo S. Load-Aware Power Conversion and Integration for Heterogeneous Systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/56182.

Council of Science Editors:

Carlo S. Load-Aware Power Conversion and Integration for Heterogeneous Systems. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56182

8. Nair, Prashant. Designing low power SRAM system using energy compression.

Degree: MS, Electrical and Computer Engineering, 2013, Georgia Tech

 The power consumption in commercial processors and application specific integrated circuits increases with decreasing technology nodes. Power saving techniques have become a first class design… (more)

Subjects/Keywords: Computer architecture; Leakage reduction; SRAM; VLSI; Low power; Random access memory; Image processing Digital techniques; Digital video

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APA (6th Edition):

Nair, P. (2013). Designing low power SRAM system using energy compression. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/47663

Chicago Manual of Style (16th Edition):

Nair, Prashant. “Designing low power SRAM system using energy compression.” 2013. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/47663.

MLA Handbook (7th Edition):

Nair, Prashant. “Designing low power SRAM system using energy compression.” 2013. Web. 26 Oct 2020.

Vancouver:

Nair P. Designing low power SRAM system using energy compression. [Internet] [Masters thesis]. Georgia Tech; 2013. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/47663.

Council of Science Editors:

Nair P. Designing low power SRAM system using energy compression. [Masters Thesis]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/47663

9. Zia, Muneeb. SRAM system design for memory based computing.

Degree: MS, Electrical and Computer Engineering, 2013, Georgia Tech

 The objective of the research was to design and test an SRAM system which can meet the performance criteria for Memory Based Computing (MBC). This… (more)

Subjects/Keywords: Look-up table; Asymmetric SRAM; Spatial computing; Temporal computing; Re-configurable computing; Memory based computing; Pulsed read operation; Memory management (Computer science); Random access memory

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APA (6th Edition):

Zia, M. (2013). SRAM system design for memory based computing. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/47636

Chicago Manual of Style (16th Edition):

Zia, Muneeb. “SRAM system design for memory based computing.” 2013. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/47636.

MLA Handbook (7th Edition):

Zia, Muneeb. “SRAM system design for memory based computing.” 2013. Web. 26 Oct 2020.

Vancouver:

Zia M. SRAM system design for memory based computing. [Internet] [Masters thesis]. Georgia Tech; 2013. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/47636.

Council of Science Editors:

Zia M. SRAM system design for memory based computing. [Masters Thesis]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/47636

10. Ahmed, Khondker Zakir. Low voltage autonomous buck-boost regulator for wide input energy harvesting.

Degree: MS, Electrical and Computer Engineering, 2015, Georgia Tech

 While high power buck-boost regulators have been extensively researched and developed in the academia and industry, low power counterparts have only recently gained momentum due… (more)

Subjects/Keywords: Buck-boost regulator; |Low voltage energy harvesting; Low current regulator; nA bias current regulator

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APA (6th Edition):

Ahmed, K. Z. (2015). Low voltage autonomous buck-boost regulator for wide input energy harvesting. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53604

Chicago Manual of Style (16th Edition):

Ahmed, Khondker Zakir. “Low voltage autonomous buck-boost regulator for wide input energy harvesting.” 2015. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/53604.

MLA Handbook (7th Edition):

Ahmed, Khondker Zakir. “Low voltage autonomous buck-boost regulator for wide input energy harvesting.” 2015. Web. 26 Oct 2020.

Vancouver:

Ahmed KZ. Low voltage autonomous buck-boost regulator for wide input energy harvesting. [Internet] [Masters thesis]. Georgia Tech; 2015. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/53604.

Council of Science Editors:

Ahmed KZ. Low voltage autonomous buck-boost regulator for wide input energy harvesting. [Masters Thesis]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53604

11. Parthasarathy, Swarrnna Karthik. Energy efficient active cooling of integrated circuits using embedded thermoelectric devices.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 With technology scaling, the amount of transistors on a single chip doubles itself every 18 months giving rise to increased power density levels. This has… (more)

Subjects/Keywords: Thermoelectric devices; Seebeck effect; Peltier effect; Thin-film TE devices; Mode switching

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APA (6th Edition):

Parthasarathy, S. K. (2014). Energy efficient active cooling of integrated circuits using embedded thermoelectric devices. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53047

Chicago Manual of Style (16th Edition):

Parthasarathy, Swarrnna Karthik. “Energy efficient active cooling of integrated circuits using embedded thermoelectric devices.” 2014. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/53047.

MLA Handbook (7th Edition):

Parthasarathy, Swarrnna Karthik. “Energy efficient active cooling of integrated circuits using embedded thermoelectric devices.” 2014. Web. 26 Oct 2020.

Vancouver:

Parthasarathy SK. Energy efficient active cooling of integrated circuits using embedded thermoelectric devices. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/53047.

Council of Science Editors:

Parthasarathy SK. Energy efficient active cooling of integrated circuits using embedded thermoelectric devices. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/53047

12. Yeleswarapu, Krishnamurthy. TCAD simulation framework for the study of TSV-device interaction.

Degree: MS, Electrical and Computer Engineering, 2013, Georgia Tech

 With the reduction in transistor dimensions to a few tens of nanometers as a result of aggressive scaling, interconnect delay has now become one of… (more)

Subjects/Keywords: Through silicon via; 3D IC; Three-dimensional integrated circuits

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APA (6th Edition):

Yeleswarapu, K. (2013). TCAD simulation framework for the study of TSV-device interaction. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51785

Chicago Manual of Style (16th Edition):

Yeleswarapu, Krishnamurthy. “TCAD simulation framework for the study of TSV-device interaction.” 2013. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/51785.

MLA Handbook (7th Edition):

Yeleswarapu, Krishnamurthy. “TCAD simulation framework for the study of TSV-device interaction.” 2013. Web. 26 Oct 2020.

Vancouver:

Yeleswarapu K. TCAD simulation framework for the study of TSV-device interaction. [Internet] [Masters thesis]. Georgia Tech; 2013. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/51785.

Council of Science Editors:

Yeleswarapu K. TCAD simulation framework for the study of TSV-device interaction. [Masters Thesis]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/51785

13. Bilbray, Kyle. DSFS: a data storage facilitating service for maximizing security, availability, performance, and customizability.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 The objective of this thesis is to study methods for the flexible and secure storage of sensitive data in an unaltered cloud. While current cloud… (more)

Subjects/Keywords: Secure cloud storage; Data storage; Customizable cloud storage

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APA (6th Edition):

Bilbray, K. (2014). DSFS: a data storage facilitating service for maximizing security, availability, performance, and customizability. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52984

Chicago Manual of Style (16th Edition):

Bilbray, Kyle. “DSFS: a data storage facilitating service for maximizing security, availability, performance, and customizability.” 2014. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/52984.

MLA Handbook (7th Edition):

Bilbray, Kyle. “DSFS: a data storage facilitating service for maximizing security, availability, performance, and customizability.” 2014. Web. 26 Oct 2020.

Vancouver:

Bilbray K. DSFS: a data storage facilitating service for maximizing security, availability, performance, and customizability. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/52984.

Council of Science Editors:

Bilbray K. DSFS: a data storage facilitating service for maximizing security, availability, performance, and customizability. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/52984

14. Nigania, Nimit. FPGA prototyping of custom GPGPUs.

Degree: MS, Computer Science, 2014, Georgia Tech

 Prototyping new systems on hardware is a time-consuming task with limited scope for architectural exploration. The aim of this work was to perform fast prototyping… (more)

Subjects/Keywords: General purpose graphic processing units (GPGPU); Field programmable gate arrays (FPGA); ISA; Cache; Field programmable gate arrays; Rapid prototyping; Computer simulation; Graphics processing units

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APA (6th Edition):

Nigania, N. (2014). FPGA prototyping of custom GPGPUs. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51966

Chicago Manual of Style (16th Edition):

Nigania, Nimit. “FPGA prototyping of custom GPGPUs.” 2014. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/51966.

MLA Handbook (7th Edition):

Nigania, Nimit. “FPGA prototyping of custom GPGPUs.” 2014. Web. 26 Oct 2020.

Vancouver:

Nigania N. FPGA prototyping of custom GPGPUs. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/51966.

Council of Science Editors:

Nigania N. FPGA prototyping of custom GPGPUs. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51966

15. Vassenkov, Phillip. Contech: a shared memory parallel program analysis framework.

Degree: MS, Computer Science, 2013, Georgia Tech

 We are in the era of multicore machines, where we must exploit thread level parallelism for programs to run better, smarter, faster, and more efficiently.… (more)

Subjects/Keywords: Data race; Experimentation; Instrumentation; Lock; Program analysis tools; Pthreads; Race detection; Shared memory; Task graph; Trace; Operating systems (Computers); Electronic data processing Distributed processing; Multiprocessors; Distributed shared memory

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APA (6th Edition):

Vassenkov, P. (2013). Contech: a shared memory parallel program analysis framework. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/50379

Chicago Manual of Style (16th Edition):

Vassenkov, Phillip. “Contech: a shared memory parallel program analysis framework.” 2013. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/50379.

MLA Handbook (7th Edition):

Vassenkov, Phillip. “Contech: a shared memory parallel program analysis framework.” 2013. Web. 26 Oct 2020.

Vancouver:

Vassenkov P. Contech: a shared memory parallel program analysis framework. [Internet] [Masters thesis]. Georgia Tech; 2013. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/50379.

Council of Science Editors:

Vassenkov P. Contech: a shared memory parallel program analysis framework. [Masters Thesis]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/50379

16. Rasquinha, Mitchelle. An energy efficient cache design using spin torque transfer (STT) RAM.

Degree: MS, Electrical and Computer Engineering, 2011, Georgia Tech

 The advent of many core architectures has coincided with the energy and power limited design of modern processors. Projections for main memory clearly show widening… (more)

Subjects/Keywords: Non volatile memory; Cache memory; Random access memory

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APA (6th Edition):

Rasquinha, M. (2011). An energy efficient cache design using spin torque transfer (STT) RAM. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/42715

Chicago Manual of Style (16th Edition):

Rasquinha, Mitchelle. “An energy efficient cache design using spin torque transfer (STT) RAM.” 2011. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/42715.

MLA Handbook (7th Edition):

Rasquinha, Mitchelle. “An energy efficient cache design using spin torque transfer (STT) RAM.” 2011. Web. 26 Oct 2020.

Vancouver:

Rasquinha M. An energy efficient cache design using spin torque transfer (STT) RAM. [Internet] [Masters thesis]. Georgia Tech; 2011. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/42715.

Council of Science Editors:

Rasquinha M. An energy efficient cache design using spin torque transfer (STT) RAM. [Masters Thesis]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/42715

17. Choudhary, Dhruv. Micro-scheduling and its interaction with cache partitioning.

Degree: MS, Electrical and Computer Engineering, 2011, Georgia Tech

 The thesis explores the sources of energy inefficiency in asymmetric multi- core architectures where energy efficiency is measured by the energy-delay squared product. The insights… (more)

Subjects/Keywords: Cache partitioning; Computer architecture; Thread scheduling; Cache memory; Multiprocessors; Parallel processing (Electronic computers); High performance computing

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APA (6th Edition):

Choudhary, D. (2011). Micro-scheduling and its interaction with cache partitioning. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/41167

Chicago Manual of Style (16th Edition):

Choudhary, Dhruv. “Micro-scheduling and its interaction with cache partitioning.” 2011. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/41167.

MLA Handbook (7th Edition):

Choudhary, Dhruv. “Micro-scheduling and its interaction with cache partitioning.” 2011. Web. 26 Oct 2020.

Vancouver:

Choudhary D. Micro-scheduling and its interaction with cache partitioning. [Internet] [Masters thesis]. Georgia Tech; 2011. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/41167.

Council of Science Editors:

Choudhary D. Micro-scheduling and its interaction with cache partitioning. [Masters Thesis]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/41167

18. Mudassar, Burhan Ahmad. Design and implementation of a content aware image processing module on FPGA.

Degree: MS, Electrical and Computer Engineering, 2015, Georgia Tech

 In this thesis, we tackle the problem of designing and implementing a wireless video sensor network for a surveillance application. The goal was to design… (more)

Subjects/Keywords: Content aware; Image processing; Edge detection; Image preprocessing; Low power; FPGA

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APA (6th Edition):

Mudassar, B. A. (2015). Design and implementation of a content aware image processing module on FPGA. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53618

Chicago Manual of Style (16th Edition):

Mudassar, Burhan Ahmad. “Design and implementation of a content aware image processing module on FPGA.” 2015. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/53618.

MLA Handbook (7th Edition):

Mudassar, Burhan Ahmad. “Design and implementation of a content aware image processing module on FPGA.” 2015. Web. 26 Oct 2020.

Vancouver:

Mudassar BA. Design and implementation of a content aware image processing module on FPGA. [Internet] [Masters thesis]. Georgia Tech; 2015. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/53618.

Council of Science Editors:

Mudassar BA. Design and implementation of a content aware image processing module on FPGA. [Masters Thesis]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53618

19. Desai, Soham Jayesh. Hardware implementation of re-configurable Restricted Boltzmann Machines for image recognition.

Degree: MS, Electrical and Computer Engineering, 2015, Georgia Tech

 The Internet of Things (IoTs) has triggered rapid advances in sensors, surveillance devices, wearables and body area networks with advanced Human-Computer Interfaces (HCI). Neural Networks… (more)

Subjects/Keywords: Restricted Boltzmann Machines; Re-configurable hardware; Neural processing cores; Image recognition; Low power sensing; Body-worn cameras; Cascaded classifiers; Posture detection

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APA (6th Edition):

Desai, S. J. (2015). Hardware implementation of re-configurable Restricted Boltzmann Machines for image recognition. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53548

Chicago Manual of Style (16th Edition):

Desai, Soham Jayesh. “Hardware implementation of re-configurable Restricted Boltzmann Machines for image recognition.” 2015. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/53548.

MLA Handbook (7th Edition):

Desai, Soham Jayesh. “Hardware implementation of re-configurable Restricted Boltzmann Machines for image recognition.” 2015. Web. 26 Oct 2020.

Vancouver:

Desai SJ. Hardware implementation of re-configurable Restricted Boltzmann Machines for image recognition. [Internet] [Masters thesis]. Georgia Tech; 2015. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/53548.

Council of Science Editors:

Desai SJ. Hardware implementation of re-configurable Restricted Boltzmann Machines for image recognition. [Masters Thesis]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53548

20. Bhagwat, Ashwini. Methodologies and tools for computation offloading on heterogeneous multicores.

Degree: MS, Computing, 2009, Georgia Tech

 Frequency scaling in traditional computing systems has hit the power wall and multicore computing is here to stay. Unlike homogeneous multicores which have uniform architecture… (more)

Subjects/Keywords: Parallel Computing; Coprocessors; Coding theory

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APA (6th Edition):

Bhagwat, A. (2009). Methodologies and tools for computation offloading on heterogeneous multicores. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/29688

Chicago Manual of Style (16th Edition):

Bhagwat, Ashwini. “Methodologies and tools for computation offloading on heterogeneous multicores.” 2009. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/29688.

MLA Handbook (7th Edition):

Bhagwat, Ashwini. “Methodologies and tools for computation offloading on heterogeneous multicores.” 2009. Web. 26 Oct 2020.

Vancouver:

Bhagwat A. Methodologies and tools for computation offloading on heterogeneous multicores. [Internet] [Masters thesis]. Georgia Tech; 2009. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/29688.

Council of Science Editors:

Bhagwat A. Methodologies and tools for computation offloading on heterogeneous multicores. [Masters Thesis]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/29688

21. Bahga, Arshdeep. Technologies for context based video search.

Degree: MS, Electrical and Computer Engineering, 2010, Georgia Tech

 This thesis presents methods and a system for video search over the internet or the intranet. The objective is to design a real time and… (more)

Subjects/Keywords: Retrieval; Search; Video; Context; Electronic information resource searching; Digital video; Image processing Digital techniques

…news clusters related to Georgia Tech . . . . . . 32 16 Example of campus news clusters… …related to Georgia Tech . . . . . . . 33 17 Example of custom RSS feeds… …system called Georgia Tech in the News, for news videos related to Georgia Tech. The framework… …Example of seed URLs for video crawler Seed URL http://search.espn.go.com/georgia-tech/video… …http://www.foxnews.com/search-results/search?q=Georgia+Tech&content=Video http… 

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APA (6th Edition):

Bahga, A. (2010). Technologies for context based video search. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/33824

Chicago Manual of Style (16th Edition):

Bahga, Arshdeep. “Technologies for context based video search.” 2010. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/33824.

MLA Handbook (7th Edition):

Bahga, Arshdeep. “Technologies for context based video search.” 2010. Web. 26 Oct 2020.

Vancouver:

Bahga A. Technologies for context based video search. [Internet] [Masters thesis]. Georgia Tech; 2010. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/33824.

Council of Science Editors:

Bahga A. Technologies for context based video search. [Masters Thesis]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/33824

22. McLaughlin, Adam Thomas. Power-constrained performance optimization of GPU graph traversal.

Degree: MS, Electrical and Computer Engineering, 2013, Georgia Tech

 Graph traversal represents an important class of graph algorithms that is the nucleus of many large scale graph analytics applications. While improving the performance of… (more)

Subjects/Keywords: GPU architecture; Graph algorithms; Power-constrained environments; Graph algorithms; Graphics processing units

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APA (6th Edition):

McLaughlin, A. T. (2013). Power-constrained performance optimization of GPU graph traversal. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/50209

Chicago Manual of Style (16th Edition):

McLaughlin, Adam Thomas. “Power-constrained performance optimization of GPU graph traversal.” 2013. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/50209.

MLA Handbook (7th Edition):

McLaughlin, Adam Thomas. “Power-constrained performance optimization of GPU graph traversal.” 2013. Web. 26 Oct 2020.

Vancouver:

McLaughlin AT. Power-constrained performance optimization of GPU graph traversal. [Internet] [Masters thesis]. Georgia Tech; 2013. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/50209.

Council of Science Editors:

McLaughlin AT. Power-constrained performance optimization of GPU graph traversal. [Masters Thesis]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/50209

23. Magudilu Vijayaraj, Thejasvi Magudilu. An empirical power model of a low power mobile platform.

Degree: MS, Electrical and Computer Engineering, 2013, Georgia Tech

 Power is one of the today’s major constraints for both hardware and software design. Thus the need to understand the statistics and distribution of power… (more)

Subjects/Keywords: Empirical power model; OMAP4460; Pandaboard; Power electronics; Energy consumption

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APA (6th Edition):

Magudilu Vijayaraj, T. M. (2013). An empirical power model of a low power mobile platform. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/49054

Chicago Manual of Style (16th Edition):

Magudilu Vijayaraj, Thejasvi Magudilu. “An empirical power model of a low power mobile platform.” 2013. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/49054.

MLA Handbook (7th Edition):

Magudilu Vijayaraj, Thejasvi Magudilu. “An empirical power model of a low power mobile platform.” 2013. Web. 26 Oct 2020.

Vancouver:

Magudilu Vijayaraj TM. An empirical power model of a low power mobile platform. [Internet] [Masters thesis]. Georgia Tech; 2013. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/49054.

Council of Science Editors:

Magudilu Vijayaraj TM. An empirical power model of a low power mobile platform. [Masters Thesis]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/49054

24. Ko, Jong Hwan. Resource-aware and robust image processing for intelligent sensor systems.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The objective of this research is to design resource-aware and robust image processing algorithms, system architecture, and hardware implementation for intelligent image sensor systems in… (more)

Subjects/Keywords: Image processing; Deep learning; Sensor systems

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APA (6th Edition):

Ko, J. H. (2018). Resource-aware and robust image processing for intelligent sensor systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60198

Chicago Manual of Style (16th Edition):

Ko, Jong Hwan. “Resource-aware and robust image processing for intelligent sensor systems.” 2018. Doctoral Dissertation, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/60198.

MLA Handbook (7th Edition):

Ko, Jong Hwan. “Resource-aware and robust image processing for intelligent sensor systems.” 2018. Web. 26 Oct 2020.

Vancouver:

Ko JH. Resource-aware and robust image processing for intelligent sensor systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/60198.

Council of Science Editors:

Ko JH. Resource-aware and robust image processing for intelligent sensor systems. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60198

25. Garg, Kartikay. Near-memory primitive support and infratructure for sparse algorithm.

Degree: MS, Electrical and Computer Engineering, 2017, Georgia Tech

 This thesis introduces an approach to solving the problem of memory latency performance penalties with traditional accelerators. By introducing simple near-data-processing (NDP) accelerators for primitives… (more)

Subjects/Keywords: Processing in memory (PIM); Near data processing (NDP); 3D-stacked memory; HMC; FPGA; SuperLU

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APA (6th Edition):

Garg, K. (2017). Near-memory primitive support and infratructure for sparse algorithm. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58343

Chicago Manual of Style (16th Edition):

Garg, Kartikay. “Near-memory primitive support and infratructure for sparse algorithm.” 2017. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/58343.

MLA Handbook (7th Edition):

Garg, Kartikay. “Near-memory primitive support and infratructure for sparse algorithm.” 2017. Web. 26 Oct 2020.

Vancouver:

Garg K. Near-memory primitive support and infratructure for sparse algorithm. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/58343.

Council of Science Editors:

Garg K. Near-memory primitive support and infratructure for sparse algorithm. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58343

26. Dasgupta, Aniruddha. CUDA performance analyzer.

Degree: MS, Electrical and Computer Engineering, 2011, Georgia Tech

 GPGPU Computing using CUDA is rapidly gaining ground today. GPGPU has been brought to the masses through the ease of use of CUDA and ubiquity… (more)

Subjects/Keywords: GPU; CUDA; Analytical modeling; GPGPU; Optimization; Performance prediction; Fast multipole method; Performance analysis; Ocelot; Graphics processing units; Computer graphics; Application software

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APA (6th Edition):

Dasgupta, A. (2011). CUDA performance analyzer. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/39555

Chicago Manual of Style (16th Edition):

Dasgupta, Aniruddha. “CUDA performance analyzer.” 2011. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/39555.

MLA Handbook (7th Edition):

Dasgupta, Aniruddha. “CUDA performance analyzer.” 2011. Web. 26 Oct 2020.

Vancouver:

Dasgupta A. CUDA performance analyzer. [Internet] [Masters thesis]. Georgia Tech; 2011. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/39555.

Council of Science Editors:

Dasgupta A. CUDA performance analyzer. [Masters Thesis]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/39555

27. Ozarde, Sarang Anil. Performance understanding and tuning of iterative computation using profiling techniques.

Degree: MS, Computing, 2010, Georgia Tech

 Most applications spend a significant amount of time in the iterative parts of a computation. They typically iterate over the same set of operations with… (more)

Subjects/Keywords: Performance debugging; Performance analysis; Combinatorial optimization; Algorithms; Heuristic algorithms

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APA (6th Edition):

Ozarde, S. A. (2010). Performance understanding and tuning of iterative computation using profiling techniques. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/34757

Chicago Manual of Style (16th Edition):

Ozarde, Sarang Anil. “Performance understanding and tuning of iterative computation using profiling techniques.” 2010. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/34757.

MLA Handbook (7th Edition):

Ozarde, Sarang Anil. “Performance understanding and tuning of iterative computation using profiling techniques.” 2010. Web. 26 Oct 2020.

Vancouver:

Ozarde SA. Performance understanding and tuning of iterative computation using profiling techniques. [Internet] [Masters thesis]. Georgia Tech; 2010. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/34757.

Council of Science Editors:

Ozarde SA. Performance understanding and tuning of iterative computation using profiling techniques. [Masters Thesis]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/34757

28. Ramrakhyani, Aniruddh. Aniruddh Ramrakhyani Thesis.

Degree: MS, Electrical and Computer Engineering, 2017, Georgia Tech

 The demise of Dennard Scaling and the continuance of Moore’s law has provided us with shrinking chip dimensions and higher on-chip transistor density at the… (more)

Subjects/Keywords: Deadlocks; NoC; Routing; Computer architecture; Dark Silicon; Power Gating; Resiliency; Topology

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APA (6th Edition):

Ramrakhyani, A. (2017). Aniruddh Ramrakhyani Thesis. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58331

Chicago Manual of Style (16th Edition):

Ramrakhyani, Aniruddh. “Aniruddh Ramrakhyani Thesis.” 2017. Masters Thesis, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/58331.

MLA Handbook (7th Edition):

Ramrakhyani, Aniruddh. “Aniruddh Ramrakhyani Thesis.” 2017. Web. 26 Oct 2020.

Vancouver:

Ramrakhyani A. Aniruddh Ramrakhyani Thesis. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/58331.

Council of Science Editors:

Ramrakhyani A. Aniruddh Ramrakhyani Thesis. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58331


Georgia Tech

29. Giardino, Michael Joseph. A software framework for application-guided power-aware control systems.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 This dissertation describes a system for proactive management of power and performance trade-offs through greater cooperation between applications and hardware. To enable such a management… (more)

Subjects/Keywords: Power-aware computing; Operating systems; Power-aware control systems; Heterogeneous memory; Heterogeneous computing; Bumpless transfer; Transient management; Machine learning; Q-learning; Reinforcement learning; Dynamic power management; Linux

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APA (6th Edition):

Giardino, M. J. (2019). A software framework for application-guided power-aware control systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61212

Chicago Manual of Style (16th Edition):

Giardino, Michael Joseph. “A software framework for application-guided power-aware control systems.” 2019. Doctoral Dissertation, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/61212.

MLA Handbook (7th Edition):

Giardino, Michael Joseph. “A software framework for application-guided power-aware control systems.” 2019. Web. 26 Oct 2020.

Vancouver:

Giardino MJ. A software framework for application-guided power-aware control systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/61212.

Council of Science Editors:

Giardino MJ. A software framework for application-guided power-aware control systems. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/61212


Georgia Tech

30. Gangopadhyay, Samantak. On-die adaptive power regulation and distribution for digital loads.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 The objective of this dissertation is to provide a power architecture solution where guardband reduction and consistent performance are the key goals for power delivery… (more)

Subjects/Keywords: Low-dropout regulator; Clocking; Phase lock loop; Voltage headroom; Leakage current; Switched capacitor network; Multi-ratio switched capacitor; Multiple-output switched capacitor; Flexible SC; Phase locked LDO; Adaptation; Resiliency; DVFS; CMOS; Digital LDO; Power distribution

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APA (6th Edition):

Gangopadhyay, S. (2017). On-die adaptive power regulation and distribution for digital loads. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62179

Chicago Manual of Style (16th Edition):

Gangopadhyay, Samantak. “On-die adaptive power regulation and distribution for digital loads.” 2017. Doctoral Dissertation, Georgia Tech. Accessed October 26, 2020. http://hdl.handle.net/1853/62179.

MLA Handbook (7th Edition):

Gangopadhyay, Samantak. “On-die adaptive power regulation and distribution for digital loads.” 2017. Web. 26 Oct 2020.

Vancouver:

Gangopadhyay S. On-die adaptive power regulation and distribution for digital loads. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1853/62179.

Council of Science Editors:

Gangopadhyay S. On-die adaptive power regulation and distribution for digital loads. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/62179

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