Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for +publisher:"Georgia Tech" +contributor:("Swaminathan, Madhavan"). Showing records 1 – 30 of 72 total matches.

[1] [2] [3]

Search Limiters

Last 2 Years | English Only

Degrees

Levels

▼ Search Limiters

1. Roper, Joshua. Design of a circular reflectarray with a performance comparable to the typical rectangular reflectarray.

Degree: MS, Electrical and Computer Engineering, 2017, Georgia Tech

 A circular reflectarray is a novel design combining the unit-ring artificial magnetic conductor with the reflectarray concept. It is shown through simulation that a circular… (more)

Subjects/Keywords: Antenna; Microwave

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Roper, J. (2017). Design of a circular reflectarray with a performance comparable to the typical rectangular reflectarray. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59292

Chicago Manual of Style (16th Edition):

Roper, Joshua. “Design of a circular reflectarray with a performance comparable to the typical rectangular reflectarray.” 2017. Masters Thesis, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/59292.

MLA Handbook (7th Edition):

Roper, Joshua. “Design of a circular reflectarray with a performance comparable to the typical rectangular reflectarray.” 2017. Web. 18 Apr 2021.

Vancouver:

Roper J. Design of a circular reflectarray with a performance comparable to the typical rectangular reflectarray. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/59292.

Council of Science Editors:

Roper J. Design of a circular reflectarray with a performance comparable to the typical rectangular reflectarray. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59292


Georgia Tech

2. Suresh, Srinidhi. Modeling, design and fabrication of substrate-embedded inductors with high inductance density and low DC resistance for integrated voltage regulators.

Degree: MS, Materials Science and Engineering, 2020, Georgia Tech

 There is an increasing need for voltage regulators to be integrated closer to active devices such as CPUs and GPUs. These integrated voltage regulators (IVRs)… (more)

Subjects/Keywords: Integrated voltage regulator; Inductor; Metal polymer composite; Toroid inductor; 48V-1V; Inductance density; DC resistance; Fabrication process

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Suresh, S. (2020). Modeling, design and fabrication of substrate-embedded inductors with high inductance density and low DC resistance for integrated voltage regulators. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62819

Chicago Manual of Style (16th Edition):

Suresh, Srinidhi. “Modeling, design and fabrication of substrate-embedded inductors with high inductance density and low DC resistance for integrated voltage regulators.” 2020. Masters Thesis, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/62819.

MLA Handbook (7th Edition):

Suresh, Srinidhi. “Modeling, design and fabrication of substrate-embedded inductors with high inductance density and low DC resistance for integrated voltage regulators.” 2020. Web. 18 Apr 2021.

Vancouver:

Suresh S. Modeling, design and fabrication of substrate-embedded inductors with high inductance density and low DC resistance for integrated voltage regulators. [Internet] [Masters thesis]. Georgia Tech; 2020. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/62819.

Council of Science Editors:

Suresh S. Modeling, design and fabrication of substrate-embedded inductors with high inductance density and low DC resistance for integrated voltage regulators. [Masters Thesis]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/62819


Georgia Tech

3. Mutnuri, Keertana. Channel adaptive process resilient ultra low-power transmitter design with simulated-annealing based self-discovery.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 Modern day wireless communication systems are constantly facing increasing bandwidth demands due to a growing consumer base. To cope up with it, they are required… (more)

Subjects/Keywords: Ofdm; Papr; Companding; Simulated-annealing; Power-amplifier

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mutnuri, K. (2014). Channel adaptive process resilient ultra low-power transmitter design with simulated-annealing based self-discovery. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53402

Chicago Manual of Style (16th Edition):

Mutnuri, Keertana. “Channel adaptive process resilient ultra low-power transmitter design with simulated-annealing based self-discovery.” 2014. Masters Thesis, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/53402.

MLA Handbook (7th Edition):

Mutnuri, Keertana. “Channel adaptive process resilient ultra low-power transmitter design with simulated-annealing based self-discovery.” 2014. Web. 18 Apr 2021.

Vancouver:

Mutnuri K. Channel adaptive process resilient ultra low-power transmitter design with simulated-annealing based self-discovery. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/53402.

Council of Science Editors:

Mutnuri K. Channel adaptive process resilient ultra low-power transmitter design with simulated-annealing based self-discovery. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/53402


Georgia Tech

4. Omprakash, Anup. Extreme environment operation of thick-film SOI SiGe HBTs in both high temperature & radiation-rich environments.

Degree: MS, Electrical and Computer Engineering, 2016, Georgia Tech

 The objective of this work is to characterize and investigate the effect of extreme environments, such as high temperature (up to 300^∘C) and radiation, on… (more)

Subjects/Keywords: SiGe; SiGe HBTs; High temperature; Total dose effects; Reliability; Thermal instability

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Omprakash, A. (2016). Extreme environment operation of thick-film SOI SiGe HBTs in both high temperature & radiation-rich environments. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58195

Chicago Manual of Style (16th Edition):

Omprakash, Anup. “Extreme environment operation of thick-film SOI SiGe HBTs in both high temperature & radiation-rich environments.” 2016. Masters Thesis, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/58195.

MLA Handbook (7th Edition):

Omprakash, Anup. “Extreme environment operation of thick-film SOI SiGe HBTs in both high temperature & radiation-rich environments.” 2016. Web. 18 Apr 2021.

Vancouver:

Omprakash A. Extreme environment operation of thick-film SOI SiGe HBTs in both high temperature & radiation-rich environments. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/58195.

Council of Science Editors:

Omprakash A. Extreme environment operation of thick-film SOI SiGe HBTs in both high temperature & radiation-rich environments. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/58195


Georgia Tech

5. Natu, Nitish Umesh. Design and prototyping of temperature resilient clock distribution networks.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 Clock Distribution Networks play a vital role in performance and reliability of a system. However, temperature gradients observed in 3D ICs hamper the functionality of… (more)

Subjects/Keywords: 3D IC; Through silicon via; Clock distribution network (CDN); Skew; Propagation delay; Adaptive voltage; Controllable delay; FPGA; Test vehicle; ASIC buffer design; Three-dimensional integrated circuits; Integrated circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Natu, N. U. (2014). Design and prototyping of temperature resilient clock distribution networks. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51812

Chicago Manual of Style (16th Edition):

Natu, Nitish Umesh. “Design and prototyping of temperature resilient clock distribution networks.” 2014. Masters Thesis, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/51812.

MLA Handbook (7th Edition):

Natu, Nitish Umesh. “Design and prototyping of temperature resilient clock distribution networks.” 2014. Web. 18 Apr 2021.

Vancouver:

Natu NU. Design and prototyping of temperature resilient clock distribution networks. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/51812.

Council of Science Editors:

Natu NU. Design and prototyping of temperature resilient clock distribution networks. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51812


Georgia Tech

6. Lee, Minah. Automated I/O library generation for interposer based system-in-package integration of multiple heterogeneous dies.

Degree: MS, Electrical and Computer Engineering, 2019, Georgia Tech

 System-in-Package (SiP) integration of multiple dies in a single package can achieve much higher performance than on-board integration of ICs while reducing the design cost/effort… (more)

Subjects/Keywords: System-in-package (SiP); 2.5D integration; Interface circuits; I/O library; Automated flow

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lee, M. (2019). Automated I/O library generation for interposer based system-in-package integration of multiple heterogeneous dies. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62366

Chicago Manual of Style (16th Edition):

Lee, Minah. “Automated I/O library generation for interposer based system-in-package integration of multiple heterogeneous dies.” 2019. Masters Thesis, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/62366.

MLA Handbook (7th Edition):

Lee, Minah. “Automated I/O library generation for interposer based system-in-package integration of multiple heterogeneous dies.” 2019. Web. 18 Apr 2021.

Vancouver:

Lee M. Automated I/O library generation for interposer based system-in-package integration of multiple heterogeneous dies. [Internet] [Masters thesis]. Georgia Tech; 2019. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/62366.

Council of Science Editors:

Lee M. Automated I/O library generation for interposer based system-in-package integration of multiple heterogeneous dies. [Masters Thesis]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62366


Georgia Tech

7. Carlo, Sergio. Load-Aware Power Conversion and Integration for Heterogeneous Systems.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 In this thesis we develop a holistic co-design approach to optimize the conversion systems in order to perform relevant trade-offs taking into account system-level converter,… (more)

Subjects/Keywords: Power conversion 3D single inductor multiple output SIMO control design power management

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Carlo, S. (2015). Load-Aware Power Conversion and Integration for Heterogeneous Systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56182

Chicago Manual of Style (16th Edition):

Carlo, Sergio. “Load-Aware Power Conversion and Integration for Heterogeneous Systems.” 2015. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/56182.

MLA Handbook (7th Edition):

Carlo, Sergio. “Load-Aware Power Conversion and Integration for Heterogeneous Systems.” 2015. Web. 18 Apr 2021.

Vancouver:

Carlo S. Load-Aware Power Conversion and Integration for Heterogeneous Systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/56182.

Council of Science Editors:

Carlo S. Load-Aware Power Conversion and Integration for Heterogeneous Systems. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56182


Georgia Tech

8. Zhou, Yi. Mechanical and High-Frequency Electrical Study of Printed, Flexible Antenna under Deformation.

Degree: MS, Mechanical Engineering, 2019, Georgia Tech

 Flexible hybrid electronics (FHE) has wide range of applications including medical devices, wearable devices, communication devices, automotive and aerospace sensors, and various consumer Internet of… (more)

Subjects/Keywords: Flexible printed antenna; Inkjet-printed electronics; Flexible hybrid electronics; Patch antenna; finite-element model; Bending test

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhou, Y. (2019). Mechanical and High-Frequency Electrical Study of Printed, Flexible Antenna under Deformation. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/64005

Chicago Manual of Style (16th Edition):

Zhou, Yi. “Mechanical and High-Frequency Electrical Study of Printed, Flexible Antenna under Deformation.” 2019. Masters Thesis, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/64005.

MLA Handbook (7th Edition):

Zhou, Yi. “Mechanical and High-Frequency Electrical Study of Printed, Flexible Antenna under Deformation.” 2019. Web. 18 Apr 2021.

Vancouver:

Zhou Y. Mechanical and High-Frequency Electrical Study of Printed, Flexible Antenna under Deformation. [Internet] [Masters thesis]. Georgia Tech; 2019. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/64005.

Council of Science Editors:

Zhou Y. Mechanical and High-Frequency Electrical Study of Printed, Flexible Antenna under Deformation. [Masters Thesis]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/64005

9. Laddha, Vishal. Correlation of PDN impedance with jitter and voltage margin in high speed channels.

Degree: MS, Electrical and Computer Engineering, 2008, Georgia Tech

 Jitter and noise on package and printed circuit board interconnects are limiting factors in the performance of high speed digital channels. The simultaneous switching noise… (more)

Subjects/Keywords: PDN impedance; Jitter; Noise margin; Impedance (Electricity); Genetic algorithms

Page 1 Page 2 Page 3 Page 4 Page 5

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Laddha, V. (2008). Correlation of PDN impedance with jitter and voltage margin in high speed channels. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/26521

Chicago Manual of Style (16th Edition):

Laddha, Vishal. “Correlation of PDN impedance with jitter and voltage margin in high speed channels.” 2008. Masters Thesis, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/26521.

MLA Handbook (7th Edition):

Laddha, Vishal. “Correlation of PDN impedance with jitter and voltage margin in high speed channels.” 2008. Web. 18 Apr 2021.

Vancouver:

Laddha V. Correlation of PDN impedance with jitter and voltage margin in high speed channels. [Internet] [Masters thesis]. Georgia Tech; 2008. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/26521.

Council of Science Editors:

Laddha V. Correlation of PDN impedance with jitter and voltage margin in high speed channels. [Masters Thesis]. Georgia Tech; 2008. Available from: http://hdl.handle.net/1853/26521

10. Huang, Min-Yu. Ultra-compact concurrent multi-directional beamforming receiving network for high-efficiency wireless power transfer (WPT).

Degree: MS, Electrical and Computer Engineering, 2018, Georgia Tech

 This thesis demonstrates an all-passive ultra-compact low-loss array-based beamforming rectenna array for high-efficiency wireless power transfer (WPT). The detailed circuit analysis and theoretical derivation are… (more)

Subjects/Keywords: Array factor; Beamforming; Field-of-view; Phased array; Rectifier; Rectenna array; Wireless power transfer

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, M. (2018). Ultra-compact concurrent multi-directional beamforming receiving network for high-efficiency wireless power transfer (WPT). (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60829

Chicago Manual of Style (16th Edition):

Huang, Min-Yu. “Ultra-compact concurrent multi-directional beamforming receiving network for high-efficiency wireless power transfer (WPT).” 2018. Masters Thesis, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/60829.

MLA Handbook (7th Edition):

Huang, Min-Yu. “Ultra-compact concurrent multi-directional beamforming receiving network for high-efficiency wireless power transfer (WPT).” 2018. Web. 18 Apr 2021.

Vancouver:

Huang M. Ultra-compact concurrent multi-directional beamforming receiving network for high-efficiency wireless power transfer (WPT). [Internet] [Masters thesis]. Georgia Tech; 2018. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/60829.

Council of Science Editors:

Huang M. Ultra-compact concurrent multi-directional beamforming receiving network for high-efficiency wireless power transfer (WPT). [Masters Thesis]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60829


Georgia Tech

11. Busi Reddy, Vishnu Vardhan Reddy. Development of dual-fiber array laser ultrasonic system for inspecting and assessing area-array microelectronic packages.

Degree: PhD, Mechanical Engineering, 2020, Georgia Tech

 Failures in solder ball interconnects makes a microelectronic packaging system inoperable. These failures often result from defects during assembly and/or due to damage accrued from… (more)

Subjects/Keywords: Laser ultrasonic inspection; Microelectronic packaging; Non-destructive Inspection

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Busi Reddy, V. V. R. (2020). Development of dual-fiber array laser ultrasonic system for inspecting and assessing area-array microelectronic packages. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/63590

Chicago Manual of Style (16th Edition):

Busi Reddy, Vishnu Vardhan Reddy. “Development of dual-fiber array laser ultrasonic system for inspecting and assessing area-array microelectronic packages.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/63590.

MLA Handbook (7th Edition):

Busi Reddy, Vishnu Vardhan Reddy. “Development of dual-fiber array laser ultrasonic system for inspecting and assessing area-array microelectronic packages.” 2020. Web. 18 Apr 2021.

Vancouver:

Busi Reddy VVR. Development of dual-fiber array laser ultrasonic system for inspecting and assessing area-array microelectronic packages. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/63590.

Council of Science Editors:

Busi Reddy VVR. Development of dual-fiber array laser ultrasonic system for inspecting and assessing area-array microelectronic packages. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/63590


Georgia Tech

12. Park, Sung Joo. Managing signal, power, and thermal integrity for three-dimensional integrated circuits.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 A full thermal-electrical model of a 3-D system consisting of a PCB, an interposer, TSVs, and stacked dies was built and simulated. From the results… (more)

Subjects/Keywords: 3-D integration; TSV; Electrical-thermal

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Park, S. J. (2016). Managing signal, power, and thermal integrity for three-dimensional integrated circuits. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58604

Chicago Manual of Style (16th Edition):

Park, Sung Joo. “Managing signal, power, and thermal integrity for three-dimensional integrated circuits.” 2016. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/58604.

MLA Handbook (7th Edition):

Park, Sung Joo. “Managing signal, power, and thermal integrity for three-dimensional integrated circuits.” 2016. Web. 18 Apr 2021.

Vancouver:

Park SJ. Managing signal, power, and thermal integrity for three-dimensional integrated circuits. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/58604.

Council of Science Editors:

Park SJ. Managing signal, power, and thermal integrity for three-dimensional integrated circuits. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/58604


Georgia Tech

13. Ha, Myunghyun. EM simulation using the Laguerre-FDTD scheme for multiscale 3-D interconnections.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 As the current electronic trend is toward integrating multiple functions in a single electronic device, there is a clear need for increasing integration density which… (more)

Subjects/Keywords: Unconditionally stable method; Finite-difference time-domain; Computational electromagentics; Laguerre-FDTD; Interconnects (Integrated circuit technology); Integrated circuits; Three-dimensional integrated circuits; Semiconductors

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ha, M. (2011). EM simulation using the Laguerre-FDTD scheme for multiscale 3-D interconnections. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/42850

Chicago Manual of Style (16th Edition):

Ha, Myunghyun. “EM simulation using the Laguerre-FDTD scheme for multiscale 3-D interconnections.” 2011. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/42850.

MLA Handbook (7th Edition):

Ha, Myunghyun. “EM simulation using the Laguerre-FDTD scheme for multiscale 3-D interconnections.” 2011. Web. 18 Apr 2021.

Vancouver:

Ha M. EM simulation using the Laguerre-FDTD scheme for multiscale 3-D interconnections. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/42850.

Council of Science Editors:

Ha M. EM simulation using the Laguerre-FDTD scheme for multiscale 3-D interconnections. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/42850


Georgia Tech

14. Pardue, Colin Andrew. Wireless power transfer using integrated and emerging technologies.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 To support the next generation of compact low power devices, a wireless power transfer solution needs to have an improved combination of receiver coil area… (more)

Subjects/Keywords: Wireless power transfer; Internet of things; Integrated inductor; Packaging; Rf near field coupling; Power integrity

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pardue, C. A. (2018). Wireless power transfer using integrated and emerging technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60216

Chicago Manual of Style (16th Edition):

Pardue, Colin Andrew. “Wireless power transfer using integrated and emerging technologies.” 2018. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/60216.

MLA Handbook (7th Edition):

Pardue, Colin Andrew. “Wireless power transfer using integrated and emerging technologies.” 2018. Web. 18 Apr 2021.

Vancouver:

Pardue CA. Wireless power transfer using integrated and emerging technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/60216.

Council of Science Editors:

Pardue CA. Wireless power transfer using integrated and emerging technologies. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60216


Georgia Tech

15. Nasir, Saad Bin. Fine-grain on-chip power management using digital and digitally-assisted linear voltage regulators.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 On-chip voltage conversion and regulation right at the point-of-load using digital and digitally-assisted linear voltage regulators was proposed. On-chip voltage conversion and regulation minimizes power… (more)

Subjects/Keywords: On-chip power delivery; Digital and digitally assisted linear voltage regulators; LDO

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nasir, S. B. (2017). Fine-grain on-chip power management using digital and digitally-assisted linear voltage regulators. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60708

Chicago Manual of Style (16th Edition):

Nasir, Saad Bin. “Fine-grain on-chip power management using digital and digitally-assisted linear voltage regulators.” 2017. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/60708.

MLA Handbook (7th Edition):

Nasir, Saad Bin. “Fine-grain on-chip power management using digital and digitally-assisted linear voltage regulators.” 2017. Web. 18 Apr 2021.

Vancouver:

Nasir SB. Fine-grain on-chip power management using digital and digitally-assisted linear voltage regulators. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/60708.

Council of Science Editors:

Nasir SB. Fine-grain on-chip power management using digital and digitally-assisted linear voltage regulators. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/60708


Georgia Tech

16. Han, Kyuhwan. Magneto-dielectric material characterization and RF antenna design.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 A novel material characterization method for magneto-dielectric composite material was proposed. MD materials have been reported as providing new opportunities for effective antenna size reduction… (more)

Subjects/Keywords: Magneto-dielectric material; Material characterization method; RF antenna design; Ferromagentic material

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Han, K. (2015). Magneto-dielectric material characterization and RF antenna design. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53863

Chicago Manual of Style (16th Edition):

Han, Kyuhwan. “Magneto-dielectric material characterization and RF antenna design.” 2015. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/53863.

MLA Handbook (7th Edition):

Han, Kyuhwan. “Magneto-dielectric material characterization and RF antenna design.” 2015. Web. 18 Apr 2021.

Vancouver:

Han K. Magneto-dielectric material characterization and RF antenna design. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/53863.

Council of Science Editors:

Han K. Magneto-dielectric material characterization and RF antenna design. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53863


Georgia Tech

17. Zhang, David Chong. Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 A power distribution network (PDN) is designed to provide clean power and facilitate high signal integrity in modern electronic systems. However, the design of a… (more)

Subjects/Keywords: Power delivery network; Power transmission line; Signal integrity; Power integrity; Return path discontinuity

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhang, D. C. (2016). Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56282

Chicago Manual of Style (16th Edition):

Zhang, David Chong. “Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems.” 2016. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/56282.

MLA Handbook (7th Edition):

Zhang, David Chong. “Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems.” 2016. Web. 18 Apr 2021.

Vancouver:

Zhang DC. Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/56282.

Council of Science Editors:

Zhang DC. Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56282


Georgia Tech

18. Peng, Yarui. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 As one of more-than-Moore technologies, 3D ICs enable next-generation systems with much higher device density without needs for technology scaling. However, designing reliable 3D IC… (more)

Subjects/Keywords: 3D IC; CAD; Methodology; Reliable; Power integrity; Signal integrity

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Peng, Y. (2016). CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56330

Chicago Manual of Style (16th Edition):

Peng, Yarui. “CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.” 2016. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/56330.

MLA Handbook (7th Edition):

Peng, Yarui. “CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.” 2016. Web. 18 Apr 2021.

Vancouver:

Peng Y. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/56330.

Council of Science Editors:

Peng Y. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56330


Georgia Tech

19. Cao, Ningyuan. Circuit and algorithm design to enable edge intelligence.

Degree: PhD, Electrical and Computer Engineering, 2020, Georgia Tech

 “Edge Intelligence” (EI) is a promising alternative to a centralized could-IoT paradigm that has inherent advantages with communication cost, processing latency, data security, network robustness,… (more)

Subjects/Keywords: Edge intelligence; Edge computation; Internet-of-things; System-on-chip; ASIC; Low-power circuit; Machine learning; Artificial intelligence; Micro-robotics

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cao, N. (2020). Circuit and algorithm design to enable edge intelligence. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/63653

Chicago Manual of Style (16th Edition):

Cao, Ningyuan. “Circuit and algorithm design to enable edge intelligence.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/63653.

MLA Handbook (7th Edition):

Cao, Ningyuan. “Circuit and algorithm design to enable edge intelligence.” 2020. Web. 18 Apr 2021.

Vancouver:

Cao N. Circuit and algorithm design to enable edge intelligence. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/63653.

Council of Science Editors:

Cao N. Circuit and algorithm design to enable edge intelligence. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/63653


Georgia Tech

20. Yu, Huan. Behavioral modeling of drivers and oscillators using machine learning.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 The objective of this dissertation is to develop time-domain behavioral models for I/O drivers and oscillators for fast simulation and IP protection. For oscillators, augmented… (more)

Subjects/Keywords: Behavioral modeling; voltage-controlled oscillator (VCO); neural network; output buffer; pre-emphasis driver; input/output buffer modeling; signal and power integrity; control parameters; overclocking; Verilog-A

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yu, H. (2019). Behavioral modeling of drivers and oscillators using machine learning. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/64031

Chicago Manual of Style (16th Edition):

Yu, Huan. “Behavioral modeling of drivers and oscillators using machine learning.” 2019. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/64031.

MLA Handbook (7th Edition):

Yu, Huan. “Behavioral modeling of drivers and oscillators using machine learning.” 2019. Web. 18 Apr 2021.

Vancouver:

Yu H. Behavioral modeling of drivers and oscillators using machine learning. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/64031.

Council of Science Editors:

Yu H. Behavioral modeling of drivers and oscillators using machine learning. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/64031


Georgia Tech

21. Huang, Min-Yu MY. NEW SYSTEM ARCHITECTURE FOR NEXT-GENERATION WIDEBAND ULTRA-RELIABLE LOW-LATENCY COMMUNICATIONS AND NETWORKS.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 Millimeter-Wave (mm-Wave) links will serve as the enabling technology for a plethora of commercial and defense applications for next-generation (5G/6G beyond) networks. To support future… (more)

Subjects/Keywords: 5G; array-based spatial filter; blocker rejection; beamforming; closed-loop; field-of-view (FoV); high capacity; iterative source localization; low-latency; millimeter-wave; multi-input-multi-output (MIMO); phased array; receiver; self-steering; fiber-wireless network; image rejection; I/Q generation

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, M. M. (2019). NEW SYSTEM ARCHITECTURE FOR NEXT-GENERATION WIDEBAND ULTRA-RELIABLE LOW-LATENCY COMMUNICATIONS AND NETWORKS. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/64037

Chicago Manual of Style (16th Edition):

Huang, Min-Yu MY. “NEW SYSTEM ARCHITECTURE FOR NEXT-GENERATION WIDEBAND ULTRA-RELIABLE LOW-LATENCY COMMUNICATIONS AND NETWORKS.” 2019. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/64037.

MLA Handbook (7th Edition):

Huang, Min-Yu MY. “NEW SYSTEM ARCHITECTURE FOR NEXT-GENERATION WIDEBAND ULTRA-RELIABLE LOW-LATENCY COMMUNICATIONS AND NETWORKS.” 2019. Web. 18 Apr 2021.

Vancouver:

Huang MM. NEW SYSTEM ARCHITECTURE FOR NEXT-GENERATION WIDEBAND ULTRA-RELIABLE LOW-LATENCY COMMUNICATIONS AND NETWORKS. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/64037.

Council of Science Editors:

Huang MM. NEW SYSTEM ARCHITECTURE FOR NEXT-GENERATION WIDEBAND ULTRA-RELIABLE LOW-LATENCY COMMUNICATIONS AND NETWORKS. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/64037


Georgia Tech

22. Ali, Muhammad. Modeling, Design and Fabrication of Miniaturized, High Performance and Integrated Passive Components for 5G and mm-Wave Applications.

Degree: PhD, Electrical and Computer Engineering, 2020, Georgia Tech

 The objective of this research is to model, design, fabricate and characterize integrated passive components for 5G and mm-wave applications on advanced substrates such as… (more)

Subjects/Keywords: 5G; new radio; passive components; modeling; design; characterization; semi-additive patterning process; filters; power dividers; diplexers; integrated passive components; error vector magnitude

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ali, M. (2020). Modeling, Design and Fabrication of Miniaturized, High Performance and Integrated Passive Components for 5G and mm-Wave Applications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/64122

Chicago Manual of Style (16th Edition):

Ali, Muhammad. “Modeling, Design and Fabrication of Miniaturized, High Performance and Integrated Passive Components for 5G and mm-Wave Applications.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/64122.

MLA Handbook (7th Edition):

Ali, Muhammad. “Modeling, Design and Fabrication of Miniaturized, High Performance and Integrated Passive Components for 5G and mm-Wave Applications.” 2020. Web. 18 Apr 2021.

Vancouver:

Ali M. Modeling, Design and Fabrication of Miniaturized, High Performance and Integrated Passive Components for 5G and mm-Wave Applications. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/64122.

Council of Science Editors:

Ali M. Modeling, Design and Fabrication of Miniaturized, High Performance and Integrated Passive Components for 5G and mm-Wave Applications. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/64122


Georgia Tech

23. Torun, Hakki Mert. Machine Learning based Design and Optimization for High-Performance Semiconductor Packaging and Systems.

Degree: PhD, Electrical and Computer Engineering, 2020, Georgia Tech

 Semiconductor industry has seen a rapid advancement over the last two decades as the number of transistors in a functional chip increased based on Moore’s… (more)

Subjects/Keywords: machine learning; semiconductor packaging; signal integrity; power integrity; optimization

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Torun, H. M. (2020). Machine Learning based Design and Optimization for High-Performance Semiconductor Packaging and Systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/64145

Chicago Manual of Style (16th Edition):

Torun, Hakki Mert. “Machine Learning based Design and Optimization for High-Performance Semiconductor Packaging and Systems.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/64145.

MLA Handbook (7th Edition):

Torun, Hakki Mert. “Machine Learning based Design and Optimization for High-Performance Semiconductor Packaging and Systems.” 2020. Web. 18 Apr 2021.

Vancouver:

Torun HM. Machine Learning based Design and Optimization for High-Performance Semiconductor Packaging and Systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/64145.

Council of Science Editors:

Torun HM. Machine Learning based Design and Optimization for High-Performance Semiconductor Packaging and Systems. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/64145


Georgia Tech

24. Watanabe, Atom O. Design and Demonstration of High-Performance Ultra-Thin Antenna-integrated 3D Glass-Based mm-wave Packages.

Degree: PhD, Electrical and Computer Engineering, 2020, Georgia Tech

 The fast-growing 5G wireless communications are emerging to transform a range of consumer and industrial sectors. Package integration of mm-wave components with antenna-in-package is one… (more)

Subjects/Keywords: 5G; mm-wave; Packaging; Glass substrates

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Watanabe, A. O. (2020). Design and Demonstration of High-Performance Ultra-Thin Antenna-integrated 3D Glass-Based mm-wave Packages. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/64171

Chicago Manual of Style (16th Edition):

Watanabe, Atom O. “Design and Demonstration of High-Performance Ultra-Thin Antenna-integrated 3D Glass-Based mm-wave Packages.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/64171.

MLA Handbook (7th Edition):

Watanabe, Atom O. “Design and Demonstration of High-Performance Ultra-Thin Antenna-integrated 3D Glass-Based mm-wave Packages.” 2020. Web. 18 Apr 2021.

Vancouver:

Watanabe AO. Design and Demonstration of High-Performance Ultra-Thin Antenna-integrated 3D Glass-Based mm-wave Packages. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/64171.

Council of Science Editors:

Watanabe AO. Design and Demonstration of High-Performance Ultra-Thin Antenna-integrated 3D Glass-Based mm-wave Packages. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/64171


Georgia Tech

25. Shi, Tailong. MODELING, DESIGN, FABRICATION AND DEMONSTRATION OF ULTRA-THIN, HIGH- PERFORMANCE GLASS PANEL EMBEDDED (GPE) PACKAGES FOR MM-WAVE APPLICATIONS.

Degree: PhD, Electrical and Computer Engineering, 2020, Georgia Tech

 The objective of the proposed research is to model, design, fabricate and demonstrate ultra-thin, highperformance ultra-thin glass panel embedded package (GPE) for mm-Wave applications. Ultra-thin… (more)

Subjects/Keywords: ultra-thin; Glass Panel Embedding (GPE)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shi, T. (2020). MODELING, DESIGN, FABRICATION AND DEMONSTRATION OF ULTRA-THIN, HIGH- PERFORMANCE GLASS PANEL EMBEDDED (GPE) PACKAGES FOR MM-WAVE APPLICATIONS. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/64217

Chicago Manual of Style (16th Edition):

Shi, Tailong. “MODELING, DESIGN, FABRICATION AND DEMONSTRATION OF ULTRA-THIN, HIGH- PERFORMANCE GLASS PANEL EMBEDDED (GPE) PACKAGES FOR MM-WAVE APPLICATIONS.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/64217.

MLA Handbook (7th Edition):

Shi, Tailong. “MODELING, DESIGN, FABRICATION AND DEMONSTRATION OF ULTRA-THIN, HIGH- PERFORMANCE GLASS PANEL EMBEDDED (GPE) PACKAGES FOR MM-WAVE APPLICATIONS.” 2020. Web. 18 Apr 2021.

Vancouver:

Shi T. MODELING, DESIGN, FABRICATION AND DEMONSTRATION OF ULTRA-THIN, HIGH- PERFORMANCE GLASS PANEL EMBEDDED (GPE) PACKAGES FOR MM-WAVE APPLICATIONS. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/64217.

Council of Science Editors:

Shi T. MODELING, DESIGN, FABRICATION AND DEMONSTRATION OF ULTRA-THIN, HIGH- PERFORMANCE GLASS PANEL EMBEDDED (GPE) PACKAGES FOR MM-WAVE APPLICATIONS. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/64217

26. Hwang, Seunghyun Eddy. Characterization and design of embedded passive circuits for applications up to millimeter-wave frequency.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 The goal of the research in this dissertation is to develop techniques for 1) system-on-package integration of passive circuits using ultra-thin advanced polymers called RXP… (more)

Subjects/Keywords: RXP; Bandpass; Organic; TSV; Silicon interposer; Filter; Integrated circuits; Microelectronics; Thin films; Thin-film circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hwang, S. E. (2011). Characterization and design of embedded passive circuits for applications up to millimeter-wave frequency. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/41146

Chicago Manual of Style (16th Edition):

Hwang, Seunghyun Eddy. “Characterization and design of embedded passive circuits for applications up to millimeter-wave frequency.” 2011. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/41146.

MLA Handbook (7th Edition):

Hwang, Seunghyun Eddy. “Characterization and design of embedded passive circuits for applications up to millimeter-wave frequency.” 2011. Web. 18 Apr 2021.

Vancouver:

Hwang SE. Characterization and design of embedded passive circuits for applications up to millimeter-wave frequency. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/41146.

Council of Science Editors:

Hwang SE. Characterization and design of embedded passive circuits for applications up to millimeter-wave frequency. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/41146

27. Barabadi, Banafsheh. Transient Joule heating in nano-scale embedded on-chip interconnects.

Degree: PhD, Mechanical Engineering, 2013, Georgia Tech

 Major challenges in maintaining quality and reliability in today’s microelectronics devices come from the ever increasing level of integration in the device fabrication, as well… (more)

Subjects/Keywords: Joule heating; Interconnects; Nano-scale heat transfer; Multi-scale thermal modeling; Interconnects (Integrated circuit technology); Nanoelectromechanical systems; Heat Transmission

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Barabadi, B. (2013). Transient Joule heating in nano-scale embedded on-chip interconnects. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51786

Chicago Manual of Style (16th Edition):

Barabadi, Banafsheh. “Transient Joule heating in nano-scale embedded on-chip interconnects.” 2013. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/51786.

MLA Handbook (7th Edition):

Barabadi, Banafsheh. “Transient Joule heating in nano-scale embedded on-chip interconnects.” 2013. Web. 18 Apr 2021.

Vancouver:

Barabadi B. Transient Joule heating in nano-scale embedded on-chip interconnects. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/51786.

Council of Science Editors:

Barabadi B. Transient Joule heating in nano-scale embedded on-chip interconnects. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/51786

28. Hsiao, Sen-Wen. Built-in test for performance characterization and calibration of phase-locked loops.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 The objective of this dissertation is to propose circuit architectures and techniques for built-in test and calibration of phase-locked loops. The design of phase-locked loops… (more)

Subjects/Keywords: Phase-locked loop; Built-in test; Built-in self-test; Calibration; Analog sensor; Reference spur; Frequency synthesizers; Telecommunication systems; Phase detectors; Phase-locked loops

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hsiao, S. (2014). Built-in test for performance characterization and calibration of phase-locked loops. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51790

Chicago Manual of Style (16th Edition):

Hsiao, Sen-Wen. “Built-in test for performance characterization and calibration of phase-locked loops.” 2014. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/51790.

MLA Handbook (7th Edition):

Hsiao, Sen-Wen. “Built-in test for performance characterization and calibration of phase-locked loops.” 2014. Web. 18 Apr 2021.

Vancouver:

Hsiao S. Built-in test for performance characterization and calibration of phase-locked loops. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/51790.

Council of Science Editors:

Hsiao S. Built-in test for performance characterization and calibration of phase-locked loops. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51790

29. Jung, Moongon. Low power and reliable design methodologies for 3D ICs.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 The main objective of this dissertation is to explore and develop computer-aided-design methodologies and optimization techniques for reliability, performance, and power of through-silicon-via-based 3D IC… (more)

Subjects/Keywords: 3D IC; TSV; Low power design; Thermo-mechanical reliability; Power delivery; Three-dimensional integrated circuits; Integrated circuits; Integrated circuits Design and construction

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jung, M. (2014). Low power and reliable design methodologies for 3D ICs. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51824

Chicago Manual of Style (16th Edition):

Jung, Moongon. “Low power and reliable design methodologies for 3D ICs.” 2014. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/51824.

MLA Handbook (7th Edition):

Jung, Moongon. “Low power and reliable design methodologies for 3D ICs.” 2014. Web. 18 Apr 2021.

Vancouver:

Jung M. Low power and reliable design methodologies for 3D ICs. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/51824.

Council of Science Editors:

Jung M. Low power and reliable design methodologies for 3D ICs. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51824

30. Tzou, Nicholas. Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 Cost reduction has been and will continue to be a primary driving force in the evolution of hardware design and associated technologies. The objective of… (more)

Subjects/Keywords: Low-cost; Sub-Nyquist; Algorithm; Hardware; Measurement; Multi-rate; Band-interleaved; Undersampling; Jitter; Crosstalk separation; Broadband communication systems Equipment and supplies; Algorithms

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tzou, N. (2014). Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51876

Chicago Manual of Style (16th Edition):

Tzou, Nicholas. “Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement.” 2014. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/51876.

MLA Handbook (7th Edition):

Tzou, Nicholas. “Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement.” 2014. Web. 18 Apr 2021.

Vancouver:

Tzou N. Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/51876.

Council of Science Editors:

Tzou N. Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51876

[1] [2] [3]

.