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You searched for +publisher:"Georgia Tech" +contributor:("Sitaraman, Suresh"). Showing records 1 – 30 of 100 total matches.

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1. Menezes, Gary. Modeling, design, fabrication and characterization of glass package-to-PCB interconnections.

Degree: MS, Electrical and Computer Engineering, 2013, Georgia Tech

 Emerging I/O density and bandwidth requirements are driving packages to low-CTE silicon, glass and organic substrates for higher wiring density and reliability of interconnections and… (more)

Subjects/Keywords: Glass package; BGA; Large package; Electronic packaging; Computer input-output equipment; Interconnects (Integrated circuit technology)

…DRAMs, RF and MEMS cost effectively. Georgia Tech PRC has been pioneering an alternative… 

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APA (6th Edition):

Menezes, G. (2013). Modeling, design, fabrication and characterization of glass package-to-PCB interconnections. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51781

Chicago Manual of Style (16th Edition):

Menezes, Gary. “Modeling, design, fabrication and characterization of glass package-to-PCB interconnections.” 2013. Masters Thesis, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/51781.

MLA Handbook (7th Edition):

Menezes, Gary. “Modeling, design, fabrication and characterization of glass package-to-PCB interconnections.” 2013. Web. 28 Feb 2020.

Vancouver:

Menezes G. Modeling, design, fabrication and characterization of glass package-to-PCB interconnections. [Internet] [Masters thesis]. Georgia Tech; 2013. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/51781.

Council of Science Editors:

Menezes G. Modeling, design, fabrication and characterization of glass package-to-PCB interconnections. [Masters Thesis]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/51781


Georgia Tech

2. Krieger, William E. R. Cohesive zone modeling for predicting interfacial delamination in microelectronic packaging.

Degree: MS, Mechanical Engineering, 2014, Georgia Tech

 Multi-layered electronic packages increase in complexity with demands for functionality. Interfacial delamination remains a prominent failure mechanism due to mismatch of coefficient of thermal expansion… (more)

Subjects/Keywords: Interfacial delamination; Cohesive zone modeling; Finite element modeling; Critical strain energy release rate; Microelectronic packaging; Composite materials Delamination; Microelectronics Research; Microelectronics

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APA (6th Edition):

Krieger, W. E. R. (2014). Cohesive zone modeling for predicting interfacial delamination in microelectronic packaging. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51888

Chicago Manual of Style (16th Edition):

Krieger, William E R. “Cohesive zone modeling for predicting interfacial delamination in microelectronic packaging.” 2014. Masters Thesis, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/51888.

MLA Handbook (7th Edition):

Krieger, William E R. “Cohesive zone modeling for predicting interfacial delamination in microelectronic packaging.” 2014. Web. 28 Feb 2020.

Vancouver:

Krieger WER. Cohesive zone modeling for predicting interfacial delamination in microelectronic packaging. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/51888.

Council of Science Editors:

Krieger WER. Cohesive zone modeling for predicting interfacial delamination in microelectronic packaging. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51888


Georgia Tech

3. Kwatra, Abhishek. Effect of temperature and humidity conditioning on mold compound/copper interfacial fracture and the associated cohesive zone models.

Degree: MS, Mechanical Engineering, 2016, Georgia Tech

 Microelectronic packages consist of multilayered structures made of dissimilar materials. Interfacial delamination is a common failure mechanism present in microelectronic packages due to the mismatch… (more)

Subjects/Keywords: Mechanical reliability; Interfacial fracture mechanics; Microelectronic packaging; Finite element modeling

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APA (6th Edition):

Kwatra, A. (2016). Effect of temperature and humidity conditioning on mold compound/copper interfacial fracture and the associated cohesive zone models. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59166

Chicago Manual of Style (16th Edition):

Kwatra, Abhishek. “Effect of temperature and humidity conditioning on mold compound/copper interfacial fracture and the associated cohesive zone models.” 2016. Masters Thesis, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/59166.

MLA Handbook (7th Edition):

Kwatra, Abhishek. “Effect of temperature and humidity conditioning on mold compound/copper interfacial fracture and the associated cohesive zone models.” 2016. Web. 28 Feb 2020.

Vancouver:

Kwatra A. Effect of temperature and humidity conditioning on mold compound/copper interfacial fracture and the associated cohesive zone models. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/59166.

Council of Science Editors:

Kwatra A. Effect of temperature and humidity conditioning on mold compound/copper interfacial fracture and the associated cohesive zone models. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/59166


Georgia Tech

4. Sulkis, Michael C. Characterization of encapsulant and edge seal materials for flexible solar cell packaging.

Degree: MS, Mechanical Engineering, 2019, Georgia Tech

 Flexible photovoltaic devices have the potential to be an attractive alternative to conventional PV technologies if they can be made environmentally stable and reliable. Therefore… (more)

Subjects/Keywords: Encapsulation; Edge seal; Photovoltaics; PV; Solar; Cells; Mechanical; Georgia; Tech; Adhesion

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APA (6th Edition):

Sulkis, M. C. (2019). Characterization of encapsulant and edge seal materials for flexible solar cell packaging. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61307

Chicago Manual of Style (16th Edition):

Sulkis, Michael C. “Characterization of encapsulant and edge seal materials for flexible solar cell packaging.” 2019. Masters Thesis, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/61307.

MLA Handbook (7th Edition):

Sulkis, Michael C. “Characterization of encapsulant and edge seal materials for flexible solar cell packaging.” 2019. Web. 28 Feb 2020.

Vancouver:

Sulkis MC. Characterization of encapsulant and edge seal materials for flexible solar cell packaging. [Internet] [Masters thesis]. Georgia Tech; 2019. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/61307.

Council of Science Editors:

Sulkis MC. Characterization of encapsulant and edge seal materials for flexible solar cell packaging. [Masters Thesis]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/61307


Georgia Tech

5. Ginga, Nicholas J. On-chip dielectric cohesive fracture characterization and mitigation investigation through off-chip carbon nanotube interconnects.

Degree: PhD, Mechanical Engineering, 2014, Georgia Tech

 The cohesive fracture of thin films is a concern for the reliability of many devices in microelectronics, MEMS, photovoltaics, and other applications. In microelectronic packaging… (more)

Subjects/Keywords: Thin film; MEMs; CNT; Fracture; Photolithography; Material characterization; Modulus; Carbon nanotubes; Microelectronics; Reliability; Finite element analysis; Interconnects

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APA (6th Edition):

Ginga, N. J. (2014). On-chip dielectric cohesive fracture characterization and mitigation investigation through off-chip carbon nanotube interconnects. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52225

Chicago Manual of Style (16th Edition):

Ginga, Nicholas J. “On-chip dielectric cohesive fracture characterization and mitigation investigation through off-chip carbon nanotube interconnects.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/52225.

MLA Handbook (7th Edition):

Ginga, Nicholas J. “On-chip dielectric cohesive fracture characterization and mitigation investigation through off-chip carbon nanotube interconnects.” 2014. Web. 28 Feb 2020.

Vancouver:

Ginga NJ. On-chip dielectric cohesive fracture characterization and mitigation investigation through off-chip carbon nanotube interconnects. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/52225.

Council of Science Editors:

Ginga NJ. On-chip dielectric cohesive fracture characterization and mitigation investigation through off-chip carbon nanotube interconnects. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/52225


Georgia Tech

6. Raghavan, Sathyanarayanan. Experimental and theoretical study of on-chip back-end-of-line (BEOL) stack fracture during flip-chip reflow assembly.

Degree: PhD, Mechanical Engineering, 2014, Georgia Tech

 With continued feature size reduction in microelectronics and with more than a billion transistors on a single integrated circuit (IC), on-chip interconnection has become a… (more)

Subjects/Keywords: DCB; BEOL fracture; Ultra low-k fracture;

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APA (6th Edition):

Raghavan, S. (2014). Experimental and theoretical study of on-chip back-end-of-line (BEOL) stack fracture during flip-chip reflow assembly. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54298

Chicago Manual of Style (16th Edition):

Raghavan, Sathyanarayanan. “Experimental and theoretical study of on-chip back-end-of-line (BEOL) stack fracture during flip-chip reflow assembly.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/54298.

MLA Handbook (7th Edition):

Raghavan, Sathyanarayanan. “Experimental and theoretical study of on-chip back-end-of-line (BEOL) stack fracture during flip-chip reflow assembly.” 2014. Web. 28 Feb 2020.

Vancouver:

Raghavan S. Experimental and theoretical study of on-chip back-end-of-line (BEOL) stack fracture during flip-chip reflow assembly. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/54298.

Council of Science Editors:

Raghavan S. Experimental and theoretical study of on-chip back-end-of-line (BEOL) stack fracture during flip-chip reflow assembly. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/54298


Georgia Tech

7. Song, Taigon. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The objective of this research is to study and develop computer-aided-design (CAD) methodologies for reliability in chip-package co-designed three-dimensional integrated circuit (3D IC) systems. 3D… (more)

Subjects/Keywords: 3D IC; Design Methodologies

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APA (6th Edition):

Song, T. (2015). CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56188

Chicago Manual of Style (16th Edition):

Song, Taigon. “CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/56188.

MLA Handbook (7th Edition):

Song, Taigon. “CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.” 2015. Web. 28 Feb 2020.

Vancouver:

Song T. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/56188.

Council of Science Editors:

Song T. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56188


Georgia Tech

8. Tong, Jialing. Electrical modeling, design and characterization of tapered through-package-vias in glass interposers for high-performance applications.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 Three dimensional (3D) packaging technologies are being developed to address the escalating demand for data traffic at lowest power consumption, smallest form factors, and lowest… (more)

Subjects/Keywords: Through-package vias; Glass interposers

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APA (6th Edition):

Tong, J. (2016). Electrical modeling, design and characterization of tapered through-package-vias in glass interposers for high-performance applications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56242

Chicago Manual of Style (16th Edition):

Tong, Jialing. “Electrical modeling, design and characterization of tapered through-package-vias in glass interposers for high-performance applications.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/56242.

MLA Handbook (7th Edition):

Tong, Jialing. “Electrical modeling, design and characterization of tapered through-package-vias in glass interposers for high-performance applications.” 2016. Web. 28 Feb 2020.

Vancouver:

Tong J. Electrical modeling, design and characterization of tapered through-package-vias in glass interposers for high-performance applications. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/56242.

Council of Science Editors:

Tong J. Electrical modeling, design and characterization of tapered through-package-vias in glass interposers for high-performance applications. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56242


Georgia Tech

9. Chou, Chia Te. Low loss and high tolerance out-of-plane single-mode optical interconnections in glass interposers.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The specific focus of this dissertation research is to design and demonstrate low loss and high tolerance out-of-plane single-mode fiber-to-chip optical interconnections in glass to… (more)

Subjects/Keywords: Optoelectronics packaging; Optical waveguide; 3D micro-structuring

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APA (6th Edition):

Chou, C. T. (2016). Low loss and high tolerance out-of-plane single-mode optical interconnections in glass interposers. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56318

Chicago Manual of Style (16th Edition):

Chou, Chia Te. “Low loss and high tolerance out-of-plane single-mode optical interconnections in glass interposers.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/56318.

MLA Handbook (7th Edition):

Chou, Chia Te. “Low loss and high tolerance out-of-plane single-mode optical interconnections in glass interposers.” 2016. Web. 28 Feb 2020.

Vancouver:

Chou CT. Low loss and high tolerance out-of-plane single-mode optical interconnections in glass interposers. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/56318.

Council of Science Editors:

Chou CT. Low loss and high tolerance out-of-plane single-mode optical interconnections in glass interposers. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56318


Georgia Tech

10. Gallé, William Preston. MEMS-based fabrication of power electronics components for advanced power converters.

Degree: PhD, Electrical and Computer Engineering, 2012, Georgia Tech

 Fabrication technology, based on MEMS processes, for constructing components for use in switched-mode power supplies are developed and presented. Capacitors, magnetic cores, and inductors based… (more)

Subjects/Keywords: Power converters; Capacitors; Inductors; Electroplating; MEMS; Microelectromechanical systems; DC-to-DC converters; Switching power supplies; Electric inductors

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APA (6th Edition):

Gallé, W. P. (2012). MEMS-based fabrication of power electronics components for advanced power converters. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/45821

Chicago Manual of Style (16th Edition):

Gallé, William Preston. “MEMS-based fabrication of power electronics components for advanced power converters.” 2012. Doctoral Dissertation, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/45821.

MLA Handbook (7th Edition):

Gallé, William Preston. “MEMS-based fabrication of power electronics components for advanced power converters.” 2012. Web. 28 Feb 2020.

Vancouver:

Gallé WP. MEMS-based fabrication of power electronics components for advanced power converters. [Internet] [Doctoral dissertation]. Georgia Tech; 2012. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/45821.

Council of Science Editors:

Gallé WP. MEMS-based fabrication of power electronics components for advanced power converters. [Doctoral Dissertation]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/45821


Georgia Tech

11. Suzuki, Yuya. Ultra-thin polymer dielectric materials and ultra-small via and trench processes for 20micron bump pitch re-distribution layer (RDL) structures for high density packages.

Degree: PhD, Materials Science and Engineering, 2017, Georgia Tech

 Higher interconnect density between multiple chips is required because of the need of the high bandwidth data transmission for many electronic systems, such as smart… (more)

Subjects/Keywords: Polymer dielectric materials; Polymer design; Micro-via; Embedded trench; Laser processing; Cutting planarization

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APA (6th Edition):

Suzuki, Y. (2017). Ultra-thin polymer dielectric materials and ultra-small via and trench processes for 20micron bump pitch re-distribution layer (RDL) structures for high density packages. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60654

Chicago Manual of Style (16th Edition):

Suzuki, Yuya. “Ultra-thin polymer dielectric materials and ultra-small via and trench processes for 20micron bump pitch re-distribution layer (RDL) structures for high density packages.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/60654.

MLA Handbook (7th Edition):

Suzuki, Yuya. “Ultra-thin polymer dielectric materials and ultra-small via and trench processes for 20micron bump pitch re-distribution layer (RDL) structures for high density packages.” 2017. Web. 28 Feb 2020.

Vancouver:

Suzuki Y. Ultra-thin polymer dielectric materials and ultra-small via and trench processes for 20micron bump pitch re-distribution layer (RDL) structures for high density packages. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/60654.

Council of Science Editors:

Suzuki Y. Ultra-thin polymer dielectric materials and ultra-small via and trench processes for 20micron bump pitch re-distribution layer (RDL) structures for high density packages. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/60654


Georgia Tech

12. Asrar, Pouya. FLOW BOILING OF R245FA IN MICROGAPS WITH STAGGERED CIRCULAR AND HYDROFOIL PIN FINS.

Degree: PhD, Mechanical Engineering, 2018, Georgia Tech

 Dielectric fluids, including refrigerants, are electrically inert and are a good candidate as working fluid in two-phase microsystem cooling applications. In this study, R245fa is… (more)

Subjects/Keywords: Flow Boiling; Heat Transfer; Microgap; Two-Phase Heat Transfer Coefficient

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APA (6th Edition):

Asrar, P. (2018). FLOW BOILING OF R245FA IN MICROGAPS WITH STAGGERED CIRCULAR AND HYDROFOIL PIN FINS. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62234

Chicago Manual of Style (16th Edition):

Asrar, Pouya. “FLOW BOILING OF R245FA IN MICROGAPS WITH STAGGERED CIRCULAR AND HYDROFOIL PIN FINS.” 2018. Doctoral Dissertation, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/62234.

MLA Handbook (7th Edition):

Asrar, Pouya. “FLOW BOILING OF R245FA IN MICROGAPS WITH STAGGERED CIRCULAR AND HYDROFOIL PIN FINS.” 2018. Web. 28 Feb 2020.

Vancouver:

Asrar P. FLOW BOILING OF R245FA IN MICROGAPS WITH STAGGERED CIRCULAR AND HYDROFOIL PIN FINS. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/62234.

Council of Science Editors:

Asrar P. FLOW BOILING OF R245FA IN MICROGAPS WITH STAGGERED CIRCULAR AND HYDROFOIL PIN FINS. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/62234


Georgia Tech

13. Jo, Paul K. Polylithic Integration of Heterogeneous Multi-die Enabled by Compressible Microinterconnects.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 This research proposes and demonstrate 1) a new compliant interconnect that can provide cost-effective and simple fabrication process and allow high-degree of freedom in design… (more)

Subjects/Keywords: Compliant interconnect; Heterogeneous integration; Package; 2.5D; 3D; System-level integration; System-in-Package

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APA (6th Edition):

Jo, P. K. (2019). Polylithic Integration of Heterogeneous Multi-die Enabled by Compressible Microinterconnects. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62301

Chicago Manual of Style (16th Edition):

Jo, Paul K. “Polylithic Integration of Heterogeneous Multi-die Enabled by Compressible Microinterconnects.” 2019. Doctoral Dissertation, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/62301.

MLA Handbook (7th Edition):

Jo, Paul K. “Polylithic Integration of Heterogeneous Multi-die Enabled by Compressible Microinterconnects.” 2019. Web. 28 Feb 2020.

Vancouver:

Jo PK. Polylithic Integration of Heterogeneous Multi-die Enabled by Compressible Microinterconnects. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/62301.

Council of Science Editors:

Jo PK. Polylithic Integration of Heterogeneous Multi-die Enabled by Compressible Microinterconnects. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62301

14. Liang, Jiaxing. Microfabricated thin silicon vapor chambers for low profile thermal management.

Degree: MS, Mechanical Engineering, 2017, Georgia Tech

 Portable electronics, such as smartphones, tablets, and ultrabooks are innovating rapidly. They are becoming as powerful as desktop computers, and incorporating multiple functionalities enabled through… (more)

Subjects/Keywords: Vapor chamber; Heat pipe; Wick; Low profile thermal management; Portable electronics; Interposer; Vapor chamber charging

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APA (6th Edition):

Liang, J. (2017). Microfabricated thin silicon vapor chambers for low profile thermal management. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60114

Chicago Manual of Style (16th Edition):

Liang, Jiaxing. “Microfabricated thin silicon vapor chambers for low profile thermal management.” 2017. Masters Thesis, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/60114.

MLA Handbook (7th Edition):

Liang, Jiaxing. “Microfabricated thin silicon vapor chambers for low profile thermal management.” 2017. Web. 28 Feb 2020.

Vancouver:

Liang J. Microfabricated thin silicon vapor chambers for low profile thermal management. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/60114.

Council of Science Editors:

Liang J. Microfabricated thin silicon vapor chambers for low profile thermal management. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/60114

15. Choudhury, Abhishek. Chip-last embedded low temperature interconnections with chip-first dimensions.

Degree: MS, Materials Science and Engineering, 2010, Georgia Tech

 Small form-factor packages with high integration density are driving the innovations in chip-to-package interconnections. Metallurgical interconnections have evolved from the conventional eutectic and lead-free solders… (more)

Subjects/Keywords: Low temperature; Reliability; NCF; Adhesive; Copper bump; Fine pitch; Flip chip; Embedded active; Interconnections; Microelectronic packaging; Interconnects (Integrated circuit technology); Copper; Metal bonding

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APA (6th Edition):

Choudhury, A. (2010). Chip-last embedded low temperature interconnections with chip-first dimensions. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/37104

Chicago Manual of Style (16th Edition):

Choudhury, Abhishek. “Chip-last embedded low temperature interconnections with chip-first dimensions.” 2010. Masters Thesis, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/37104.

MLA Handbook (7th Edition):

Choudhury, Abhishek. “Chip-last embedded low temperature interconnections with chip-first dimensions.” 2010. Web. 28 Feb 2020.

Vancouver:

Choudhury A. Chip-last embedded low temperature interconnections with chip-first dimensions. [Internet] [Masters thesis]. Georgia Tech; 2010. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/37104.

Council of Science Editors:

Choudhury A. Chip-last embedded low temperature interconnections with chip-first dimensions. [Masters Thesis]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/37104

16. McCaslin, Luke. Methodology for predicting microelectronic substrate warpage incorporating copper trace pattern characteristics.

Degree: MS, Mechanical Engineering, 2008, Georgia Tech

 The current trend in electronics manufacturing is to decrease the size of electronic components while attempting to increase processing power and performance. This is leading… (more)

Subjects/Keywords: Finite element modeling; Microelectronics packaging; Metals Thermomechanical properties; Copper Transport properties; Copper Thermal conductivity; Microelectronic packaging; Electronic packaging; Surface mount technology

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APA (6th Edition):

McCaslin, L. (2008). Methodology for predicting microelectronic substrate warpage incorporating copper trace pattern characteristics. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/24641

Chicago Manual of Style (16th Edition):

McCaslin, Luke. “Methodology for predicting microelectronic substrate warpage incorporating copper trace pattern characteristics.” 2008. Masters Thesis, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/24641.

MLA Handbook (7th Edition):

McCaslin, Luke. “Methodology for predicting microelectronic substrate warpage incorporating copper trace pattern characteristics.” 2008. Web. 28 Feb 2020.

Vancouver:

McCaslin L. Methodology for predicting microelectronic substrate warpage incorporating copper trace pattern characteristics. [Internet] [Masters thesis]. Georgia Tech; 2008. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/24641.

Council of Science Editors:

McCaslin L. Methodology for predicting microelectronic substrate warpage incorporating copper trace pattern characteristics. [Masters Thesis]. Georgia Tech; 2008. Available from: http://hdl.handle.net/1853/24641

17. Jones, Jason Patrick. Electro-thermo-mechanical characterization of stress development in AlGaN/GaN HEMTs under RF operating conditions.

Degree: MS, Mechanical Engineering, 2015, Georgia Tech

 Gallium nitride (GaN) based high electron mobility transistors (HEMTs) offer numerous benefits for both direct current (DC) and radio frequency (RF) power technology due to… (more)

Subjects/Keywords: Algan; Gan; Transient; Pulsed; Microelectronics; High; Electron; Mobility; Transistor; Hemt; Hfet; Gallium; Nitride; Aluminum

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APA (6th Edition):

Jones, J. P. (2015). Electro-thermo-mechanical characterization of stress development in AlGaN/GaN HEMTs under RF operating conditions. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53528

Chicago Manual of Style (16th Edition):

Jones, Jason Patrick. “Electro-thermo-mechanical characterization of stress development in AlGaN/GaN HEMTs under RF operating conditions.” 2015. Masters Thesis, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/53528.

MLA Handbook (7th Edition):

Jones, Jason Patrick. “Electro-thermo-mechanical characterization of stress development in AlGaN/GaN HEMTs under RF operating conditions.” 2015. Web. 28 Feb 2020.

Vancouver:

Jones JP. Electro-thermo-mechanical characterization of stress development in AlGaN/GaN HEMTs under RF operating conditions. [Internet] [Masters thesis]. Georgia Tech; 2015. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/53528.

Council of Science Editors:

Jones JP. Electro-thermo-mechanical characterization of stress development in AlGaN/GaN HEMTs under RF operating conditions. [Masters Thesis]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53528

18. Bhat, Anirudh. Response of multi-path compliant interconnects subjected to drop and impact loading.

Degree: MS, Mechanical Engineering, 2012, Georgia Tech

 Conventional solder balls used in microelectronic packaging suffer from thermo- mechanical damage due to difference in coefficient of thermal expansion between the die and the… (more)

Subjects/Keywords: Finite-element simulation; Drop testing; Compliant interconnects; Input-G method; Stereolithography; Interconnects (Integrated circuit technology); Microelectronic packaging; Shock (Mechanics); Impact

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APA (6th Edition):

Bhat, A. (2012). Response of multi-path compliant interconnects subjected to drop and impact loading. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/50132

Chicago Manual of Style (16th Edition):

Bhat, Anirudh. “Response of multi-path compliant interconnects subjected to drop and impact loading.” 2012. Masters Thesis, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/50132.

MLA Handbook (7th Edition):

Bhat, Anirudh. “Response of multi-path compliant interconnects subjected to drop and impact loading.” 2012. Web. 28 Feb 2020.

Vancouver:

Bhat A. Response of multi-path compliant interconnects subjected to drop and impact loading. [Internet] [Masters thesis]. Georgia Tech; 2012. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/50132.

Council of Science Editors:

Bhat A. Response of multi-path compliant interconnects subjected to drop and impact loading. [Masters Thesis]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/50132

19. McCann, Scott R. Experimental and theoretical assessment of thin glass panels as interposers for microelectronic packages.

Degree: MS, Mechanical Engineering, 2014, Georgia Tech

 As the microelectronic industry moves toward stacking of dies to achieve greater performance and smaller footprint, there are several reliability concerns when assembling the stacked… (more)

Subjects/Keywords: Warpage; Shadow moire; Finite element; Process modeling; Microelectronic packaging; Glass interposer; Microelectronics; Finite element method; Electronic packaging

…Research Center at Georgia Tech is investigating glass as a packaging material through several… …Packaging Research Center at Georgia Tech. 4.2 Die Assembly with Glass Interposer Before the die… 

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APA (6th Edition):

McCann, S. R. (2014). Experimental and theoretical assessment of thin glass panels as interposers for microelectronic packages. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51889

Chicago Manual of Style (16th Edition):

McCann, Scott R. “Experimental and theoretical assessment of thin glass panels as interposers for microelectronic packages.” 2014. Masters Thesis, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/51889.

MLA Handbook (7th Edition):

McCann, Scott R. “Experimental and theoretical assessment of thin glass panels as interposers for microelectronic packages.” 2014. Web. 28 Feb 2020.

Vancouver:

McCann SR. Experimental and theoretical assessment of thin glass panels as interposers for microelectronic packages. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/51889.

Council of Science Editors:

McCann SR. Experimental and theoretical assessment of thin glass panels as interposers for microelectronic packages. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51889


Georgia Tech

20. Tunga, Krishna Rajaram. Study of Sn-Ag-Cu reliability through material microstructure evolution and laser moire interferometry.

Degree: PhD, Mechanical Engineering, 2008, Georgia Tech

 This research aims to understand the reliability of Sn-Ag-Cu solder interconnects used in plastic ball grid array (PBGA) packages using microstructure evolution, laser moiré interferometry… (more)

Subjects/Keywords: Fatigue life prediction; Solder joint fatigue; Microstructure evolution; SAC405; SAC305; Laser moire interferometry; Finite element modeling; Lead-free solders; Moiré method; Ball grid array technology; Electronic packaging

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APA (6th Edition):

Tunga, K. R. (2008). Study of Sn-Ag-Cu reliability through material microstructure evolution and laser moire interferometry. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/24805

Chicago Manual of Style (16th Edition):

Tunga, Krishna Rajaram. “Study of Sn-Ag-Cu reliability through material microstructure evolution and laser moire interferometry.” 2008. Doctoral Dissertation, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/24805.

MLA Handbook (7th Edition):

Tunga, Krishna Rajaram. “Study of Sn-Ag-Cu reliability through material microstructure evolution and laser moire interferometry.” 2008. Web. 28 Feb 2020.

Vancouver:

Tunga KR. Study of Sn-Ag-Cu reliability through material microstructure evolution and laser moire interferometry. [Internet] [Doctoral dissertation]. Georgia Tech; 2008. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/24805.

Council of Science Editors:

Tunga KR. Study of Sn-Ag-Cu reliability through material microstructure evolution and laser moire interferometry. [Doctoral Dissertation]. Georgia Tech; 2008. Available from: http://hdl.handle.net/1853/24805

21. Crnkic, Edin. Geometry guided phase transition pathway and stable structure search for crystals.

Degree: MS, Mechanical Engineering, 2012, Georgia Tech

 Recently a periodic surface model was developed to assist geometric construction in computer-aided nano-design. This implicit surface model helps create super-porous nano structures parametrically and… (more)

Subjects/Keywords: Phase transition; Implicit modeling; Computer-aided nano design; Global optimization; Nanomanufacturing; Nanomaterials; Nanocrystals; Simulated annealing (Mathematics); Mathematical optimization; Phase transformations (Statistical physics)

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APA (6th Edition):

Crnkic, E. (2012). Geometry guided phase transition pathway and stable structure search for crystals. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/44760

Chicago Manual of Style (16th Edition):

Crnkic, Edin. “Geometry guided phase transition pathway and stable structure search for crystals.” 2012. Masters Thesis, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/44760.

MLA Handbook (7th Edition):

Crnkic, Edin. “Geometry guided phase transition pathway and stable structure search for crystals.” 2012. Web. 28 Feb 2020.

Vancouver:

Crnkic E. Geometry guided phase transition pathway and stable structure search for crystals. [Internet] [Masters thesis]. Georgia Tech; 2012. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/44760.

Council of Science Editors:

Crnkic E. Geometry guided phase transition pathway and stable structure search for crystals. [Masters Thesis]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/44760

22. Singh, Bhupender. Modeling, design, fabrication and reliability characterization of ultra-thin glass BGA package-to-board interconnections.

Degree: MS, Materials Science and Engineering, 2016, Georgia Tech

 Recent trends to miniaturized systems such as smartphones and wearables, as well as the rise of autonomous vehicles relying on all-electric and smart in-car systems,… (more)

Subjects/Keywords: Board-level reliability; Glass packages; BGA balling; Thermal cycling; Drop testing

…scaling alone. A novel system scaling approach has been proposed by Georgia Tech to address… …Packaging Research Center at Georgia Tech has been pioneering System-on-Package (SOP) to… …demonstrated to effectively improve fatigue life of solders by 30-50% [11, 12]. Georgia… …Tech PRC and its industry partner Namics Corporation Inc. have recently extended this concept… 

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APA (6th Edition):

Singh, B. (2016). Modeling, design, fabrication and reliability characterization of ultra-thin glass BGA package-to-board interconnections. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55031

Chicago Manual of Style (16th Edition):

Singh, Bhupender. “Modeling, design, fabrication and reliability characterization of ultra-thin glass BGA package-to-board interconnections.” 2016. Masters Thesis, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/55031.

MLA Handbook (7th Edition):

Singh, Bhupender. “Modeling, design, fabrication and reliability characterization of ultra-thin glass BGA package-to-board interconnections.” 2016. Web. 28 Feb 2020.

Vancouver:

Singh B. Modeling, design, fabrication and reliability characterization of ultra-thin glass BGA package-to-board interconnections. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/55031.

Council of Science Editors:

Singh B. Modeling, design, fabrication and reliability characterization of ultra-thin glass BGA package-to-board interconnections. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55031

23. Watanabe, Narumi. Computational and experimental investigation of reinforced polymers for material extrusion additive manufacturing.

Degree: MS, Mechanical Engineering, 2016, Georgia Tech

 Among the most widely used additive manufacturing technologies is the material extrusion based process, in which a filament of thermoplastic material is liquefied and extruded… (more)

Subjects/Keywords: Additive manufacturing; Material extrusion; Fused deposition modeling; Process simulation model; Polypropylene; Polymer; Warpage

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APA (6th Edition):

Watanabe, N. (2016). Computational and experimental investigation of reinforced polymers for material extrusion additive manufacturing. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56374

Chicago Manual of Style (16th Edition):

Watanabe, Narumi. “Computational and experimental investigation of reinforced polymers for material extrusion additive manufacturing.” 2016. Masters Thesis, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/56374.

MLA Handbook (7th Edition):

Watanabe, Narumi. “Computational and experimental investigation of reinforced polymers for material extrusion additive manufacturing.” 2016. Web. 28 Feb 2020.

Vancouver:

Watanabe N. Computational and experimental investigation of reinforced polymers for material extrusion additive manufacturing. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/56374.

Council of Science Editors:

Watanabe N. Computational and experimental investigation of reinforced polymers for material extrusion additive manufacturing. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56374

24. Chung, Philip Y. Vibration analysis of electroplated copper compliant interconnects.

Degree: MS, Mechanical Engineering, 2017, Georgia Tech

 Microelectronic packaging interconnects are subjected to mechanical damage due to thermal and power cycles, drop impact shock, and various vibration loads during application. As traditional… (more)

Subjects/Keywords: Random vibration; Electroplated copper; Compliant interconnect

…been studied, including the copper microwire array developed by Georgia Tech presented in… …4 proposed by Georgia Tech in 2002 [35] and the Microsprings developed by Xerox… …Georgia Tech. This includes the β–Helix [41], G–Helix [42], and FlexConnects… …research at Georgia Tech. 13 2.1.4. 3-Arc-Fan Compliant Interconnect The 3-Arc-Fan, or… 

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APA (6th Edition):

Chung, P. Y. (2017). Vibration analysis of electroplated copper compliant interconnects. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58321

Chicago Manual of Style (16th Edition):

Chung, Philip Y. “Vibration analysis of electroplated copper compliant interconnects.” 2017. Masters Thesis, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/58321.

MLA Handbook (7th Edition):

Chung, Philip Y. “Vibration analysis of electroplated copper compliant interconnects.” 2017. Web. 28 Feb 2020.

Vancouver:

Chung PY. Vibration analysis of electroplated copper compliant interconnects. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/58321.

Council of Science Editors:

Chung PY. Vibration analysis of electroplated copper compliant interconnects. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58321

25. Song, Yaqin. Thermal annealing and mechanical characterization study of electroplated copper in silicon trenches.

Degree: MS, Mechanical Engineering, 2017, Georgia Tech

 Microelectronic systems continue to move to towards 3-D integration to meet the increasing demands, Through-Silicon Vias (TSVs) play an important role in interconnecting stacked silicon… (more)

Subjects/Keywords: TSV; Copper

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APA (6th Edition):

Song, Y. (2017). Thermal annealing and mechanical characterization study of electroplated copper in silicon trenches. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58340

Chicago Manual of Style (16th Edition):

Song, Yaqin. “Thermal annealing and mechanical characterization study of electroplated copper in silicon trenches.” 2017. Masters Thesis, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/58340.

MLA Handbook (7th Edition):

Song, Yaqin. “Thermal annealing and mechanical characterization study of electroplated copper in silicon trenches.” 2017. Web. 28 Feb 2020.

Vancouver:

Song Y. Thermal annealing and mechanical characterization study of electroplated copper in silicon trenches. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/58340.

Council of Science Editors:

Song Y. Thermal annealing and mechanical characterization study of electroplated copper in silicon trenches. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58340

26. Jayaram, Vidya. Modeling, design and demonstration of large 2.5D glass BGA packages for balanced chip-and-board-level reliability.

Degree: MS, Materials Science and Engineering, 2017, Georgia Tech

 Transistor scaling, driven by Moore’s Law, has enabled the integration of billions of transistors on a single integrated chip (IC); thereby enabling rapid miniaturization of… (more)

Subjects/Keywords: 2.5D; Glass BGA package; System-level reliability; Warpage mitigation; Finite-element analysis

…by Georgia Tech PRC, relies on co-integration of multiple electronic functions on a package… …Georgia Tech has recently pioneered glass as an alternative substrate technology overcoming the… …circumferential polymer collars. Georgia Tech PRC, along with its industry partner Namics Corporation… 

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APA (6th Edition):

Jayaram, V. (2017). Modeling, design and demonstration of large 2.5D glass BGA packages for balanced chip-and-board-level reliability. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58342

Chicago Manual of Style (16th Edition):

Jayaram, Vidya. “Modeling, design and demonstration of large 2.5D glass BGA packages for balanced chip-and-board-level reliability.” 2017. Masters Thesis, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/58342.

MLA Handbook (7th Edition):

Jayaram, Vidya. “Modeling, design and demonstration of large 2.5D glass BGA packages for balanced chip-and-board-level reliability.” 2017. Web. 28 Feb 2020.

Vancouver:

Jayaram V. Modeling, design and demonstration of large 2.5D glass BGA packages for balanced chip-and-board-level reliability. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/58342.

Council of Science Editors:

Jayaram V. Modeling, design and demonstration of large 2.5D glass BGA packages for balanced chip-and-board-level reliability. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58342

27. Zhao, Changxuan. Real-time monitoring of exposure controlled projection lithography (ECPL) process.

Degree: MS, Mechanical Engineering, 2017, Georgia Tech

 Exposure Controlled Projection Lithography (ECPL) is a stereolithographic based additive manufacturing process in which photopolymer resin is used to fabricate lens shaped features. During this… (more)

Subjects/Keywords: Stereolithography; Real-time monitoring; Additive manufacturing; Interferometry

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APA (6th Edition):

Zhao, C. (2017). Real-time monitoring of exposure controlled projection lithography (ECPL) process. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58725

Chicago Manual of Style (16th Edition):

Zhao, Changxuan. “Real-time monitoring of exposure controlled projection lithography (ECPL) process.” 2017. Masters Thesis, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/58725.

MLA Handbook (7th Edition):

Zhao, Changxuan. “Real-time monitoring of exposure controlled projection lithography (ECPL) process.” 2017. Web. 28 Feb 2020.

Vancouver:

Zhao C. Real-time monitoring of exposure controlled projection lithography (ECPL) process. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/58725.

Council of Science Editors:

Zhao C. Real-time monitoring of exposure controlled projection lithography (ECPL) process. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58725


Georgia Tech

28. Rudraraju, Anirudh V. Digital data processing and computational design for large area maskless photopolymerization.

Degree: PhD, Mechanical Engineering, 2013, Georgia Tech

 Large Area Maskless Photopolymerization (LAMP) is a novel additive manufacturing technology currently being developed at Georgia Tech in collaboration with the University of Michigan at… (more)

Subjects/Keywords: Additive manufacturing; Direct digital manufacturing; 3D printing; Rapid prototyping

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APA (6th Edition):

Rudraraju, A. V. (2013). Digital data processing and computational design for large area maskless photopolymerization. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52930

Chicago Manual of Style (16th Edition):

Rudraraju, Anirudh V. “Digital data processing and computational design for large area maskless photopolymerization.” 2013. Doctoral Dissertation, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/52930.

MLA Handbook (7th Edition):

Rudraraju, Anirudh V. “Digital data processing and computational design for large area maskless photopolymerization.” 2013. Web. 28 Feb 2020.

Vancouver:

Rudraraju AV. Digital data processing and computational design for large area maskless photopolymerization. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/52930.

Council of Science Editors:

Rudraraju AV. Digital data processing and computational design for large area maskless photopolymerization. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/52930


Georgia Tech

29. Hirsch, Michael Robert. Temperature dependent fretting damage modeling of AISI 301 stainless steel.

Degree: PhD, Mechanical Engineering, 2013, Georgia Tech

 Prediction of fatigue damage due to fretting is complex due to the number of influential factors and the competitive interaction between wear and fatigue. The… (more)

Subjects/Keywords: Fretting; Fatigue; Stainless steel; FEM

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APA (6th Edition):

Hirsch, M. R. (2013). Temperature dependent fretting damage modeling of AISI 301 stainless steel. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52975

Chicago Manual of Style (16th Edition):

Hirsch, Michael Robert. “Temperature dependent fretting damage modeling of AISI 301 stainless steel.” 2013. Doctoral Dissertation, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/52975.

MLA Handbook (7th Edition):

Hirsch, Michael Robert. “Temperature dependent fretting damage modeling of AISI 301 stainless steel.” 2013. Web. 28 Feb 2020.

Vancouver:

Hirsch MR. Temperature dependent fretting damage modeling of AISI 301 stainless steel. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/52975.

Council of Science Editors:

Hirsch MR. Temperature dependent fretting damage modeling of AISI 301 stainless steel. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/52975


Georgia Tech

30. Chen, Wei. Design, fabrication, and reliability study of second-level compliant microelectronic interconnects.

Degree: PhD, Mechanical Engineering, 2015, Georgia Tech

 Free-standing off-chip interconnects have high in-plane and out-of-plane compliance and are being pursued in academia and industry to reduce die stresses and to enhance interconnect… (more)

Subjects/Keywords: Compliant interconnect; Microelectronic packaging; Packaging reliability

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APA (6th Edition):

Chen, W. (2015). Design, fabrication, and reliability study of second-level compliant microelectronic interconnects. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55550

Chicago Manual of Style (16th Edition):

Chen, Wei. “Design, fabrication, and reliability study of second-level compliant microelectronic interconnects.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 28, 2020. http://hdl.handle.net/1853/55550.

MLA Handbook (7th Edition):

Chen, Wei. “Design, fabrication, and reliability study of second-level compliant microelectronic interconnects.” 2015. Web. 28 Feb 2020.

Vancouver:

Chen W. Design, fabrication, and reliability study of second-level compliant microelectronic interconnects. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2020 Feb 28]. Available from: http://hdl.handle.net/1853/55550.

Council of Science Editors:

Chen W. Design, fabrication, and reliability study of second-level compliant microelectronic interconnects. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/55550

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