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You searched for +publisher:"Georgia Tech" +contributor:("Singh, Adit"). Showing records 1 – 7 of 7 total matches.

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Georgia Tech

1. Natarajan, Jayaram. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 One of the challenges faced today in the design of microprocessors is to obtain power, performance scalability and reliability at the same time with technology… (more)

Subjects/Keywords: Microprocessor; Low power; Process variation; Timing variation tolerant; Timing margins; Better than worse-case design; Error resilient pipeline; Reliability

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APA (6th Edition):

Natarajan, J. (2016). Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55577

Chicago Manual of Style (16th Edition):

Natarajan, Jayaram. “Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.” 2016. Doctoral Dissertation, Georgia Tech. Accessed September 17, 2019. http://hdl.handle.net/1853/55577.

MLA Handbook (7th Edition):

Natarajan, Jayaram. “Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.” 2016. Web. 17 Sep 2019.

Vancouver:

Natarajan J. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Sep 17]. Available from: http://hdl.handle.net/1853/55577.

Council of Science Editors:

Natarajan J. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55577


Georgia Tech

2. Muldrey, Barry John. ALGORITHMS FOR POST-SILICON VALIDATION AND DEBUG OF RADIO-FREQUENCY, ANALOG, AND MIXED-SIGNAL CIRCUITS AND SYSTEMS.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 This thesis makes inroads toward a unified paradigm for the verification of hierarchical dynamical models for analog, mixed-signal, and radio-frequency circuits and systems and provides… (more)

Subjects/Keywords: validation; verification; post-silicon; model-order-reduction; design-of-experiments; model-extraction; model-augmentation; model-boosting

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APA (6th Edition):

Muldrey, B. J. (2019). ALGORITHMS FOR POST-SILICON VALIDATION AND DEBUG OF RADIO-FREQUENCY, ANALOG, AND MIXED-SIGNAL CIRCUITS AND SYSTEMS. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61713

Chicago Manual of Style (16th Edition):

Muldrey, Barry John. “ALGORITHMS FOR POST-SILICON VALIDATION AND DEBUG OF RADIO-FREQUENCY, ANALOG, AND MIXED-SIGNAL CIRCUITS AND SYSTEMS.” 2019. Doctoral Dissertation, Georgia Tech. Accessed September 17, 2019. http://hdl.handle.net/1853/61713.

MLA Handbook (7th Edition):

Muldrey, Barry John. “ALGORITHMS FOR POST-SILICON VALIDATION AND DEBUG OF RADIO-FREQUENCY, ANALOG, AND MIXED-SIGNAL CIRCUITS AND SYSTEMS.” 2019. Web. 17 Sep 2019.

Vancouver:

Muldrey BJ. ALGORITHMS FOR POST-SILICON VALIDATION AND DEBUG OF RADIO-FREQUENCY, ANALOG, AND MIXED-SIGNAL CIRCUITS AND SYSTEMS. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2019 Sep 17]. Available from: http://hdl.handle.net/1853/61713.

Council of Science Editors:

Muldrey BJ. ALGORITHMS FOR POST-SILICON VALIDATION AND DEBUG OF RADIO-FREQUENCY, ANALOG, AND MIXED-SIGNAL CIRCUITS AND SYSTEMS. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/61713

3. Wang, Xian. Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 Low-cost test and tuning methods for difficult-to-measure specifications are presented in this research from the following perspectives: 1)"Safe" test and self-tuning for power converters: To… (more)

Subjects/Keywords: Signature test; RF signal generation; Power converter test; Built-in test; DFT; Alternative testing

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APA (6th Edition):

Wang, X. (2015). Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53521

Chicago Manual of Style (16th Edition):

Wang, Xian. “Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices.” 2015. Doctoral Dissertation, Georgia Tech. Accessed September 17, 2019. http://hdl.handle.net/1853/53521.

MLA Handbook (7th Edition):

Wang, Xian. “Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices.” 2015. Web. 17 Sep 2019.

Vancouver:

Wang X. Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Sep 17]. Available from: http://hdl.handle.net/1853/53521.

Council of Science Editors:

Wang X. Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53521

4. Deyati, Sabyasachi. Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 With the advent of SOCs and SOPs, more functionalities are integrated into an IC or package. Higher level of integration has made testing, validation of… (more)

Subjects/Keywords: Adaptive testing; Analog/RF testing; Mixed signal validation; Machine learning; Beam forming MIMO systems; Trojan detection; Analog physically unclonable function

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APA (6th Edition):

Deyati, S. (2017). Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58757

Chicago Manual of Style (16th Edition):

Deyati, Sabyasachi. “Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems.” 2017. Doctoral Dissertation, Georgia Tech. Accessed September 17, 2019. http://hdl.handle.net/1853/58757.

MLA Handbook (7th Edition):

Deyati, Sabyasachi. “Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems.” 2017. Web. 17 Sep 2019.

Vancouver:

Deyati S. Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Sep 17]. Available from: http://hdl.handle.net/1853/58757.

Council of Science Editors:

Deyati S. Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58757


Georgia Tech

5. Ashouei, Maryam. Algorithms and Methodology for Post-Manufacture Adaptation to Process Variations and Induced Noise in Deeply Scaled CMOS Technologies.

Degree: PhD, Electrical and Computer Engineering, 2007, Georgia Tech

 In the last two decades, VLSI technology scaling has spurred a rapid growth in the semiconductor industry. With CMOS device dimensions falling below 100 nm,… (more)

Subjects/Keywords: Probablistic compensation; Transient error; CMOS; Process variation; Metal oxide semiconductors, Complementary; Manufacturing processes

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APA (6th Edition):

Ashouei, M. (2007). Algorithms and Methodology for Post-Manufacture Adaptation to Process Variations and Induced Noise in Deeply Scaled CMOS Technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/19859

Chicago Manual of Style (16th Edition):

Ashouei, Maryam. “Algorithms and Methodology for Post-Manufacture Adaptation to Process Variations and Induced Noise in Deeply Scaled CMOS Technologies.” 2007. Doctoral Dissertation, Georgia Tech. Accessed September 17, 2019. http://hdl.handle.net/1853/19859.

MLA Handbook (7th Edition):

Ashouei, Maryam. “Algorithms and Methodology for Post-Manufacture Adaptation to Process Variations and Induced Noise in Deeply Scaled CMOS Technologies.” 2007. Web. 17 Sep 2019.

Vancouver:

Ashouei M. Algorithms and Methodology for Post-Manufacture Adaptation to Process Variations and Induced Noise in Deeply Scaled CMOS Technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2007. [cited 2019 Sep 17]. Available from: http://hdl.handle.net/1853/19859.

Council of Science Editors:

Ashouei M. Algorithms and Methodology for Post-Manufacture Adaptation to Process Variations and Induced Noise in Deeply Scaled CMOS Technologies. [Doctoral Dissertation]. Georgia Tech; 2007. Available from: http://hdl.handle.net/1853/19859


Georgia Tech

6. Xuan, Xiangdong. Analysis and design of reliable mixed-signal CMOS circuits.

Degree: PhD, Electrical and Computer Engineering, 2004, Georgia Tech

 Facing the constantly increasing reliability challenges under technology scaling, the topics in IC reliability technique have been receiving serious attention during recent years. In this… (more)

Subjects/Keywords: Reliability simulation; Design-for-reliability; IC reliability; Metal oxide semiconductors, Complementary Reliability Computer simulation; Integrated circuits Reliability Computer simulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xuan, X. (2004). Analysis and design of reliable mixed-signal CMOS circuits. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/4776

Chicago Manual of Style (16th Edition):

Xuan, Xiangdong. “Analysis and design of reliable mixed-signal CMOS circuits.” 2004. Doctoral Dissertation, Georgia Tech. Accessed September 17, 2019. http://hdl.handle.net/1853/4776.

MLA Handbook (7th Edition):

Xuan, Xiangdong. “Analysis and design of reliable mixed-signal CMOS circuits.” 2004. Web. 17 Sep 2019.

Vancouver:

Xuan X. Analysis and design of reliable mixed-signal CMOS circuits. [Internet] [Doctoral dissertation]. Georgia Tech; 2004. [cited 2019 Sep 17]. Available from: http://hdl.handle.net/1853/4776.

Council of Science Editors:

Xuan X. Analysis and design of reliable mixed-signal CMOS circuits. [Doctoral Dissertation]. Georgia Tech; 2004. Available from: http://hdl.handle.net/1853/4776


Georgia Tech

7. Dhillon, Yuvraj Singh. Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability.

Degree: PhD, Electrical and Computer Engineering, 2005, Georgia Tech

 Power consumption and soft-error tolerance have become major constraints in the design of DSM CMOS circuits. With continued technology scaling, the impact of these parameters… (more)

Subjects/Keywords: Dual threshold voltages; Multiple supply voltages; Low-power; Sizing; Circuit optimization; Soft error

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dhillon, Y. S. (2005). Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/6935

Chicago Manual of Style (16th Edition):

Dhillon, Yuvraj Singh. “Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability.” 2005. Doctoral Dissertation, Georgia Tech. Accessed September 17, 2019. http://hdl.handle.net/1853/6935.

MLA Handbook (7th Edition):

Dhillon, Yuvraj Singh. “Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability.” 2005. Web. 17 Sep 2019.

Vancouver:

Dhillon YS. Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability. [Internet] [Doctoral dissertation]. Georgia Tech; 2005. [cited 2019 Sep 17]. Available from: http://hdl.handle.net/1853/6935.

Council of Science Editors:

Dhillon YS. Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability. [Doctoral Dissertation]. Georgia Tech; 2005. Available from: http://hdl.handle.net/1853/6935

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