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You searched for +publisher:"Georgia Tech" +contributor:("Raychowdhury, Arijit"). Showing records 1 – 30 of 36 total matches.

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1. Ku, Bon Woong Woong. Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node.

Degree: MS, Electrical and Computer Engineering, 2017, Georgia Tech

 The nature of device scaling in the 7nm era is changing from the traditional scheme driven by Moore’s law because of the physical and economic… (more)

Subjects/Keywords: Gate-level; Monolithic 3D IC; PPC tradeoff; 7nm technology node

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APA (6th Edition):

Ku, B. W. W. (2017). Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58257

Chicago Manual of Style (16th Edition):

Ku, Bon Woong Woong. “Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node.” 2017. Masters Thesis, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/58257.

MLA Handbook (7th Edition):

Ku, Bon Woong Woong. “Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node.” 2017. Web. 22 Sep 2019.

Vancouver:

Ku BWW. Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/58257.

Council of Science Editors:

Ku BWW. Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58257


Georgia Tech

2. Chintaluri, Ashwin K. Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays.

Degree: MS, Electrical and Computer Engineering, 2016, Georgia Tech

 Spin transfer torque magnetic random access memory (STT-MRAM) is a competitive, future memory technology that has gained immense interest in recent years due to its… (more)

Subjects/Keywords: STT-MRAM; Variation; Faults

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APA (6th Edition):

Chintaluri, A. K. (2016). Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55060

Chicago Manual of Style (16th Edition):

Chintaluri, Ashwin K. “Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays.” 2016. Masters Thesis, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/55060.

MLA Handbook (7th Edition):

Chintaluri, Ashwin K. “Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays.” 2016. Web. 22 Sep 2019.

Vancouver:

Chintaluri AK. Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/55060.

Council of Science Editors:

Chintaluri AK. Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55060


Georgia Tech

3. Carlo, Sergio. Load-Aware Power Conversion and Integration for Heterogeneous Systems.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 In this thesis we develop a holistic co-design approach to optimize the conversion systems in order to perform relevant trade-offs taking into account system-level converter,… (more)

Subjects/Keywords: Power conversion 3D single inductor multiple output SIMO control design power management

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APA (6th Edition):

Carlo, S. (2015). Load-Aware Power Conversion and Integration for Heterogeneous Systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56182

Chicago Manual of Style (16th Edition):

Carlo, Sergio. “Load-Aware Power Conversion and Integration for Heterogeneous Systems.” 2015. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/56182.

MLA Handbook (7th Edition):

Carlo, Sergio. “Load-Aware Power Conversion and Integration for Heterogeneous Systems.” 2015. Web. 22 Sep 2019.

Vancouver:

Carlo S. Load-Aware Power Conversion and Integration for Heterogeneous Systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/56182.

Council of Science Editors:

Carlo S. Load-Aware Power Conversion and Integration for Heterogeneous Systems. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56182


Georgia Tech

4. Ko, Jong Hwan. Resource-aware and robust image processing for intelligent sensor systems.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The objective of this research is to design resource-aware and robust image processing algorithms, system architecture, and hardware implementation for intelligent image sensor systems in… (more)

Subjects/Keywords: Image processing; Deep learning; Sensor systems

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APA (6th Edition):

Ko, J. H. (2018). Resource-aware and robust image processing for intelligent sensor systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60198

Chicago Manual of Style (16th Edition):

Ko, Jong Hwan. “Resource-aware and robust image processing for intelligent sensor systems.” 2018. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/60198.

MLA Handbook (7th Edition):

Ko, Jong Hwan. “Resource-aware and robust image processing for intelligent sensor systems.” 2018. Web. 22 Sep 2019.

Vancouver:

Ko JH. Resource-aware and robust image processing for intelligent sensor systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/60198.

Council of Science Editors:

Ko JH. Resource-aware and robust image processing for intelligent sensor systems. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60198


Georgia Tech

5. Kamdar, Keval Prakash. Performance estimation of large area nanowires.

Degree: MS, Electrical and Computer Engineering, 2019, Georgia Tech

 The focus of the thesis is to extensively model high-performance nanowires, develop Verilog A models of the devices and then simulate them using SPICE to… (more)

Subjects/Keywords: Nanowires; vlsi

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APA (6th Edition):

Kamdar, K. P. (2019). Performance estimation of large area nanowires. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61309

Chicago Manual of Style (16th Edition):

Kamdar, Keval Prakash. “Performance estimation of large area nanowires.” 2019. Masters Thesis, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/61309.

MLA Handbook (7th Edition):

Kamdar, Keval Prakash. “Performance estimation of large area nanowires.” 2019. Web. 22 Sep 2019.

Vancouver:

Kamdar KP. Performance estimation of large area nanowires. [Internet] [Masters thesis]. Georgia Tech; 2019. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/61309.

Council of Science Editors:

Kamdar KP. Performance estimation of large area nanowires. [Masters Thesis]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/61309

6. Lohith, Penmetsa Neela. Monolithic 3D integration of asynchronous systems.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 The goal of this thesis is to study the impact of 3D integration on asynchronous circuits and explore the benefits in power, performance and area… (more)

Subjects/Keywords: Asynchronous; 3DIC; Monolithic

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APA (6th Edition):

Lohith, P. N. (2014). Monolithic 3D integration of asynchronous systems. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53113

Chicago Manual of Style (16th Edition):

Lohith, Penmetsa Neela. “Monolithic 3D integration of asynchronous systems.” 2014. Masters Thesis, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/53113.

MLA Handbook (7th Edition):

Lohith, Penmetsa Neela. “Monolithic 3D integration of asynchronous systems.” 2014. Web. 22 Sep 2019.

Vancouver:

Lohith PN. Monolithic 3D integration of asynchronous systems. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/53113.

Council of Science Editors:

Lohith PN. Monolithic 3D integration of asynchronous systems. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/53113

7. Subramanian, Ashwin Srinath. Enhancing microprocessor power efficiency through clock-data compensation.

Degree: MS, Electrical and Computer Engineering, 2015, Georgia Tech

 The Smartphone revolution and the Internet of Things (IoTs) have triggered rapid advances in complex system-on-chips (SoCs) that increasing provide more functionality within a tight… (more)

Subjects/Keywords: Power management; Adaptive Clocking; Clock-data compensation; Power efficiency

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APA (6th Edition):

Subramanian, A. S. (2015). Enhancing microprocessor power efficiency through clock-data compensation. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54471

Chicago Manual of Style (16th Edition):

Subramanian, Ashwin Srinath. “Enhancing microprocessor power efficiency through clock-data compensation.” 2015. Masters Thesis, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/54471.

MLA Handbook (7th Edition):

Subramanian, Ashwin Srinath. “Enhancing microprocessor power efficiency through clock-data compensation.” 2015. Web. 22 Sep 2019.

Vancouver:

Subramanian AS. Enhancing microprocessor power efficiency through clock-data compensation. [Internet] [Masters thesis]. Georgia Tech; 2015. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/54471.

Council of Science Editors:

Subramanian AS. Enhancing microprocessor power efficiency through clock-data compensation. [Masters Thesis]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/54471

8. Somoye, Idris Olansile. GPU accelerated adaptive compressed sensing.

Degree: MS, Electrical and Computer Engineering, 2016, Georgia Tech

 There are presently image sensors based around compressed sensing that apply the fundamental theory to video acquisition; however, these imagers require specialized hardware modules that… (more)

Subjects/Keywords: GPU; Compressed sensing; GPGPU; Predictive video encoding

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APA (6th Edition):

Somoye, I. O. (2016). GPU accelerated adaptive compressed sensing. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56379

Chicago Manual of Style (16th Edition):

Somoye, Idris Olansile. “GPU accelerated adaptive compressed sensing.” 2016. Masters Thesis, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/56379.

MLA Handbook (7th Edition):

Somoye, Idris Olansile. “GPU accelerated adaptive compressed sensing.” 2016. Web. 22 Sep 2019.

Vancouver:

Somoye IO. GPU accelerated adaptive compressed sensing. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/56379.

Council of Science Editors:

Somoye IO. GPU accelerated adaptive compressed sensing. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56379

9. Ahmed, Khondker Zakir. Low voltage autonomous buck-boost regulator for wide input energy harvesting.

Degree: MS, Electrical and Computer Engineering, 2015, Georgia Tech

 While high power buck-boost regulators have been extensively researched and developed in the academia and industry, low power counterparts have only recently gained momentum due… (more)

Subjects/Keywords: Buck-boost regulator; |Low voltage energy harvesting; Low current regulator; nA bias current regulator

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APA (6th Edition):

Ahmed, K. Z. (2015). Low voltage autonomous buck-boost regulator for wide input energy harvesting. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53604

Chicago Manual of Style (16th Edition):

Ahmed, Khondker Zakir. “Low voltage autonomous buck-boost regulator for wide input energy harvesting.” 2015. Masters Thesis, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/53604.

MLA Handbook (7th Edition):

Ahmed, Khondker Zakir. “Low voltage autonomous buck-boost regulator for wide input energy harvesting.” 2015. Web. 22 Sep 2019.

Vancouver:

Ahmed KZ. Low voltage autonomous buck-boost regulator for wide input energy harvesting. [Internet] [Masters thesis]. Georgia Tech; 2015. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/53604.

Council of Science Editors:

Ahmed KZ. Low voltage autonomous buck-boost regulator for wide input energy harvesting. [Masters Thesis]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53604

10. Mudassar, Burhan Ahmad. Design and implementation of a content aware image processing module on FPGA.

Degree: MS, Electrical and Computer Engineering, 2015, Georgia Tech

 In this thesis, we tackle the problem of designing and implementing a wireless video sensor network for a surveillance application. The goal was to design… (more)

Subjects/Keywords: Content aware; Image processing; Edge detection; Image preprocessing; Low power; FPGA

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APA (6th Edition):

Mudassar, B. A. (2015). Design and implementation of a content aware image processing module on FPGA. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53618

Chicago Manual of Style (16th Edition):

Mudassar, Burhan Ahmad. “Design and implementation of a content aware image processing module on FPGA.” 2015. Masters Thesis, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/53618.

MLA Handbook (7th Edition):

Mudassar, Burhan Ahmad. “Design and implementation of a content aware image processing module on FPGA.” 2015. Web. 22 Sep 2019.

Vancouver:

Mudassar BA. Design and implementation of a content aware image processing module on FPGA. [Internet] [Masters thesis]. Georgia Tech; 2015. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/53618.

Council of Science Editors:

Mudassar BA. Design and implementation of a content aware image processing module on FPGA. [Masters Thesis]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53618

11. Desai, Soham Jayesh. Hardware implementation of re-configurable Restricted Boltzmann Machines for image recognition.

Degree: MS, Electrical and Computer Engineering, 2015, Georgia Tech

 The Internet of Things (IoTs) has triggered rapid advances in sensors, surveillance devices, wearables and body area networks with advanced Human-Computer Interfaces (HCI). Neural Networks… (more)

Subjects/Keywords: Restricted Boltzmann Machines; Re-configurable hardware; Neural processing cores; Image recognition; Low power sensing; Body-worn cameras; Cascaded classifiers; Posture detection

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APA (6th Edition):

Desai, S. J. (2015). Hardware implementation of re-configurable Restricted Boltzmann Machines for image recognition. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53548

Chicago Manual of Style (16th Edition):

Desai, Soham Jayesh. “Hardware implementation of re-configurable Restricted Boltzmann Machines for image recognition.” 2015. Masters Thesis, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/53548.

MLA Handbook (7th Edition):

Desai, Soham Jayesh. “Hardware implementation of re-configurable Restricted Boltzmann Machines for image recognition.” 2015. Web. 22 Sep 2019.

Vancouver:

Desai SJ. Hardware implementation of re-configurable Restricted Boltzmann Machines for image recognition. [Internet] [Masters thesis]. Georgia Tech; 2015. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/53548.

Council of Science Editors:

Desai SJ. Hardware implementation of re-configurable Restricted Boltzmann Machines for image recognition. [Masters Thesis]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53548


Georgia Tech

12. Zhang, David Chong. Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 A power distribution network (PDN) is designed to provide clean power and facilitate high signal integrity in modern electronic systems. However, the design of a… (more)

Subjects/Keywords: Power delivery network; Power transmission line; Signal integrity; Power integrity; Return path discontinuity

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APA (6th Edition):

Zhang, D. C. (2016). Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56282

Chicago Manual of Style (16th Edition):

Zhang, David Chong. “Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems.” 2016. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/56282.

MLA Handbook (7th Edition):

Zhang, David Chong. “Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems.” 2016. Web. 22 Sep 2019.

Vancouver:

Zhang DC. Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/56282.

Council of Science Editors:

Zhang DC. Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56282


Georgia Tech

13. Chae, Kwanyeob. Design methodologies for robust low-power digital systems under static and dynamic variations.

Degree: PhD, Electrical and Computer Engineering, 2013, Georgia Tech

 Variability affects the performance and power of a circuit. Along with static variations, dynamic variations, which occur during chip operation, necessitate a safety margin. The… (more)

Subjects/Keywords: Adaptive circuit; Resilient design; Static variation; Dynamic variation; Error prevention

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APA (6th Edition):

Chae, K. (2013). Design methodologies for robust low-power digital systems under static and dynamic variations. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52174

Chicago Manual of Style (16th Edition):

Chae, Kwanyeob. “Design methodologies for robust low-power digital systems under static and dynamic variations.” 2013. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/52174.

MLA Handbook (7th Edition):

Chae, Kwanyeob. “Design methodologies for robust low-power digital systems under static and dynamic variations.” 2013. Web. 22 Sep 2019.

Vancouver:

Chae K. Design methodologies for robust low-power digital systems under static and dynamic variations. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/52174.

Council of Science Editors:

Chae K. Design methodologies for robust low-power digital systems under static and dynamic variations. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/52174


Georgia Tech

14. Natarajan, Jayaram. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 One of the challenges faced today in the design of microprocessors is to obtain power, performance scalability and reliability at the same time with technology… (more)

Subjects/Keywords: Microprocessor; Low power; Process variation; Timing variation tolerant; Timing margins; Better than worse-case design; Error resilient pipeline; Reliability

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APA (6th Edition):

Natarajan, J. (2016). Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55577

Chicago Manual of Style (16th Edition):

Natarajan, Jayaram. “Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.” 2016. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/55577.

MLA Handbook (7th Edition):

Natarajan, Jayaram. “Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.” 2016. Web. 22 Sep 2019.

Vancouver:

Natarajan J. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/55577.

Council of Science Editors:

Natarajan J. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55577


Georgia Tech

15. Song, Taigon. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The objective of this research is to study and develop computer-aided-design (CAD) methodologies for reliability in chip-package co-designed three-dimensional integrated circuit (3D IC) systems. 3D… (more)

Subjects/Keywords: 3D IC; Design Methodologies

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APA (6th Edition):

Song, T. (2015). CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56188

Chicago Manual of Style (16th Edition):

Song, Taigon. “CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.” 2015. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/56188.

MLA Handbook (7th Edition):

Song, Taigon. “CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.” 2015. Web. 22 Sep 2019.

Vancouver:

Song T. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/56188.

Council of Science Editors:

Song T. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56188


Georgia Tech

16. Peng, Yarui. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 As one of more-than-Moore technologies, 3D ICs enable next-generation systems with much higher device density without needs for technology scaling. However, designing reliable 3D IC… (more)

Subjects/Keywords: 3D IC; CAD; Methodology; Reliable; Power integrity; Signal integrity

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APA (6th Edition):

Peng, Y. (2016). CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56330

Chicago Manual of Style (16th Edition):

Peng, Yarui. “CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.” 2016. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/56330.

MLA Handbook (7th Edition):

Peng, Yarui. “CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.” 2016. Web. 22 Sep 2019.

Vancouver:

Peng Y. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/56330.

Council of Science Editors:

Peng Y. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56330


Georgia Tech

17. Tellekamp, Marshall B. Lithium niobium oxide multifunctional materials and applications in neuromorphic computing.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 This work explores the growth fundamentals and multifunctional applications of materials in the Li-Nb-O family with specific focus on the memristive applications of LiNbO2 as… (more)

Subjects/Keywords: Lithium niobite; Molecular beam epitaxy; Lithium niobate; Thin films; Neuromorphic computing

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APA (6th Edition):

Tellekamp, M. B. (2017). Lithium niobium oxide multifunctional materials and applications in neuromorphic computing. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60701

Chicago Manual of Style (16th Edition):

Tellekamp, Marshall B. “Lithium niobium oxide multifunctional materials and applications in neuromorphic computing.” 2017. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/60701.

MLA Handbook (7th Edition):

Tellekamp, Marshall B. “Lithium niobium oxide multifunctional materials and applications in neuromorphic computing.” 2017. Web. 22 Sep 2019.

Vancouver:

Tellekamp MB. Lithium niobium oxide multifunctional materials and applications in neuromorphic computing. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/60701.

Council of Science Editors:

Tellekamp MB. Lithium niobium oxide multifunctional materials and applications in neuromorphic computing. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/60701


Georgia Tech

18. Nasir, Saad Bin. Fine-grain on-chip power management using digital and digitally-assisted linear voltage regulators.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 On-chip voltage conversion and regulation right at the point-of-load using digital and digitally-assisted linear voltage regulators was proposed. On-chip voltage conversion and regulation minimizes power… (more)

Subjects/Keywords: On-chip power delivery; Digital and digitally assisted linear voltage regulators; LDO

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APA (6th Edition):

Nasir, S. B. (2017). Fine-grain on-chip power management using digital and digitally-assisted linear voltage regulators. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60708

Chicago Manual of Style (16th Edition):

Nasir, Saad Bin. “Fine-grain on-chip power management using digital and digitally-assisted linear voltage regulators.” 2017. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/60708.

MLA Handbook (7th Edition):

Nasir, Saad Bin. “Fine-grain on-chip power management using digital and digitally-assisted linear voltage regulators.” 2017. Web. 22 Sep 2019.

Vancouver:

Nasir SB. Fine-grain on-chip power management using digital and digitally-assisted linear voltage regulators. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/60708.

Council of Science Editors:

Nasir SB. Fine-grain on-chip power management using digital and digitally-assisted linear voltage regulators. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/60708


Georgia Tech

19. Zhang, Yang. Thermal and power delivery network modeling for emerging microelectronic integration platforms.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 In this dissertation, thermal management and power delivery challenges in 2.5-D and 3-D integration are presented. To address the thermal coupling issues in heterogeneous 3-D… (more)

Subjects/Keywords: 3D-IC, 2.5-D IC, Thermal, Power delivery, Signaling; 2.5-D IC; Thermal; Power delivery; Signaling

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APA (6th Edition):

Zhang, Y. (2017). Thermal and power delivery network modeling for emerging microelectronic integration platforms. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59199

Chicago Manual of Style (16th Edition):

Zhang, Yang. “Thermal and power delivery network modeling for emerging microelectronic integration platforms.” 2017. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/59199.

MLA Handbook (7th Edition):

Zhang, Yang. “Thermal and power delivery network modeling for emerging microelectronic integration platforms.” 2017. Web. 22 Sep 2019.

Vancouver:

Zhang Y. Thermal and power delivery network modeling for emerging microelectronic integration platforms. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/59199.

Council of Science Editors:

Zhang Y. Thermal and power delivery network modeling for emerging microelectronic integration platforms. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59199


Georgia Tech

20. Kar, Monodeep. Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 The energy-efficiency and security needs in computing systems, ranging from high performance processors to low-power devices are steadily increasing. State-of-the-art digital systems use dedicated encryption… (more)

Subjects/Keywords: Side channel attack; Power attack; Differential power analysis; DPA; Correlation power analysis; CPA; Differential electromagnetic analysis; DEMA; Test vector leakage assessment; TVLA; Integrated voltage regulators; IVR; Voltage regulation; Haswell; FIVR; Security guard extension; SGX; DC-DC converters; Buck regulators; IoT; Countermeasures; Advanced encryption standard; AES; AES-NI; Randomization; Security; Masking countermeasure; Dual rail logic

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APA (6th Edition):

Kar, M. (2017). Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59182

Chicago Manual of Style (16th Edition):

Kar, Monodeep. “Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines.” 2017. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/59182.

MLA Handbook (7th Edition):

Kar, Monodeep. “Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines.” 2017. Web. 22 Sep 2019.

Vancouver:

Kar M. Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/59182.

Council of Science Editors:

Kar M. Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59182


Georgia Tech

21. Wells, Joshua W. Content-adaptive cross-layer optimized video processing using real-time feature feedback.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 The objective of this research is to design a low-power video processing system capable of minimizing power consumption through graceful reduction of the quality of… (more)

Subjects/Keywords: Video processing; Video encoding; Object tracking; Low power; Error tolerant; Content adaptive

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APA (6th Edition):

Wells, J. W. (2017). Content-adaptive cross-layer optimized video processing using real-time feature feedback. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59751

Chicago Manual of Style (16th Edition):

Wells, Joshua W. “Content-adaptive cross-layer optimized video processing using real-time feature feedback.” 2017. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/59751.

MLA Handbook (7th Edition):

Wells, Joshua W. “Content-adaptive cross-layer optimized video processing using real-time feature feedback.” 2017. Web. 22 Sep 2019.

Vancouver:

Wells JW. Content-adaptive cross-layer optimized video processing using real-time feature feedback. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/59751.

Council of Science Editors:

Wells JW. Content-adaptive cross-layer optimized video processing using real-time feature feedback. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59751


Georgia Tech

22. Pardue, Colin Andrew. Wireless power transfer using integrated and emerging technologies.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 To support the next generation of compact low power devices, a wireless power transfer solution needs to have an improved combination of receiver coil area… (more)

Subjects/Keywords: Wireless power transfer; Internet of things; Integrated inductor; Packaging; Rf near field coupling; Power integrity

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APA (6th Edition):

Pardue, C. A. (2018). Wireless power transfer using integrated and emerging technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60216

Chicago Manual of Style (16th Edition):

Pardue, Colin Andrew. “Wireless power transfer using integrated and emerging technologies.” 2018. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/60216.

MLA Handbook (7th Edition):

Pardue, Colin Andrew. “Wireless power transfer using integrated and emerging technologies.” 2018. Web. 22 Sep 2019.

Vancouver:

Pardue CA. Wireless power transfer using integrated and emerging technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/60216.

Council of Science Editors:

Pardue CA. Wireless power transfer using integrated and emerging technologies. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60216


Georgia Tech

23. Dutta, Sourav. BEYOND-CMOS LOGIC AND INTERCONNECT USING COLLECTIVE PHENOMENA OF MAGNON, SKYRMION AND PLASMON.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The objective of this dissertation is to develop emerging beyond-CMOS logic and interconnect solutions using two alternative “tokens” for information processing - electron spin and… (more)

Subjects/Keywords: Magnon; Spin wave; Spintronics; Plasmon; Plasmonics; Skyrmion

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APA (6th Edition):

Dutta, S. (2018). BEYOND-CMOS LOGIC AND INTERCONNECT USING COLLECTIVE PHENOMENA OF MAGNON, SKYRMION AND PLASMON. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61100

Chicago Manual of Style (16th Edition):

Dutta, Sourav. “BEYOND-CMOS LOGIC AND INTERCONNECT USING COLLECTIVE PHENOMENA OF MAGNON, SKYRMION AND PLASMON.” 2018. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/61100.

MLA Handbook (7th Edition):

Dutta, Sourav. “BEYOND-CMOS LOGIC AND INTERCONNECT USING COLLECTIVE PHENOMENA OF MAGNON, SKYRMION AND PLASMON.” 2018. Web. 22 Sep 2019.

Vancouver:

Dutta S. BEYOND-CMOS LOGIC AND INTERCONNECT USING COLLECTIVE PHENOMENA OF MAGNON, SKYRMION AND PLASMON. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/61100.

Council of Science Editors:

Dutta S. BEYOND-CMOS LOGIC AND INTERCONNECT USING COLLECTIVE PHENOMENA OF MAGNON, SKYRMION AND PLASMON. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/61100


Georgia Tech

24. Ku, Bon Woong. Physical Design Solutions for 3D ICs and their Neuromorphic Applications.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 The wafer-level 3D integration including face-to-face (F2F) and monolithic 3D (M3D) technologies has been featured as a promising innovation to succeed the horizontal device scaling… (more)

Subjects/Keywords: Physical Design Solutions; 3D ICs; Neuromorphic Processor

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APA (6th Edition):

Ku, B. W. (2019). Physical Design Solutions for 3D ICs and their Neuromorphic Applications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61227

Chicago Manual of Style (16th Edition):

Ku, Bon Woong. “Physical Design Solutions for 3D ICs and their Neuromorphic Applications.” 2019. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/61227.

MLA Handbook (7th Edition):

Ku, Bon Woong. “Physical Design Solutions for 3D ICs and their Neuromorphic Applications.” 2019. Web. 22 Sep 2019.

Vancouver:

Ku BW. Physical Design Solutions for 3D ICs and their Neuromorphic Applications. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/61227.

Council of Science Editors:

Ku BW. Physical Design Solutions for 3D ICs and their Neuromorphic Applications. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/61227


Georgia Tech

25. Yoon, Insik. POST-CMOS MEMORY TECHNOLOGIES AND THEIR APPLICATIONS IN EMERGING COMPUTING MODELS.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 The objective of this proposed research is to take a holistic approach to the post-CMOS in/near-memory processing system design for machine learning and optimizations. We… (more)

Subjects/Keywords: Post-CMOS memory; STT-MRAM; Ferroelectric FET; reinforcement learning; in-memory computing; convex optimization

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APA (6th Edition):

Yoon, I. (2019). POST-CMOS MEMORY TECHNOLOGIES AND THEIR APPLICATIONS IN EMERGING COMPUTING MODELS. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61768

Chicago Manual of Style (16th Edition):

Yoon, Insik. “POST-CMOS MEMORY TECHNOLOGIES AND THEIR APPLICATIONS IN EMERGING COMPUTING MODELS.” 2019. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/61768.

MLA Handbook (7th Edition):

Yoon, Insik. “POST-CMOS MEMORY TECHNOLOGIES AND THEIR APPLICATIONS IN EMERGING COMPUTING MODELS.” 2019. Web. 22 Sep 2019.

Vancouver:

Yoon I. POST-CMOS MEMORY TECHNOLOGIES AND THEIR APPLICATIONS IN EMERGING COMPUTING MODELS. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/61768.

Council of Science Editors:

Yoon I. POST-CMOS MEMORY TECHNOLOGIES AND THEIR APPLICATIONS IN EMERGING COMPUTING MODELS. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/61768

26. Alexandrov, Borislav P. Design methodology for thermal management using embedded thermoelectric devices.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The main objectives of this dissertation is to investigate the prospects of embedded thermoelectric devices integrated in a chip package and to develop a design… (more)

Subjects/Keywords: VLSI; Thermal management; Thermoelectric cooling; Energy harvesting; CMOS control circuits; Temperature control

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APA (6th Edition):

Alexandrov, B. P. (2015). Design methodology for thermal management using embedded thermoelectric devices. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54352

Chicago Manual of Style (16th Edition):

Alexandrov, Borislav P. “Design methodology for thermal management using embedded thermoelectric devices.” 2015. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/54352.

MLA Handbook (7th Edition):

Alexandrov, Borislav P. “Design methodology for thermal management using embedded thermoelectric devices.” 2015. Web. 22 Sep 2019.

Vancouver:

Alexandrov BP. Design methodology for thermal management using embedded thermoelectric devices. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/54352.

Council of Science Editors:

Alexandrov BP. Design methodology for thermal management using embedded thermoelectric devices. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/54352

27. Kung, Jae Ha. Energy-efficient digital hardware platform for learning complex systems.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 System learning is the most fundamental research area in engineering domain. It is a modeling method to map external inputs to the corresponding outputs with/without… (more)

Subjects/Keywords: Energy-efficiency; Digital accelerator

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APA (6th Edition):

Kung, J. H. (2017). Energy-efficient digital hardware platform for learning complex systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58316

Chicago Manual of Style (16th Edition):

Kung, Jae Ha. “Energy-efficient digital hardware platform for learning complex systems.” 2017. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/58316.

MLA Handbook (7th Edition):

Kung, Jae Ha. “Energy-efficient digital hardware platform for learning complex systems.” 2017. Web. 22 Sep 2019.

Vancouver:

Kung JH. Energy-efficient digital hardware platform for learning complex systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/58316.

Council of Science Editors:

Kung JH. Energy-efficient digital hardware platform for learning complex systems. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58316

28. Lie, Denny. Design methodology for low power 3D-integrated image sensing system for network based applications.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 This dissertation investigates a methodology that can be used to design and optimize an energy efficient 3D-integrated image sensing and compression system for network based… (more)

Subjects/Keywords: VLSI; Digital system; 3D integration

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APA (6th Edition):

Lie, D. (2015). Design methodology for low power 3D-integrated image sensing system for network based applications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54862

Chicago Manual of Style (16th Edition):

Lie, Denny. “Design methodology for low power 3D-integrated image sensing system for network based applications.” 2015. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/54862.

MLA Handbook (7th Edition):

Lie, Denny. “Design methodology for low power 3D-integrated image sensing system for network based applications.” 2015. Web. 22 Sep 2019.

Vancouver:

Lie D. Design methodology for low power 3D-integrated image sensing system for network based applications. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/54862.

Council of Science Editors:

Lie D. Design methodology for low power 3D-integrated image sensing system for network based applications. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/54862

29. Wang, Xian. Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 Low-cost test and tuning methods for difficult-to-measure specifications are presented in this research from the following perspectives: 1)"Safe" test and self-tuning for power converters: To… (more)

Subjects/Keywords: Signature test; RF signal generation; Power converter test; Built-in test; DFT; Alternative testing

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APA (6th Edition):

Wang, X. (2015). Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53521

Chicago Manual of Style (16th Edition):

Wang, Xian. “Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices.” 2015. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/53521.

MLA Handbook (7th Edition):

Wang, Xian. “Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices.” 2015. Web. 22 Sep 2019.

Vancouver:

Wang X. Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/53521.

Council of Science Editors:

Wang X. Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53521

30. Deyati, Sabyasachi. Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 With the advent of SOCs and SOPs, more functionalities are integrated into an IC or package. Higher level of integration has made testing, validation of… (more)

Subjects/Keywords: Adaptive testing; Analog/RF testing; Mixed signal validation; Machine learning; Beam forming MIMO systems; Trojan detection; Analog physically unclonable function

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APA (6th Edition):

Deyati, S. (2017). Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58757

Chicago Manual of Style (16th Edition):

Deyati, Sabyasachi. “Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems.” 2017. Doctoral Dissertation, Georgia Tech. Accessed September 22, 2019. http://hdl.handle.net/1853/58757.

MLA Handbook (7th Edition):

Deyati, Sabyasachi. “Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems.” 2017. Web. 22 Sep 2019.

Vancouver:

Deyati S. Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Sep 22]. Available from: http://hdl.handle.net/1853/58757.

Council of Science Editors:

Deyati S. Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58757

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