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1.
Gordon, Christal.
Bio-inspired, bio-compatible, reconfigurable analog CMOS circuits.
Degree: PhD, Electrical and Computer Engineering, 2009, Georgia Tech
URL: http://hdl.handle.net/1853/37222 
► This work details CMOS, bio-inspired, bio-compatible circuits which were used as synapses between an artificial neuron and a living neuron and between two living neurons.…
(more)
▼ This work details CMOS, bio-inspired, bio-compatible circuits which were used as synapses between an artificial neuron and a living neuron and between two living neurons. An intracellular signal from a living neuron was amplified, an integrate-and-fire neuron was used as a simple processing element to detect the spikes, and an artificial synapse was used to send outputs to another living neuron.
The key structure is an electronic synapse which is based around a floating-gate pFET. The charge on the floating-gate is analogous to the synaptic weight and can be modified. This modification can be viewed as similar to long-term potentiation and long-term depression. The modification can either be programmed (supervised learning) or can adapt to the inputs (unsupervised learning). Since the technology to change the floating-gate weight has greatly improved, these weights can be set quickly and accurately. Intrinsic floating-gate learning rules were explored and the ability to change the synaptic weight was shown.
Advisors/Committee Members: Paul Hasler (Committee Chair).
Subjects/Keywords: Bio-inspired; Analog; CMOS; Design; Neural interfacing; Neuromorphic; Metal oxide semiconductors, Complementary; Synapses
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APA (6th Edition):
Gordon, C. (2009). Bio-inspired, bio-compatible, reconfigurable analog CMOS circuits. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/37222
Chicago Manual of Style (16th Edition):
Gordon, Christal. “Bio-inspired, bio-compatible, reconfigurable analog CMOS circuits.” 2009. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019.
http://hdl.handle.net/1853/37222.
MLA Handbook (7th Edition):
Gordon, Christal. “Bio-inspired, bio-compatible, reconfigurable analog CMOS circuits.” 2009. Web. 07 Dec 2019.
Vancouver:
Gordon C. Bio-inspired, bio-compatible, reconfigurable analog CMOS circuits. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2019 Dec 07].
Available from: http://hdl.handle.net/1853/37222.
Council of Science Editors:
Gordon C. Bio-inspired, bio-compatible, reconfigurable analog CMOS circuits. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/37222
Georgia Tech
2.
Marr, Bo.
Learning, probabilistic, and asynchronous technologies for an ultra efficient datapath.
Degree: PhD, Electrical and Computer Engineering, 2009, Georgia Tech
URL: http://hdl.handle.net/1853/31724
► A novel microarchitecture and circuit design techniques are presented for an asynchronous datapath that not only exhibits an extremely high rate of performance, but is…
(more)
▼ A novel microarchitecture and circuit design techniques are presented for an asynchronous datapath that not only exhibits an extremely high rate of performance, but is also energy efficient. A 0.5 um chip was fabricated and tested that contains test circuits for the asynchronous datapath. Results show an adder and multiplier design that due to the 2-dimensional bit pipelining techniques, speculative completion, dynamic asynchronous circuits, and bit-level reservation stations and reorder buffers can commit 16-bit additions and multiplications at 1 giga operation per second (GOPS). The synchronicity simulator is also shown that simulates the same architecture except at more modern transistor nodes showing adder and multiplier performances at up to 11.1 GOPS in a commerically available 65 nm process. When compared to other designs and results, these prove to be some of the fastest if not the fastest adders and multipliers to date. The chip technology also was tested down to supply voltages below threshold making it extremely energy efficient. The asynchronous architecture also allows more exotic technologies, which are presented. Learning digital circuits are presented whereby the current supplied to a digital gate can be dynamically updated with floating gate technology. Probabilistic digital signal processing is also presented where the probabilistic operation is due to the statistical delay through the asynchronous circuits. Results show successful image processing with probabilistic operation in the least significant bits of the datapath resulting in large performance and energy gains.
Advisors/Committee Members: Paul Hasler (Committee Chair), David V. Anderson (Committee Co-Chair).
Subjects/Keywords: Asynchronous; Adaptive; Circuits; Probabilistic computing; Low power; Energy efficient; Energy consumption; Asynchronous circuits; Signal processing Digital techniques
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APA (6th Edition):
Marr, B. (2009). Learning, probabilistic, and asynchronous technologies for an ultra efficient datapath. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/31724
Chicago Manual of Style (16th Edition):
Marr, Bo. “Learning, probabilistic, and asynchronous technologies for an ultra efficient datapath.” 2009. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019.
http://hdl.handle.net/1853/31724.
MLA Handbook (7th Edition):
Marr, Bo. “Learning, probabilistic, and asynchronous technologies for an ultra efficient datapath.” 2009. Web. 07 Dec 2019.
Vancouver:
Marr B. Learning, probabilistic, and asynchronous technologies for an ultra efficient datapath. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2019 Dec 07].
Available from: http://hdl.handle.net/1853/31724.
Council of Science Editors:
Marr B. Learning, probabilistic, and asynchronous technologies for an ultra efficient datapath. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/31724
Georgia Tech
3.
Wunderlich, Richard Bryan.
CMOS gate delay, power measurements and characterization with logical effort and logical power.
Degree: MS, Electrical and Computer Engineering, 2009, Georgia Tech
URL: http://hdl.handle.net/1853/31652
► The primary metrics associated with a logic gate's performance are speed, power, and area. We define a gate as a specific CMOS transistor level implementation…
(more)
▼ The primary metrics associated with a logic gate's performance are speed, power,
and area. We define a gate as a specific CMOS transistor level implementation of a particu-
lar boolean function in a specific fabrication technology at a constant rail voltage, constant
length, and where the ratio of any two transistor widths are constant. Asking how fast a
gate switches then is highly situational; it changes with load capacitance, choice of inputs,
input slew rate, and the size of the gate. Predicting how much energy the gate consumes
depends on the time frame, how many times the gate has switched in this time frame, input
selection, input slew rate, load capacitance, and gate width. Logical Effort (LE) predicts
gate delay with a simple linear equation: d = t(gh+p). Where g and p are gate and input
dependent parameters independent of load size and gate size, and h is the ratio of output ca-
pacitance to input capacitance (directly related to gate width), and t is a process dependent
conversion factor. The product, gh, then is the delay associated with driving a subsequent
gate, and p is the delay of the gate driving itself. The prediction ignores input slew rate and
the linear dependence fails for very large values of h, but for input slew rates on the same
order as the output slew rate, and for reasonable fan-outs, LE provides remarkably accurate
predictions of gate switching time. The methodology goes on to solve for the widths nec-
essary for each gate in an arbitrary logic path to minimize delay. Designs can quickly be
compared, analyzed and optimized. By breaking down delay into components, one is able
to intuitively choose better logic implementations, if parasitic delay is dominating, often a
better implementation is one with smaller fan-in gates and less logic depth, if effort delay
is dominating then then higher logic depth can lead to faster results. What the method does
not do is predict the power consumption ramifications of all of these choices. What about
minimizing power on non-critical paths, for instance?
To our knowledge, no methodology exists to predict power consumption in a similar
fashion. We propose a power prediction methodology, Logical Power (LP), compatible
with LE that breaks down power consumption into dynamic, static, and short-circuit com-
ponents with linear equations dependent on h. This would allow a compact and efficient
way to characterize a gate that scales with its environment, as well as to allow designers
optimizing with LE to consider not only the speed ramifications of individual gate sizings
but power as well. For instance given a target path delay higher than the theoretical mini-
mum predicted by LE, sizings could be chosen with LE and LP that minimize power that
still result in meeting the target delay.
The other major contribution of this work is a new short-circuit power measurement
technique for simulation that more accurately distinguishes between short-circuit and the
parasitic portions of dynamic power in total active power…
Advisors/Committee Members: Paul Hasler (Committee Chair), David V Anderson (Committee Member), Saibal Mukhopadhyay (Committee Member).
Subjects/Keywords: Speed; Power; Logical power; Logical effort; Analysis; Logic design; Logic circuits
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APA (6th Edition):
Wunderlich, R. B. (2009). CMOS gate delay, power measurements and characterization with logical effort and logical power. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/31652
Chicago Manual of Style (16th Edition):
Wunderlich, Richard Bryan. “CMOS gate delay, power measurements and characterization with logical effort and logical power.” 2009. Masters Thesis, Georgia Tech. Accessed December 07, 2019.
http://hdl.handle.net/1853/31652.
MLA Handbook (7th Edition):
Wunderlich, Richard Bryan. “CMOS gate delay, power measurements and characterization with logical effort and logical power.” 2009. Web. 07 Dec 2019.
Vancouver:
Wunderlich RB. CMOS gate delay, power measurements and characterization with logical effort and logical power. [Internet] [Masters thesis]. Georgia Tech; 2009. [cited 2019 Dec 07].
Available from: http://hdl.handle.net/1853/31652.
Council of Science Editors:
Wunderlich RB. CMOS gate delay, power measurements and characterization with logical effort and logical power. [Masters Thesis]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/31652
Georgia Tech
4.
Petre, Csaba.
Sim2spice, a tool for compiling simulink designs on FPAA and applications to neuromorphic circuits.
Degree: MS, Electrical and Computer Engineering, 2009, Georgia Tech
URL: http://hdl.handle.net/1853/31820
► Analog circuit technology is of vital importance in today's world of electronic design. Increasing prevalence of mobile electronics necessitates the search for solutions which offer…
(more)
▼ Analog circuit technology is of vital importance in today's world of electronic design. Increasing prevalence of mobile electronics necessitates the search for solutions which offer high performance given tight constraints on power and chip area. Field programmable arrays utilizing floating-gate technology are one possible solution to analog design. It offers the advantages of analog processing with the additional advantage of reconfigurability, giving the designer the ability to test new analog designs without costly and time-consuming fabrication and test cycles.
In this work, a new interface for FPAA's is demonstrated called Sim2spice, with which users can design signal processing systems in Matlab Simulink and compile them to SPICE circuit netlists. These netlists can be further compiled with a tool called GRASPER to a switch list for programming on an FPAA chip. Example library elements are shown, along with some compiled systems such as filters and vector-matrix multipliers.
One particularly compelling application of reconfigurable analog design is the field of neuromorphic circuits, which aims to reproduce the basic functional characteristics of biological neurons and synapses in analog integrated circuit technology. Simulink libraries have been built to allow designers to build neuromorphic systems on several FPAAs that have been developed expressly for the purpose of building neurons and connecting them in networks with synapses. Several possible dynamically learning synapses have also been explored.
Advisors/Committee Members: Paul Hasler (Committee Chair), Christopher Rozell (Committee Member), David Anderson (Committee Member).
Subjects/Keywords: Analog; Neuromorphic; FPAA; Simulink; Field programmable gate arrays; Signal processing; Linear integrated circuits
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APA (6th Edition):
Petre, C. (2009). Sim2spice, a tool for compiling simulink designs on FPAA and applications to neuromorphic circuits. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/31820
Chicago Manual of Style (16th Edition):
Petre, Csaba. “Sim2spice, a tool for compiling simulink designs on FPAA and applications to neuromorphic circuits.” 2009. Masters Thesis, Georgia Tech. Accessed December 07, 2019.
http://hdl.handle.net/1853/31820.
MLA Handbook (7th Edition):
Petre, Csaba. “Sim2spice, a tool for compiling simulink designs on FPAA and applications to neuromorphic circuits.” 2009. Web. 07 Dec 2019.
Vancouver:
Petre C. Sim2spice, a tool for compiling simulink designs on FPAA and applications to neuromorphic circuits. [Internet] [Masters thesis]. Georgia Tech; 2009. [cited 2019 Dec 07].
Available from: http://hdl.handle.net/1853/31820.
Council of Science Editors:
Petre C. Sim2spice, a tool for compiling simulink designs on FPAA and applications to neuromorphic circuits. [Masters Thesis]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/31820
5.
Horst, Stephen J.
Frequency synthesis applications of SiGe BiCMOS processes.
Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech
URL: http://hdl.handle.net/1853/42815
► Silicon Germanium BiCMOS technology has been demonstrated as an ideal platform for highly integrated systems requiring both high performance analog and RF circuits as well…
(more)
▼ Silicon Germanium BiCMOS technology has been demonstrated as an ideal platform for highly integrated systems requiring both high performance analog and RF circuits as well as large-scale digital functionality. Frequency synthesizers are ideal candidates for this technology because the mixed-signal nature of modern frequency synthesis designs fundamentally requires both digital and analog signal processing. This research targets three areas to improve SiGe frequency synthesizers. A majority of this work focuses on applying SiGe frequency synthesizers to extreme environment applications such as space, where low temperatures and ionizing radiation are significant design issues to contend with. A second focus area involves using SiGe HBTs to minimize noise in frequency synthesizer circuits. Improved low frequency "pink" noise in SiGe HBTs provide a significant advantage over CMOS devices, and frequency synthesis circuits are significantly affected by this type of noise. However, improving thermal "white" noise is also considered. Finally, an analysis of AM-PM distortion is considered for SiGe HBTs. The studies presented focus on identifying the physical mechanisms of observed phenomena, such as single event transients or phase noise characteristics in oscillators. The ultimate goal of this research is to provide a reference of effective design parameters for circuit and system designers seeking to take advantage of the properties of SiGe device physics.
Advisors/Committee Members: John D. Cressler (Committee Chair), Greg Sadowy (Committee Member), John Papapolymerou (Committee Member), Paul Hasler (Committee Member), Shyh-Chiang Shen (Committee Member).
Subjects/Keywords: Radiation hardening; Phase noise measurements; Frequency synthesizers; Signal generators; Semiconductors; Analog electronic systems
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APA (6th Edition):
Horst, S. J. (2011). Frequency synthesis applications of SiGe BiCMOS processes. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/42815
Chicago Manual of Style (16th Edition):
Horst, Stephen J. “Frequency synthesis applications of SiGe BiCMOS processes.” 2011. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019.
http://hdl.handle.net/1853/42815.
MLA Handbook (7th Edition):
Horst, Stephen J. “Frequency synthesis applications of SiGe BiCMOS processes.” 2011. Web. 07 Dec 2019.
Vancouver:
Horst SJ. Frequency synthesis applications of SiGe BiCMOS processes. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Dec 07].
Available from: http://hdl.handle.net/1853/42815.
Council of Science Editors:
Horst SJ. Frequency synthesis applications of SiGe BiCMOS processes. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/42815
6.
Baskaya, Ismail Faik.
Physical design automation for large scale field programmable analog arrays.
Degree: PhD, Electrical and Computer Engineering, 2009, Georgia Tech
URL: http://hdl.handle.net/1853/31810
► Field-programmable analog arrays (FPAA) are integrated circuits with a collection of analog building blocks connected through a wire and switch fabric to achieve reconfigurability similar…
(more)
▼ Field-programmable analog arrays (FPAA) are integrated circuits with a collection of analog building blocks connected through a wire and switch fabric to achieve reconfigurability similar to the FPGAs of the digital domain. Like FPGAs, FPAAs can help reduce the time and money costs of the integrated circuit design cycle and make analog design much easier. In recent years, several types of FPAAs have been developed. Among these, FPAAs that use floating-gate transistors as programming elements have shown great potential in scalability because of the simplicity they provide in configuring the chip. Existing tools for programming FPAAs tend to be device specific and aimed at specific tasks such as filter design. To move FPAAs to the next step, more powerful and generic placement and routing tools are necessary.
This thesis presents a placement and routing tool for large-scale floating-gate-based FPAAs. A topology independent routing resource graph (RRG) was used to model the FPAA routing topology, which enables generic description of any FPAA architecture with arbitrary connectivity including possible FPGA support in the future as well. So far, different FPAA architectures have been specified and routed successfully. The tool is already in use in classes and workshops for analog circuit and system design. Efficient ways to describe circuits and user constraints were developed to allow easy integration with other tools. Analog circuit performance was optimized by taking into account the routing parasitic effects on interconnects under various device-related constraints. Parasitic modeling allows simulation and evaluation of circuits routed on FPAA. Finally, a methodology was developed to explore the optimum architecture for a set of circuit
classes by evaluating the efficiency of different architectures for each circuit class.
Advisors/Committee Members: David V Anderson (Committee Chair), Sung Kyu Lim (Committee Co-Chair), Aaron Lanterman (Committee Member), Abhijit Chatterjee (Committee Member), Daniel Foty (Committee Member), Paul Hasler (Committee Member).
Subjects/Keywords: FPAA; Reconfigurable analog arrays; Placement; Routing; Parasitic extraction; Architecture exploration; Field programmable gate arrays; Integrated circuits; Integrated circuits Design and construction; Linear integrated circuits
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APA (6th Edition):
Baskaya, I. F. (2009). Physical design automation for large scale field programmable analog arrays. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/31810
Chicago Manual of Style (16th Edition):
Baskaya, Ismail Faik. “Physical design automation for large scale field programmable analog arrays.” 2009. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019.
http://hdl.handle.net/1853/31810.
MLA Handbook (7th Edition):
Baskaya, Ismail Faik. “Physical design automation for large scale field programmable analog arrays.” 2009. Web. 07 Dec 2019.
Vancouver:
Baskaya IF. Physical design automation for large scale field programmable analog arrays. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2019 Dec 07].
Available from: http://hdl.handle.net/1853/31810.
Council of Science Editors:
Baskaya IF. Physical design automation for large scale field programmable analog arrays. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/31810
Georgia Tech
7.
Levy, Michael Yehuda.
Calculation of the Band Properties of a Quantum Dot Intermediate Band Solar Cell with Centrally Located Hydrogenic Impurities.
Degree: MS, Electrical and Computer Engineering, 2004, Georgia Tech
URL: http://hdl.handle.net/1853/5072
► In the quantum dot implementation of an intermediate band solar cell presented in this thesis, the offset of the intermediate band with respect to the…
(more)
▼ In the quantum dot implementation of an intermediate band solar cell presented in this thesis, the offset of the intermediate band with respect to the conduction band is approximated by the ground state energy of a single electron in a single quantum dot heterojunction. The ground state energy is calculated with the radial Schrodinger equation with a Hamiltonian whose potential is composed from the step-like conduction band offset of the quantum dot heterojunction and the 1/r electrostatic potential of the hydrogenic impurity. The position of the intermediate band is tuned by adjusting the radius of the quantum dots. By assuming that the centrally located impurities are ionized, the location of the Fermi energy is guaranteed to be within the intermediate band.
An intermediate band solar cell contains three bands: a conduction band, a valence band; and an intermediate band. The addition of an intermediate band augments the photogeneration of carriers. These additional carriers allow for an increased theoretical efficiency as compared to a conventional homojunction solar cell. The challenges in implementing an intermediate band solar cell involve centering the intermediate band at an energy level matched to the solar spectrum and aligning the Fermi energy within the intermediate band. The latter is necessary to ensure both a supply of electrons capable of photon induced transition to the conduction band as well as a large population of holes that allow photon induced electrons to transition from the valence band to the intermediate band.
This thesis presents a novel material system, InPAs quantum dots enveloped in AlGaAs barriers grown on GaAs substrates, with which to implement an optimized QD-IBSC. This novel material system is selected based upon a refined set of design rules that include a requirement that the quantum dot/barrier pair offer a negligible valence band offset. With such a design rule the existence of hole levels is avoided, thus reducing bandgap narrowing at the valence band edge and the existence of minibands below the intermediate band.
Advisors/Committee Members: David Citrin (Committee Chair), Christiana Honsberg (Committee Member), Paul Hasler (Committee Member).
Subjects/Keywords: Intermediate band solar cell; Quantum dots; Hydrogenic impurity
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APA (6th Edition):
Levy, M. Y. (2004). Calculation of the Band Properties of a Quantum Dot Intermediate Band Solar Cell with Centrally Located Hydrogenic Impurities. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/5072
Chicago Manual of Style (16th Edition):
Levy, Michael Yehuda. “Calculation of the Band Properties of a Quantum Dot Intermediate Band Solar Cell with Centrally Located Hydrogenic Impurities.” 2004. Masters Thesis, Georgia Tech. Accessed December 07, 2019.
http://hdl.handle.net/1853/5072.
MLA Handbook (7th Edition):
Levy, Michael Yehuda. “Calculation of the Band Properties of a Quantum Dot Intermediate Band Solar Cell with Centrally Located Hydrogenic Impurities.” 2004. Web. 07 Dec 2019.
Vancouver:
Levy MY. Calculation of the Band Properties of a Quantum Dot Intermediate Band Solar Cell with Centrally Located Hydrogenic Impurities. [Internet] [Masters thesis]. Georgia Tech; 2004. [cited 2019 Dec 07].
Available from: http://hdl.handle.net/1853/5072.
Council of Science Editors:
Levy MY. Calculation of the Band Properties of a Quantum Dot Intermediate Band Solar Cell with Centrally Located Hydrogenic Impurities. [Masters Thesis]. Georgia Tech; 2004. Available from: http://hdl.handle.net/1853/5072
Georgia Tech
8.
Abramson, David.
MITE Architectures for Reconfigurable Analog Arrays.
Degree: MS, Electrical and Computer Engineering, 2004, Georgia Tech
URL: http://hdl.handle.net/1853/4920
► With the introduction of the floating-gate transistor into reconfigurable architectures, great advances have been made in the field. Recently, Hall et. al. have proposed the…
(more)
▼ With the introduction of the floating-gate transistor into reconfigurable architectures, great advances have been made in the field. Recently, Hall et. al. have proposed the first truly large-scale field programmable analog array (FPAA). As an outgrowth of this work, a new class of FPAAs based on translinear elements has begun to be developed. The use of translinear elements, multiple input translinear elements (MITEs) specifically, allows for extreme versatility in the functions implemented by the system while keeping the computational elements of the FPAA regular. In addition, synthesis procedures have been developed for translinear elements. This facilitates the implementation of large-scale systems on the FPAA because the circuit design can be extracted using the synthesis procedures based on equations entered by the user.
Two architectures are proposed for the new FPAA. The first architecture uses fine grain reconfigurability, every gate capacitor and the drain of each MITE can be connected arbitrarily, in order to create reconfigurable MITE networks. Circuits including a squaring circuit, a square root circuit, a translinear loop, a vector magnitude circuit, and a 1st-order log-domain filter were implemented using this architecture and results are presented. In addition, examples are shown to illustrate the compilation of the circuits onto the FPAA. The second proposed architecture uses a mix of fine and medium granularity in order to simplify the implementation of larger systems. Examples are given and again the compilation of the circuits onto the FPAA is shown.
Advisors/Committee Members: David Anderson (Committee Chair), Mark Smith (Committee Member), Paul Hasler (Committee Member).
Subjects/Keywords: MITE; Analog; FPAA; Programmable; Reconfigurable; Field programmable gate arrays; Electronic analog computers Circuits; Translinear
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APA (6th Edition):
Abramson, D. (2004). MITE Architectures for Reconfigurable Analog Arrays. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/4920
Chicago Manual of Style (16th Edition):
Abramson, David. “MITE Architectures for Reconfigurable Analog Arrays.” 2004. Masters Thesis, Georgia Tech. Accessed December 07, 2019.
http://hdl.handle.net/1853/4920.
MLA Handbook (7th Edition):
Abramson, David. “MITE Architectures for Reconfigurable Analog Arrays.” 2004. Web. 07 Dec 2019.
Vancouver:
Abramson D. MITE Architectures for Reconfigurable Analog Arrays. [Internet] [Masters thesis]. Georgia Tech; 2004. [cited 2019 Dec 07].
Available from: http://hdl.handle.net/1853/4920.
Council of Science Editors:
Abramson D. MITE Architectures for Reconfigurable Analog Arrays. [Masters Thesis]. Georgia Tech; 2004. Available from: http://hdl.handle.net/1853/4920
Georgia Tech
9.
Robucci, Ryan.
On Chip Error Compensation, Light Adaptation, and Image Enhancement with a CMOS Transform Image Sensor.
Degree: MS, Electrical and Computer Engineering, 2005, Georgia Tech
URL: http://hdl.handle.net/1853/6986
► CMOS imagers are replacing CCD imagers in many applications and will continue to make new applications possible. CMOS imaging offers lower cost implementations on standard…
(more)
▼ CMOS imagers are replacing CCD imagers in many applications and will continue to make new applications possible. CMOS imaging offers lower cost implementations on standard CMOS processes which allow for mixed signal processing on-chip. A system-on-a-chip approach offers the ability to perform complex algorithms faster, in less space, and with lower power and noise. Our transform imager is an implementation of a mixed focal plane and peripheral computation imager which allows high fill factor with high computational rates at low power. However, in order to use the technology effectively a need to verify and further understand the behavior and of the pixel elements in this transform imager was needed. This thesis presents a study of the pixel elements and mismatches and errors in the pixel array of this imager. From there, a discussion about removing offsets and an implementation of a circuit to remove the largest offsets is shown. To further enhance performance, initial work to develop light adaptive readout circuits is presented. Finally, an overview is given of a newly designed one-megapixel transform imager with many design improvements.
Advisors/Committee Members: Paul Hasler (Committee Chair), David Anderson (Committee Member), Steven DeWeerth (Committee Member).
Subjects/Keywords: CMOS imager; Metal oxide semiconductors, Complementary; Optical detectors; Imaging systems
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APA (6th Edition):
Robucci, R. (2005). On Chip Error Compensation, Light Adaptation, and Image Enhancement with a CMOS Transform Image Sensor. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/6986
Chicago Manual of Style (16th Edition):
Robucci, Ryan. “On Chip Error Compensation, Light Adaptation, and Image Enhancement with a CMOS Transform Image Sensor.” 2005. Masters Thesis, Georgia Tech. Accessed December 07, 2019.
http://hdl.handle.net/1853/6986.
MLA Handbook (7th Edition):
Robucci, Ryan. “On Chip Error Compensation, Light Adaptation, and Image Enhancement with a CMOS Transform Image Sensor.” 2005. Web. 07 Dec 2019.
Vancouver:
Robucci R. On Chip Error Compensation, Light Adaptation, and Image Enhancement with a CMOS Transform Image Sensor. [Internet] [Masters thesis]. Georgia Tech; 2005. [cited 2019 Dec 07].
Available from: http://hdl.handle.net/1853/6986.
Council of Science Editors:
Robucci R. On Chip Error Compensation, Light Adaptation, and Image Enhancement with a CMOS Transform Image Sensor. [Masters Thesis]. Georgia Tech; 2005. Available from: http://hdl.handle.net/1853/6986
Georgia Tech
10.
Twigg, Christopher M.
Floating Gate Based Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing.
Degree: PhD, Electrical and Computer Engineering, 2006, Georgia Tech
URL: http://hdl.handle.net/1853/11601
► Large-scale reconfigurable and programmable analog devices provide a new option for prototyping and synthesizing analog circuits for analog signal processing and beyond. Field-programmable analog arrays…
(more)
▼ Large-scale reconfigurable and programmable analog devices provide a new option for prototyping and synthesizing analog circuits for analog signal processing and beyond. Field-programmable analog arrays (FPAAs) built upon floating gate transistor technologies provide the analog reconfigurability and programmability density required for large-scale devices on a single integrated circuit (IC). A wide variety of synthesized circuits, such as OTA followers, band-pass filters, and capacitively coupled summation/difference circuits, were measured to demonstrate the flexibility of FPAAs. Three generations of devices were designed and tested to verify the viability of such floating gate based large-scale FPAAs. Various architectures and circuit topologies were also designed and tested to explore the trade-offs present in reconfigurable analog systems. In addition, large-scale FPAAs have been incorporated into class laboratory exercises, which provide students with a much broader range of circuit and IC design experiences than have been previously possible. By combining reconfigurable analog technologies with an equivalent large-scale digital device, such as a field-programmable gate array (FPGA), an extremely powerful and flexible mixed signal development system can be produced that will enable all of the benefits possible through cooperative analog/digital signal processing (CADSP).
Advisors/Committee Members: Dr. Paul Hasler (Committee Chair), Aaron D. Lanterman (Committee Member), David V. Anderson (Committee Member), John B. Peatman (Committee Member).
Subjects/Keywords: fpaa reconfigurable programmable analog; Signal processing; Linear integrated circuits; Integrated circuits Very large scale integration; Field programmable gate arrays
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APA (6th Edition):
Twigg, C. M. (2006). Floating Gate Based Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/11601
Chicago Manual of Style (16th Edition):
Twigg, Christopher M. “Floating Gate Based Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing.” 2006. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019.
http://hdl.handle.net/1853/11601.
MLA Handbook (7th Edition):
Twigg, Christopher M. “Floating Gate Based Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing.” 2006. Web. 07 Dec 2019.
Vancouver:
Twigg CM. Floating Gate Based Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing. [Internet] [Doctoral dissertation]. Georgia Tech; 2006. [cited 2019 Dec 07].
Available from: http://hdl.handle.net/1853/11601.
Council of Science Editors:
Twigg CM. Floating Gate Based Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing. [Doctoral Dissertation]. Georgia Tech; 2006. Available from: http://hdl.handle.net/1853/11601
Georgia Tech
11.
Hyun, Seok Hun.
Design of High-Speed Laser Driver Using a Standard CMOS Technology for Optical Data Transmission.
Degree: PhD, Electrical and Computer Engineering, 2004, Georgia Tech
URL: http://hdl.handle.net/1853/4903
► Many researchers and engineers designing laser drivers for data rates at or above 10 gigabits per second (Gbps) implemented their designs using integrated circuit technologies…
(more)
▼ Many researchers and engineers designing laser drivers for data rates at or above 10 gigabits per second (Gbps) implemented their designs using integrated circuit technologies that provide high bandwidth and good quality passive components such as GaAs, silicon bipolar, and InP. However, in low-cost and high volume short-haul applications at data rates of around 10 Gbps (such as LAN, MAN, and board-to-board interconnection), there has been an increasing interest in commercial CMOS technology for implementing the laser driver. This is because CMOS technology has unique advantages such as low power and low cost of fabrication that are the result of high yield and a high degree of integration. Therefore, the objective of this research in this dissertation is to investigate the possibility of implementing a high-speed CMOS laser driver for these cost sensitive applications.
The high-speed CMOS laser drivers designed in this research are of two types. The first type is a low power laser driver for driving a vertical cavity surface emitting laser (VCSEL). The other driver type is a high current laser driver for driving edge-emitting lasers such as double-heterojunction (DH), multiquantum well (MQW), or Febry-Perrot (FP) lasers.
The parasitic effects of the layout geometry are crucial in the design of the high-speed laser drivers. Thus, in this research, all simulations contain a complete set of parasitic elements extracted from the layout of the laser driver. To test laser drivers, chip-on-board (COB) technology is employed, and printed circuit boards (PCBs) to test the laser drivers are designed at the same time as the laser drivers themselves and manufactured specifically for these tests.
This research makes two significant new contributions to the technology that are reported and described here. One is the first 10 Gbps performance of a differential CMOS laser driver with better than 10-14 bit-error-rate (BER). The second is the first demonstration of a heterogeneous integration method to integrate independently grown and customized thin film lasers onto CMOS laser driver circuits to form an optical transmitter.
Advisors/Committee Members: Martin Brooke (Committee Chair), Bernard Kippelen (Committee Member), David Schimmel (Committee Member), Paul Hasler (Committee Member), Paul Kohl (Committee Member).
Subjects/Keywords: Optical communications; Laser driver; CMOS; Hybrid integration
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APA (6th Edition):
Hyun, S. H. (2004). Design of High-Speed Laser Driver Using a Standard CMOS Technology for Optical Data Transmission. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/4903
Chicago Manual of Style (16th Edition):
Hyun, Seok Hun. “Design of High-Speed Laser Driver Using a Standard CMOS Technology for Optical Data Transmission.” 2004. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019.
http://hdl.handle.net/1853/4903.
MLA Handbook (7th Edition):
Hyun, Seok Hun. “Design of High-Speed Laser Driver Using a Standard CMOS Technology for Optical Data Transmission.” 2004. Web. 07 Dec 2019.
Vancouver:
Hyun SH. Design of High-Speed Laser Driver Using a Standard CMOS Technology for Optical Data Transmission. [Internet] [Doctoral dissertation]. Georgia Tech; 2004. [cited 2019 Dec 07].
Available from: http://hdl.handle.net/1853/4903.
Council of Science Editors:
Hyun SH. Design of High-Speed Laser Driver Using a Standard CMOS Technology for Optical Data Transmission. [Doctoral Dissertation]. Georgia Tech; 2004. Available from: http://hdl.handle.net/1853/4903
Georgia Tech
12.
Dugger, Jeffery Don.
Adaptive Analog VLSI Signal Processing and Neural Networks.
Degree: PhD, Electrical and Computer Engineering, 2003, Georgia Tech
URL: http://hdl.handle.net/1853/5294
► Research presented in this thesis provides a substantial leap from the study of interesting device physics to fully adaptive analog networks and lays a solid…
(more)
▼ Research presented in this thesis provides
a substantial leap from the study of interesting
device physics to fully adaptive analog networks
and lays a solid foundation for future development
of large-scale, compact, low-power adaptive parallel
analog computation systems.
The investigation described here started with
observation of this potential learning capability
and led to the first derivation and characterization of
the floating-gate pFET correlation learning rule.
Starting with two synapses sharing the same error signal,
we progressed from phase correlation experiments
through correlation experiments involving harmonically related sinusoids,
culminating in learning the Fourier series coefficients
of a square wave cite{kn:Dugger2000}.
Extending these earlier two-input node experiments to the general case
of correlated inputs required dealing with
weight decay naturally exhibited by the learning rule.
We introduced a source-follower floating-gate synapse
as an improvement over our earlier source-degenerated floating-gate synapse
in terms of relative weight decay cite{kn:Dugger2004}.
A larger network of source-follower floating-gate synapses was fabricated
and an FPGA-controlled testboard was designed and built.
This more sophisticated system provides an excellent
framework for exploring applications to multi-input, multi-node
adaptive filtering applications.
Adaptive channel equalization provided
a practical test-case illustrating the use
of these adaptive systems in solving real-world problems.
The same system could easily be applied to noise and echo cancellation
in communication systems and system identification tasks in
optimal control problems.
We envision the commercialization of these adaptive analog VLSI
systems as practical products within a couple of years.
Advisors/Committee Members: Paul Hasler (Committee Chair), David Anderson (Committee Member), Dieter Jaeger (Committee Member), Mark Clements (Committee Member), Steve Deweerth (Committee Member).
Subjects/Keywords: Floating gate transistors; Neural networks; Adaptive filters; VLSI; Analog electronics
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APA (6th Edition):
Dugger, J. D. (2003). Adaptive Analog VLSI Signal Processing and Neural Networks. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/5294
Chicago Manual of Style (16th Edition):
Dugger, Jeffery Don. “Adaptive Analog VLSI Signal Processing and Neural Networks.” 2003. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019.
http://hdl.handle.net/1853/5294.
MLA Handbook (7th Edition):
Dugger, Jeffery Don. “Adaptive Analog VLSI Signal Processing and Neural Networks.” 2003. Web. 07 Dec 2019.
Vancouver:
Dugger JD. Adaptive Analog VLSI Signal Processing and Neural Networks. [Internet] [Doctoral dissertation]. Georgia Tech; 2003. [cited 2019 Dec 07].
Available from: http://hdl.handle.net/1853/5294.
Council of Science Editors:
Dugger JD. Adaptive Analog VLSI Signal Processing and Neural Networks. [Doctoral Dissertation]. Georgia Tech; 2003. Available from: http://hdl.handle.net/1853/5294
Georgia Tech
13.
Sharma, Ajit.
CMOS systems and circuits for sub-degree per hour MEMS gyroscopes.
Degree: PhD, Electrical and Computer Engineering, 2007, Georgia Tech
URL: http://hdl.handle.net/1853/26636
► The objective of our research is to develop system architectures and CMOS circuits that interface with high-Q silicon microgyroscopes to implement navigation-grade angular rate sensors.…
(more)
▼ The objective of our research is to develop system architectures and CMOS circuits that interface with high-Q silicon microgyroscopes to implement navigation-grade angular rate sensors. The MEMS sensor used in this work is an in-plane bulk-micromachined mode-matched tuning fork gyroscope (M² – TFG
), fabricated on silicon-on-insulator substrate. The use of CMOS transimpedance amplifiers (TIA) as front-ends in high-Q MEMS resonant sensors is explored. A T-network TIA is proposed as the front-end for resonant capacitive detection. The T-TIA provides on-chip transimpedance gains of 25MΩ, has a measured capacitive resolution of 0.02aF /√Hz at 15kHz, a dynamic range of 104dB in a bandwidth of 10Hz and consumes 400μW of power. A second contribution is the development of an automated scheme to adaptively bias the mechanical structure, such that the sensor is operated in the mode-matched condition. Mode-matching leverages the inherently high quality factors of the microgyroscope, resulting in significant improvement in the Brownian noise floor, electronic noise, sensitivity and bias drift of the microsensor. We developed a novel architecture that utilizes the often ignored residual quadrature error in a gyroscope to achieve and maintain perfect mode-matching (i.e.0Hz split between the drive and sense mode frequencies), as well as electronically control the sensor bandwidth. A CMOS implementation is developed that allows mode-matching of the drive and sense frequencies of a gyroscope at a fraction of the time taken by current state of-the-art techniques. Further, this mode-matching technique allows for maintaining a controlled separation between the drive and sense resonant frequencies, providing a means of increasing sensor bandwidth and dynamic range. The mode-matching CMOS IC, implemented in a 0.5μm 2P3M process, and control algorithm have been interfaced with a 60μm thick M2−TFG to implement an angular rate sensor with bias drift as low as 0.1°/hr ℃ the lowest recorded to date for a silicon MEMS gyro.
Advisors/Committee Members: Farrokh Ayazi (Committee Chair), Jennifer Michaels (Committee Member), Levent Degertekin (Committee Member), Paul Hasler (Committee Member), W. Marshall Leach (Committee Member).
Subjects/Keywords: MEMS; Gyroscopes; Data converters; Transimpedance amplifiers; Low-noise; Bias drift; Mode-matching; Detectors; Noise control; Transducers – Drift; Gyroscopic instruments
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APA (6th Edition):
Sharma, A. (2007). CMOS systems and circuits for sub-degree per hour MEMS gyroscopes. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/26636
Chicago Manual of Style (16th Edition):
Sharma, Ajit. “CMOS systems and circuits for sub-degree per hour MEMS gyroscopes.” 2007. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019.
http://hdl.handle.net/1853/26636.
MLA Handbook (7th Edition):
Sharma, Ajit. “CMOS systems and circuits for sub-degree per hour MEMS gyroscopes.” 2007. Web. 07 Dec 2019.
Vancouver:
Sharma A. CMOS systems and circuits for sub-degree per hour MEMS gyroscopes. [Internet] [Doctoral dissertation]. Georgia Tech; 2007. [cited 2019 Dec 07].
Available from: http://hdl.handle.net/1853/26636.
Council of Science Editors:
Sharma A. CMOS systems and circuits for sub-degree per hour MEMS gyroscopes. [Doctoral Dissertation]. Georgia Tech; 2007. Available from: http://hdl.handle.net/1853/26636
Georgia Tech
14.
Demiroglu, Cenk.
Multisensor Segmentation-based Noise Suppression for Intelligibility Improvement in MELP Coders.
Degree: PhD, Electrical and Computer Engineering, 2006, Georgia Tech
URL: http://hdl.handle.net/1853/10455
► This thesis investigates the use of an auxiliary sensor, the GEMS device, for improving the quality of noisy speech and designing noise preprocessors to MELP…
(more)
▼ This thesis investigates the use of an auxiliary sensor, the GEMS device, for improving the quality of noisy speech and designing noise preprocessors to MELP speech coders. Use of auxiliary sensors for noise-robust
ASR applications is also investigated to develop speech enhancement algorithms that use acoustic-phonetic
properties of the speech signal.
A Bayesian risk minimization framework is developed that can incorporate the acoustic-phonetic properties
of speech sounds and knowledge of human auditory perception into the speech enhancement framework. Two noise suppression
systems are presented using the ideas developed in the mathematical framework. In the first system, an aharmonic
comb filter is proposed for voiced speech where low-energy frequencies are severely suppressed while
high-energy frequencies are suppressed mildly. The proposed
system outperformed an MMSE estimator in subjective listening tests and DRT intelligibility test for MELP-coded noisy speech.
The effect of aharmonic
comb filtering on the linear predictive coding (LPC) parameters is analyzed using a missing data approach.
Suppressing the low-energy frequencies without any modification of the high-energy frequencies is shown to
improve the LPC spectrum using the Itakura-Saito distance measure.
The second system combines the aharmonic comb filter with the acoustic-phonetic properties of speech
to improve the intelligibility of the MELP-coded noisy speech.
Noisy speech signal is segmented into broad level sound classes using a multi-sensor automatic
segmentation/classification tool, and each sound class is enhanced differently based on its
acoustic-phonetic properties. The proposed system is shown to outperform both the MELPe noise preprocessor
and the aharmonic comb filter in intelligibility tests when used in concatenation with the MELP coder.
Since the second noise suppression system uses an automatic segmentation/classification algorithm, exploiting the GEMS signal in an automatic
segmentation/classification task is also addressed using an ASR
approach. Current ASR engines can segment and classify speech utterances
in a single pass; however, they are sensitive to ambient noise.
Features that are extracted from the GEMS signal can be fused with the noisy MFCC features
to improve the noise-robustness of the ASR system. In the first phase, a voicing
feature is extracted from the clean speech signal and fused with the MFCC features.
The actual GEMS signal could not be used in this phase because of insufficient sensor data to train the ASR system.
Tests are done using the Aurora2 noisy digits database. The speech-based voicing
feature is found to be effective at around 10 dB but, below 10 dB, the effectiveness rapidly drops with decreasing SNR
because of the severe distortions in the speech-based features at these SNRs. Hence, a novel system is proposed that treats the
MFCC features in a speech frame as missing data if the global SNR is below 10 dB and the speech frame is
unvoiced. If the global SNR…
Advisors/Committee Members: David V. Anderson (Committee Chair), Levent Degertekin (Committee Member), Mark A. Clements (Committee Member), Paul Hasler (Committee Member), Thomas Barnwell (Committee Member).
Subjects/Keywords: Speech intelligibility; Speech quality; GEMS; Multi-sensor; Automatic speech recognition; Speech enhancement; Segmentation-based enhancement; Noise-robust automatic segmentation; Comb filter; Data marginalization; Data fusion; Missing data
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APA (6th Edition):
Demiroglu, C. (2006). Multisensor Segmentation-based Noise Suppression for Intelligibility Improvement in MELP Coders. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/10455
Chicago Manual of Style (16th Edition):
Demiroglu, Cenk. “Multisensor Segmentation-based Noise Suppression for Intelligibility Improvement in MELP Coders.” 2006. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019.
http://hdl.handle.net/1853/10455.
MLA Handbook (7th Edition):
Demiroglu, Cenk. “Multisensor Segmentation-based Noise Suppression for Intelligibility Improvement in MELP Coders.” 2006. Web. 07 Dec 2019.
Vancouver:
Demiroglu C. Multisensor Segmentation-based Noise Suppression for Intelligibility Improvement in MELP Coders. [Internet] [Doctoral dissertation]. Georgia Tech; 2006. [cited 2019 Dec 07].
Available from: http://hdl.handle.net/1853/10455.
Council of Science Editors:
Demiroglu C. Multisensor Segmentation-based Noise Suppression for Intelligibility Improvement in MELP Coders. [Doctoral Dissertation]. Georgia Tech; 2006. Available from: http://hdl.handle.net/1853/10455
Georgia Tech
15.
Srinivasan, Venkatesh.
Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning.
Degree: PhD, Electrical and Computer Engineering, 2006, Georgia Tech
URL: http://hdl.handle.net/1853/11588
► In this work, programmable analog techniques using floating-gate transistors have been developed to design precision analog circuits, low-power signal processing primitives and adaptive systems that…
(more)
▼ In this work, programmable analog techniques using floating-gate transistors have been developed to design precision analog circuits, low-power signal processing primitives and adaptive systems that learn on-chip. Traditional analog implementations lack programmability with the result that issues such as mismatch are corrected at the expense of area. Techniques have been proposed that use floating-gate transistors as an integral part of the circuit of interest to provide both programmability and the ability to correct for mismatch. Traditionally, signal processing has been performed in the digital domain with analog circuits handling the interface with the outside world. Such a partitioning of responsibilities is inefficient as signal processing involves repeated multiplication and addition operations that are both very power efficient in the analog domain. Using programmable analog techniques, fundamental signal processing primitives such as multipliers have been developed in a low-power fashion while preserving accuracy. This results in a paradigm shift in signal processing. A co-operative analog/digital signal processing framework is now possible such that the partitioning of tasks between the analog and digital domains is performed in a power efficient manner. Complex signal processing tasks such as adaptive filtering that learn the weight coefficients are implemented by exploiting the non-linearities inherent with floating-gate programming. The resulting floating-gate synapses are compact, low-power and offer the benefits of non-volatile weight storage. In summary, this research involves developing techniques for improving analog circuit performance and in developing power-efficient techniques for signal processing and on-chip learning.
Advisors/Committee Members: Dr. Paul Hasler (Committee Chair), Dr. Alan Doolittle (Committee Member), Dr. David Anderson (Committee Member), Dr. Farrokh Ayazi (Committee Member), Dr. Mark Smith (Committee Member).
Subjects/Keywords: Programmable multipliers; Adaptive filters; Voltage references; Offset cancellation; Floating-gate transistors; Synapse; Neural networks (Computer science); Signal processing; Adaptive signal processing; Electronic analog computers Circuits; Gate array circuits
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APA (6th Edition):
Srinivasan, V. (2006). Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/11588
Chicago Manual of Style (16th Edition):
Srinivasan, Venkatesh. “Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning.” 2006. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019.
http://hdl.handle.net/1853/11588.
MLA Handbook (7th Edition):
Srinivasan, Venkatesh. “Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning.” 2006. Web. 07 Dec 2019.
Vancouver:
Srinivasan V. Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning. [Internet] [Doctoral dissertation]. Georgia Tech; 2006. [cited 2019 Dec 07].
Available from: http://hdl.handle.net/1853/11588.
Council of Science Editors:
Srinivasan V. Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning. [Doctoral Dissertation]. Georgia Tech; 2006. Available from: http://hdl.handle.net/1853/11588
Georgia Tech
16.
Rosen, Gail L.
Signal processing for biologically-inspired gradient source localization and DNA sequence analysis.
Degree: PhD, Electrical and Computer Engineering, 2006, Georgia Tech
URL: http://hdl.handle.net/1853/11628
► Biological signal processing can help us gain knowledge about biological complexity, as well as using this knowledge to engineer better systems. Three areas are identified…
(more)
▼ Biological signal processing can help us gain knowledge about biological complexity, as well as using this knowledge to engineer better systems. Three areas are identified as critical to understanding biology: 1) understanding DNA, 2) examining the overall biological function and 3) evaluating these systems in environmental (ie: turbulent) conditions.
DNA is investigated for coding structure and redundancy, and a new tandem repeat region, an indicator of a neurodegenerative disease, is discovered. The linear algebraic framework can be used for further analysis and techniques. The work illustrates how signal processing is a tool to reverse engineer biological systems, and how our better understanding of biology can improve engineering designs.
Then, the way a single-cell mobilizes in response to a chemical gradient, known as chemotaxis, is examined. Inspiration from receptor clustering in chemotaxis combined with a Hebbian learning method is shown to improve a gradient-source (chemical/thermal) localization algorithm. The algorithm is implemented, and its performance is evaluated in diffusive and turbulent environments. We then show that sensor cross-correlation can be used in solving chemical localization in difficult turbulent scenarios. This leads into future techniques which can be designed for gradient source tracking. These techniques pave the way for use of biologically-inspired sensor networks in chemical localization.
Advisors/Committee Members: Paul Hasler (Committee Chair), David Anderson (Committee Member), James H. McClellan (Committee Member), Mark T. Smith (Committee Member), Oliver Brand (Committee Member).
Subjects/Keywords: DNA analysis; Ficks second law; Hebbian learning; Biased random walk; Sensor cross-correlation; Delay-and-Sum beamforming; Turbulent plumes; Electronic nose; Tandem repeats; Gradient sensing; Bacterial chemotaxis navigation; Chemotaxis; Sensor networks; Signal processing; Biologically-inspired computing; Chemotaxis; Nervous system Degeneration; Nucleotide sequence
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APA (6th Edition):
Rosen, G. L. (2006). Signal processing for biologically-inspired gradient source localization and DNA sequence analysis. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/11628
Chicago Manual of Style (16th Edition):
Rosen, Gail L. “Signal processing for biologically-inspired gradient source localization and DNA sequence analysis.” 2006. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019.
http://hdl.handle.net/1853/11628.
MLA Handbook (7th Edition):
Rosen, Gail L. “Signal processing for biologically-inspired gradient source localization and DNA sequence analysis.” 2006. Web. 07 Dec 2019.
Vancouver:
Rosen GL. Signal processing for biologically-inspired gradient source localization and DNA sequence analysis. [Internet] [Doctoral dissertation]. Georgia Tech; 2006. [cited 2019 Dec 07].
Available from: http://hdl.handle.net/1853/11628.
Council of Science Editors:
Rosen GL. Signal processing for biologically-inspired gradient source localization and DNA sequence analysis. [Doctoral Dissertation]. Georgia Tech; 2006. Available from: http://hdl.handle.net/1853/11628
Georgia Tech
17.
Yoo, Heejong.
Low-Power Audio Input Enhancement for Portable Devices.
Degree: PhD, Electrical and Computer Engineering, 2005, Georgia Tech
URL: http://hdl.handle.net/1853/6821
► With the development of VLSI and wireless communication technology, portable devices such as personal digital assistants (PDAs), pocket PCs, and mobile phones have gained a…
(more)
▼ With the development of VLSI and wireless communication
technology, portable devices such as personal digital assistants
(PDAs), pocket PCs, and mobile phones have gained a lot of
popularity. Many such devices incorporate a speech recognition
engine, enabling users to interact with the devices using
voice-driven commands and text-to-speech synthesis.
The power consumption of DSP microprocessors has been
consistently decreasing by half about every 18 months, following
Gene's law. The capacity of signal processing, however, is still
significantly constrained by the limited power budget of these
portable devices. In addition, analog-to-digital (A/D) converters
can also limit the signal processing of portable devices. Many
systems require very high-resolution and high-performance A/D
converters, which often consume a large fraction of the limited
power budget of portable devices.
The proposed research develops a low-power audio signal
enhancement system that combines programmable analog signal
processing and traditional digital signal processing. By
utilizing analog signal processing based on floating-gate
transistor technology, the power consumption of the overall
system as well as the complexity of the A/D converters can be
reduced significantly. The system can be used as a front end of
portable devices in which enhancement of audio signal quality
plays a critical role in automatic speech recognition systems on
portable devices. The proposed system performs background audio
noise suppression in a continuous-time domain using analog
computing elements and acoustic echo cancellation in a
discrete-time domain using an FPGA.
Advisors/Committee Members: David V. Anderson (Committee Chair), Brani Vidakovic (Committee Member), Douglas Williams (Committee Member), Paul Hasler (Committee Member), W. Marshall Leach (Committee Member).
Subjects/Keywords: LMS adaptive filter; Low-power processing; CADSP; Floating gate transistors; Speech processing systems; Analog electronic systems; Mobile computing; Portable computers Programming; Signal processing Digital techniques
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APA (6th Edition):
Yoo, H. (2005). Low-Power Audio Input Enhancement for Portable Devices. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/6821
Chicago Manual of Style (16th Edition):
Yoo, Heejong. “Low-Power Audio Input Enhancement for Portable Devices.” 2005. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019.
http://hdl.handle.net/1853/6821.
MLA Handbook (7th Edition):
Yoo, Heejong. “Low-Power Audio Input Enhancement for Portable Devices.” 2005. Web. 07 Dec 2019.
Vancouver:
Yoo H. Low-Power Audio Input Enhancement for Portable Devices. [Internet] [Doctoral dissertation]. Georgia Tech; 2005. [cited 2019 Dec 07].
Available from: http://hdl.handle.net/1853/6821.
Council of Science Editors:
Yoo H. Low-Power Audio Input Enhancement for Portable Devices. [Doctoral Dissertation]. Georgia Tech; 2005. Available from: http://hdl.handle.net/1853/6821
Georgia Tech
18.
Chawla, Ravi.
Power-efficient analog systems to perform signal-processing using floating-gate MOS device for portable applications.
Degree: PhD, Electrical and Computer Engineering, 2005, Georgia Tech
URL: http://hdl.handle.net/1853/6823
► Digital Signal Processors (DSPs) have been an important component of all signal processing systems for over two decades now. Some of the obvious advantages of…
(more)
▼ Digital Signal Processors (DSPs) have been an important component of all signal processing systems for over two decades now. Some of the
obvious advantages of digital signal processing are the flexibility to make specific changes in the processing functions through hardware
or software programming, faster processing speeds of the DSPs, cheaper storage, and retrieval of digital information and lower sensitivity
to electrical noise.
The explosive growth of wireless and signal processing applications has resulted in an increasing demand for such systems with low cost,
low power consumption, and small form factors. With high – level of integration to single – chip systems, power consumption becomes a very
important concern to be addressed. Intermediate – Frequency (IF) band signal processing requires the use of an array of DSPs, operating in
parallel, to meet the speed requirements. This is a power intensive approach and makes use of certain communication schemes impractical in applications where power budget is limited. The front – end ADC and back – end DAC converters required in these systems become expensive when the signal is of wideband nature and a greater resolution is required.
We present techniques to use floating – gate devices to implement signal processing systems in the analog domain in a power efficient and
cost effective manner. Use of floating – gate devices mitigates key limitations in analog signal processing such as the lack of flexibility
to specific changes in processing functions and the lack of programmability. This will impact the way a variety of signal processing systems are designed currently. It also enables array signal processing to be done in an area efficient manner. As will be shown through sample applications, this methodology promises to replace expensive wideband ADC and DAC converters with relatively easy to implement baseband data converters and an array of power intensive high speed DSPs with baseband DSPs. This approach is especially beneficial for portable systems where a lot of applications are running from a single battery.
Advisors/Committee Members: Joy Laskar (Committee Chair), Dave Anderson (Committee Member), Mark T. Smith (Committee Member), Paul Hasler (Committee Member), Phil Allen (Committee Member).
Subjects/Keywords: Floating gate systems
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APA (6th Edition):
Chawla, R. (2005). Power-efficient analog systems to perform signal-processing using floating-gate MOS device for portable applications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/6823
Chicago Manual of Style (16th Edition):
Chawla, Ravi. “Power-efficient analog systems to perform signal-processing using floating-gate MOS device for portable applications.” 2005. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019.
http://hdl.handle.net/1853/6823.
MLA Handbook (7th Edition):
Chawla, Ravi. “Power-efficient analog systems to perform signal-processing using floating-gate MOS device for portable applications.” 2005. Web. 07 Dec 2019.
Vancouver:
Chawla R. Power-efficient analog systems to perform signal-processing using floating-gate MOS device for portable applications. [Internet] [Doctoral dissertation]. Georgia Tech; 2005. [cited 2019 Dec 07].
Available from: http://hdl.handle.net/1853/6823.
Council of Science Editors:
Chawla R. Power-efficient analog systems to perform signal-processing using floating-gate MOS device for portable applications. [Doctoral Dissertation]. Georgia Tech; 2005. Available from: http://hdl.handle.net/1853/6823
. 
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