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You searched for +publisher:"Georgia Tech" +contributor:("Paul Hasler"). Showing records 1 – 18 of 18 total matches.

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1. Gordon, Christal. Bio-inspired, bio-compatible, reconfigurable analog CMOS circuits.

Degree: PhD, Electrical and Computer Engineering, 2009, Georgia Tech

 This work details CMOS, bio-inspired, bio-compatible circuits which were used as synapses between an artificial neuron and a living neuron and between two living neurons.… (more)

Subjects/Keywords: Bio-inspired; Analog; CMOS; Design; Neural interfacing; Neuromorphic; Metal oxide semiconductors, Complementary; Synapses

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APA (6th Edition):

Gordon, C. (2009). Bio-inspired, bio-compatible, reconfigurable analog CMOS circuits. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/37222

Chicago Manual of Style (16th Edition):

Gordon, Christal. “Bio-inspired, bio-compatible, reconfigurable analog CMOS circuits.” 2009. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019. http://hdl.handle.net/1853/37222.

MLA Handbook (7th Edition):

Gordon, Christal. “Bio-inspired, bio-compatible, reconfigurable analog CMOS circuits.” 2009. Web. 07 Dec 2019.

Vancouver:

Gordon C. Bio-inspired, bio-compatible, reconfigurable analog CMOS circuits. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2019 Dec 07]. Available from: http://hdl.handle.net/1853/37222.

Council of Science Editors:

Gordon C. Bio-inspired, bio-compatible, reconfigurable analog CMOS circuits. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/37222


Georgia Tech

2. Marr, Bo. Learning, probabilistic, and asynchronous technologies for an ultra efficient datapath.

Degree: PhD, Electrical and Computer Engineering, 2009, Georgia Tech

 A novel microarchitecture and circuit design techniques are presented for an asynchronous datapath that not only exhibits an extremely high rate of performance, but is… (more)

Subjects/Keywords: Asynchronous; Adaptive; Circuits; Probabilistic computing; Low power; Energy efficient; Energy consumption; Asynchronous circuits; Signal processing Digital techniques

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APA (6th Edition):

Marr, B. (2009). Learning, probabilistic, and asynchronous technologies for an ultra efficient datapath. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/31724

Chicago Manual of Style (16th Edition):

Marr, Bo. “Learning, probabilistic, and asynchronous technologies for an ultra efficient datapath.” 2009. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019. http://hdl.handle.net/1853/31724.

MLA Handbook (7th Edition):

Marr, Bo. “Learning, probabilistic, and asynchronous technologies for an ultra efficient datapath.” 2009. Web. 07 Dec 2019.

Vancouver:

Marr B. Learning, probabilistic, and asynchronous technologies for an ultra efficient datapath. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2019 Dec 07]. Available from: http://hdl.handle.net/1853/31724.

Council of Science Editors:

Marr B. Learning, probabilistic, and asynchronous technologies for an ultra efficient datapath. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/31724


Georgia Tech

3. Wunderlich, Richard Bryan. CMOS gate delay, power measurements and characterization with logical effort and logical power.

Degree: MS, Electrical and Computer Engineering, 2009, Georgia Tech

 The primary metrics associated with a logic gate's performance are speed, power, and area. We define a gate as a specific CMOS transistor level implementation… (more)

Subjects/Keywords: Speed; Power; Logical power; Logical effort; Analysis; Logic design; Logic circuits

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APA (6th Edition):

Wunderlich, R. B. (2009). CMOS gate delay, power measurements and characterization with logical effort and logical power. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/31652

Chicago Manual of Style (16th Edition):

Wunderlich, Richard Bryan. “CMOS gate delay, power measurements and characterization with logical effort and logical power.” 2009. Masters Thesis, Georgia Tech. Accessed December 07, 2019. http://hdl.handle.net/1853/31652.

MLA Handbook (7th Edition):

Wunderlich, Richard Bryan. “CMOS gate delay, power measurements and characterization with logical effort and logical power.” 2009. Web. 07 Dec 2019.

Vancouver:

Wunderlich RB. CMOS gate delay, power measurements and characterization with logical effort and logical power. [Internet] [Masters thesis]. Georgia Tech; 2009. [cited 2019 Dec 07]. Available from: http://hdl.handle.net/1853/31652.

Council of Science Editors:

Wunderlich RB. CMOS gate delay, power measurements and characterization with logical effort and logical power. [Masters Thesis]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/31652


Georgia Tech

4. Petre, Csaba. Sim2spice, a tool for compiling simulink designs on FPAA and applications to neuromorphic circuits.

Degree: MS, Electrical and Computer Engineering, 2009, Georgia Tech

 Analog circuit technology is of vital importance in today's world of electronic design. Increasing prevalence of mobile electronics necessitates the search for solutions which offer… (more)

Subjects/Keywords: Analog; Neuromorphic; FPAA; Simulink; Field programmable gate arrays; Signal processing; Linear integrated circuits

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APA (6th Edition):

Petre, C. (2009). Sim2spice, a tool for compiling simulink designs on FPAA and applications to neuromorphic circuits. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/31820

Chicago Manual of Style (16th Edition):

Petre, Csaba. “Sim2spice, a tool for compiling simulink designs on FPAA and applications to neuromorphic circuits.” 2009. Masters Thesis, Georgia Tech. Accessed December 07, 2019. http://hdl.handle.net/1853/31820.

MLA Handbook (7th Edition):

Petre, Csaba. “Sim2spice, a tool for compiling simulink designs on FPAA and applications to neuromorphic circuits.” 2009. Web. 07 Dec 2019.

Vancouver:

Petre C. Sim2spice, a tool for compiling simulink designs on FPAA and applications to neuromorphic circuits. [Internet] [Masters thesis]. Georgia Tech; 2009. [cited 2019 Dec 07]. Available from: http://hdl.handle.net/1853/31820.

Council of Science Editors:

Petre C. Sim2spice, a tool for compiling simulink designs on FPAA and applications to neuromorphic circuits. [Masters Thesis]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/31820

5. Horst, Stephen J. Frequency synthesis applications of SiGe BiCMOS processes.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 Silicon Germanium BiCMOS technology has been demonstrated as an ideal platform for highly integrated systems requiring both high performance analog and RF circuits as well… (more)

Subjects/Keywords: Radiation hardening; Phase noise measurements; Frequency synthesizers; Signal generators; Semiconductors; Analog electronic systems

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APA (6th Edition):

Horst, S. J. (2011). Frequency synthesis applications of SiGe BiCMOS processes. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/42815

Chicago Manual of Style (16th Edition):

Horst, Stephen J. “Frequency synthesis applications of SiGe BiCMOS processes.” 2011. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019. http://hdl.handle.net/1853/42815.

MLA Handbook (7th Edition):

Horst, Stephen J. “Frequency synthesis applications of SiGe BiCMOS processes.” 2011. Web. 07 Dec 2019.

Vancouver:

Horst SJ. Frequency synthesis applications of SiGe BiCMOS processes. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Dec 07]. Available from: http://hdl.handle.net/1853/42815.

Council of Science Editors:

Horst SJ. Frequency synthesis applications of SiGe BiCMOS processes. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/42815

6. Baskaya, Ismail Faik. Physical design automation for large scale field programmable analog arrays.

Degree: PhD, Electrical and Computer Engineering, 2009, Georgia Tech

 Field-programmable analog arrays (FPAA) are integrated circuits with a collection of analog building blocks connected through a wire and switch fabric to achieve reconfigurability similar… (more)

Subjects/Keywords: FPAA; Reconfigurable analog arrays; Placement; Routing; Parasitic extraction; Architecture exploration; Field programmable gate arrays; Integrated circuits; Integrated circuits Design and construction; Linear integrated circuits

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APA (6th Edition):

Baskaya, I. F. (2009). Physical design automation for large scale field programmable analog arrays. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/31810

Chicago Manual of Style (16th Edition):

Baskaya, Ismail Faik. “Physical design automation for large scale field programmable analog arrays.” 2009. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019. http://hdl.handle.net/1853/31810.

MLA Handbook (7th Edition):

Baskaya, Ismail Faik. “Physical design automation for large scale field programmable analog arrays.” 2009. Web. 07 Dec 2019.

Vancouver:

Baskaya IF. Physical design automation for large scale field programmable analog arrays. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2019 Dec 07]. Available from: http://hdl.handle.net/1853/31810.

Council of Science Editors:

Baskaya IF. Physical design automation for large scale field programmable analog arrays. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/31810


Georgia Tech

7. Levy, Michael Yehuda. Calculation of the Band Properties of a Quantum Dot Intermediate Band Solar Cell with Centrally Located Hydrogenic Impurities.

Degree: MS, Electrical and Computer Engineering, 2004, Georgia Tech

 In the quantum dot implementation of an intermediate band solar cell presented in this thesis, the offset of the intermediate band with respect to the… (more)

Subjects/Keywords: Intermediate band solar cell; Quantum dots; Hydrogenic impurity

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APA (6th Edition):

Levy, M. Y. (2004). Calculation of the Band Properties of a Quantum Dot Intermediate Band Solar Cell with Centrally Located Hydrogenic Impurities. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/5072

Chicago Manual of Style (16th Edition):

Levy, Michael Yehuda. “Calculation of the Band Properties of a Quantum Dot Intermediate Band Solar Cell with Centrally Located Hydrogenic Impurities.” 2004. Masters Thesis, Georgia Tech. Accessed December 07, 2019. http://hdl.handle.net/1853/5072.

MLA Handbook (7th Edition):

Levy, Michael Yehuda. “Calculation of the Band Properties of a Quantum Dot Intermediate Band Solar Cell with Centrally Located Hydrogenic Impurities.” 2004. Web. 07 Dec 2019.

Vancouver:

Levy MY. Calculation of the Band Properties of a Quantum Dot Intermediate Band Solar Cell with Centrally Located Hydrogenic Impurities. [Internet] [Masters thesis]. Georgia Tech; 2004. [cited 2019 Dec 07]. Available from: http://hdl.handle.net/1853/5072.

Council of Science Editors:

Levy MY. Calculation of the Band Properties of a Quantum Dot Intermediate Band Solar Cell with Centrally Located Hydrogenic Impurities. [Masters Thesis]. Georgia Tech; 2004. Available from: http://hdl.handle.net/1853/5072


Georgia Tech

8. Abramson, David. MITE Architectures for Reconfigurable Analog Arrays.

Degree: MS, Electrical and Computer Engineering, 2004, Georgia Tech

 With the introduction of the floating-gate transistor into reconfigurable architectures, great advances have been made in the field. Recently, Hall et. al. have proposed the… (more)

Subjects/Keywords: MITE; Analog; FPAA; Programmable; Reconfigurable; Field programmable gate arrays; Electronic analog computers Circuits; Translinear

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APA (6th Edition):

Abramson, D. (2004). MITE Architectures for Reconfigurable Analog Arrays. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/4920

Chicago Manual of Style (16th Edition):

Abramson, David. “MITE Architectures for Reconfigurable Analog Arrays.” 2004. Masters Thesis, Georgia Tech. Accessed December 07, 2019. http://hdl.handle.net/1853/4920.

MLA Handbook (7th Edition):

Abramson, David. “MITE Architectures for Reconfigurable Analog Arrays.” 2004. Web. 07 Dec 2019.

Vancouver:

Abramson D. MITE Architectures for Reconfigurable Analog Arrays. [Internet] [Masters thesis]. Georgia Tech; 2004. [cited 2019 Dec 07]. Available from: http://hdl.handle.net/1853/4920.

Council of Science Editors:

Abramson D. MITE Architectures for Reconfigurable Analog Arrays. [Masters Thesis]. Georgia Tech; 2004. Available from: http://hdl.handle.net/1853/4920


Georgia Tech

9. Robucci, Ryan. On Chip Error Compensation, Light Adaptation, and Image Enhancement with a CMOS Transform Image Sensor.

Degree: MS, Electrical and Computer Engineering, 2005, Georgia Tech

 CMOS imagers are replacing CCD imagers in many applications and will continue to make new applications possible. CMOS imaging offers lower cost implementations on standard… (more)

Subjects/Keywords: CMOS imager; Metal oxide semiconductors, Complementary; Optical detectors; Imaging systems

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APA (6th Edition):

Robucci, R. (2005). On Chip Error Compensation, Light Adaptation, and Image Enhancement with a CMOS Transform Image Sensor. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/6986

Chicago Manual of Style (16th Edition):

Robucci, Ryan. “On Chip Error Compensation, Light Adaptation, and Image Enhancement with a CMOS Transform Image Sensor.” 2005. Masters Thesis, Georgia Tech. Accessed December 07, 2019. http://hdl.handle.net/1853/6986.

MLA Handbook (7th Edition):

Robucci, Ryan. “On Chip Error Compensation, Light Adaptation, and Image Enhancement with a CMOS Transform Image Sensor.” 2005. Web. 07 Dec 2019.

Vancouver:

Robucci R. On Chip Error Compensation, Light Adaptation, and Image Enhancement with a CMOS Transform Image Sensor. [Internet] [Masters thesis]. Georgia Tech; 2005. [cited 2019 Dec 07]. Available from: http://hdl.handle.net/1853/6986.

Council of Science Editors:

Robucci R. On Chip Error Compensation, Light Adaptation, and Image Enhancement with a CMOS Transform Image Sensor. [Masters Thesis]. Georgia Tech; 2005. Available from: http://hdl.handle.net/1853/6986


Georgia Tech

10. Twigg, Christopher M. Floating Gate Based Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing.

Degree: PhD, Electrical and Computer Engineering, 2006, Georgia Tech

 Large-scale reconfigurable and programmable analog devices provide a new option for prototyping and synthesizing analog circuits for analog signal processing and beyond. Field-programmable analog arrays… (more)

Subjects/Keywords: fpaa reconfigurable programmable analog; Signal processing; Linear integrated circuits; Integrated circuits Very large scale integration; Field programmable gate arrays

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APA (6th Edition):

Twigg, C. M. (2006). Floating Gate Based Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/11601

Chicago Manual of Style (16th Edition):

Twigg, Christopher M. “Floating Gate Based Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing.” 2006. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019. http://hdl.handle.net/1853/11601.

MLA Handbook (7th Edition):

Twigg, Christopher M. “Floating Gate Based Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing.” 2006. Web. 07 Dec 2019.

Vancouver:

Twigg CM. Floating Gate Based Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing. [Internet] [Doctoral dissertation]. Georgia Tech; 2006. [cited 2019 Dec 07]. Available from: http://hdl.handle.net/1853/11601.

Council of Science Editors:

Twigg CM. Floating Gate Based Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing. [Doctoral Dissertation]. Georgia Tech; 2006. Available from: http://hdl.handle.net/1853/11601


Georgia Tech

11. Hyun, Seok Hun. Design of High-Speed Laser Driver Using a Standard CMOS Technology for Optical Data Transmission.

Degree: PhD, Electrical and Computer Engineering, 2004, Georgia Tech

 Many researchers and engineers designing laser drivers for data rates at or above 10 gigabits per second (Gbps) implemented their designs using integrated circuit technologies… (more)

Subjects/Keywords: Optical communications; Laser driver; CMOS; Hybrid integration

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APA (6th Edition):

Hyun, S. H. (2004). Design of High-Speed Laser Driver Using a Standard CMOS Technology for Optical Data Transmission. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/4903

Chicago Manual of Style (16th Edition):

Hyun, Seok Hun. “Design of High-Speed Laser Driver Using a Standard CMOS Technology for Optical Data Transmission.” 2004. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019. http://hdl.handle.net/1853/4903.

MLA Handbook (7th Edition):

Hyun, Seok Hun. “Design of High-Speed Laser Driver Using a Standard CMOS Technology for Optical Data Transmission.” 2004. Web. 07 Dec 2019.

Vancouver:

Hyun SH. Design of High-Speed Laser Driver Using a Standard CMOS Technology for Optical Data Transmission. [Internet] [Doctoral dissertation]. Georgia Tech; 2004. [cited 2019 Dec 07]. Available from: http://hdl.handle.net/1853/4903.

Council of Science Editors:

Hyun SH. Design of High-Speed Laser Driver Using a Standard CMOS Technology for Optical Data Transmission. [Doctoral Dissertation]. Georgia Tech; 2004. Available from: http://hdl.handle.net/1853/4903


Georgia Tech

12. Dugger, Jeffery Don. Adaptive Analog VLSI Signal Processing and Neural Networks.

Degree: PhD, Electrical and Computer Engineering, 2003, Georgia Tech

 Research presented in this thesis provides a substantial leap from the study of interesting device physics to fully adaptive analog networks and lays a solid… (more)

Subjects/Keywords: Floating gate transistors; Neural networks; Adaptive filters; VLSI; Analog electronics

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APA (6th Edition):

Dugger, J. D. (2003). Adaptive Analog VLSI Signal Processing and Neural Networks. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/5294

Chicago Manual of Style (16th Edition):

Dugger, Jeffery Don. “Adaptive Analog VLSI Signal Processing and Neural Networks.” 2003. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019. http://hdl.handle.net/1853/5294.

MLA Handbook (7th Edition):

Dugger, Jeffery Don. “Adaptive Analog VLSI Signal Processing and Neural Networks.” 2003. Web. 07 Dec 2019.

Vancouver:

Dugger JD. Adaptive Analog VLSI Signal Processing and Neural Networks. [Internet] [Doctoral dissertation]. Georgia Tech; 2003. [cited 2019 Dec 07]. Available from: http://hdl.handle.net/1853/5294.

Council of Science Editors:

Dugger JD. Adaptive Analog VLSI Signal Processing and Neural Networks. [Doctoral Dissertation]. Georgia Tech; 2003. Available from: http://hdl.handle.net/1853/5294


Georgia Tech

13. Sharma, Ajit. CMOS systems and circuits for sub-degree per hour MEMS gyroscopes.

Degree: PhD, Electrical and Computer Engineering, 2007, Georgia Tech

 The objective of our research is to develop system architectures and CMOS circuits that interface with high-Q silicon microgyroscopes to implement navigation-grade angular rate sensors.… (more)

Subjects/Keywords: MEMS; Gyroscopes; Data converters; Transimpedance amplifiers; Low-noise; Bias drift; Mode-matching; Detectors; Noise control; Transducers – Drift; Gyroscopic instruments

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APA (6th Edition):

Sharma, A. (2007). CMOS systems and circuits for sub-degree per hour MEMS gyroscopes. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/26636

Chicago Manual of Style (16th Edition):

Sharma, Ajit. “CMOS systems and circuits for sub-degree per hour MEMS gyroscopes.” 2007. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019. http://hdl.handle.net/1853/26636.

MLA Handbook (7th Edition):

Sharma, Ajit. “CMOS systems and circuits for sub-degree per hour MEMS gyroscopes.” 2007. Web. 07 Dec 2019.

Vancouver:

Sharma A. CMOS systems and circuits for sub-degree per hour MEMS gyroscopes. [Internet] [Doctoral dissertation]. Georgia Tech; 2007. [cited 2019 Dec 07]. Available from: http://hdl.handle.net/1853/26636.

Council of Science Editors:

Sharma A. CMOS systems and circuits for sub-degree per hour MEMS gyroscopes. [Doctoral Dissertation]. Georgia Tech; 2007. Available from: http://hdl.handle.net/1853/26636


Georgia Tech

14. Demiroglu, Cenk. Multisensor Segmentation-based Noise Suppression for Intelligibility Improvement in MELP Coders.

Degree: PhD, Electrical and Computer Engineering, 2006, Georgia Tech

 This thesis investigates the use of an auxiliary sensor, the GEMS device, for improving the quality of noisy speech and designing noise preprocessors to MELP… (more)

Subjects/Keywords: Speech intelligibility; Speech quality; GEMS; Multi-sensor; Automatic speech recognition; Speech enhancement; Segmentation-based enhancement; Noise-robust automatic segmentation; Comb filter; Data marginalization; Data fusion; Missing data

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APA (6th Edition):

Demiroglu, C. (2006). Multisensor Segmentation-based Noise Suppression for Intelligibility Improvement in MELP Coders. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/10455

Chicago Manual of Style (16th Edition):

Demiroglu, Cenk. “Multisensor Segmentation-based Noise Suppression for Intelligibility Improvement in MELP Coders.” 2006. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019. http://hdl.handle.net/1853/10455.

MLA Handbook (7th Edition):

Demiroglu, Cenk. “Multisensor Segmentation-based Noise Suppression for Intelligibility Improvement in MELP Coders.” 2006. Web. 07 Dec 2019.

Vancouver:

Demiroglu C. Multisensor Segmentation-based Noise Suppression for Intelligibility Improvement in MELP Coders. [Internet] [Doctoral dissertation]. Georgia Tech; 2006. [cited 2019 Dec 07]. Available from: http://hdl.handle.net/1853/10455.

Council of Science Editors:

Demiroglu C. Multisensor Segmentation-based Noise Suppression for Intelligibility Improvement in MELP Coders. [Doctoral Dissertation]. Georgia Tech; 2006. Available from: http://hdl.handle.net/1853/10455


Georgia Tech

15. Srinivasan, Venkatesh. Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning.

Degree: PhD, Electrical and Computer Engineering, 2006, Georgia Tech

 In this work, programmable analog techniques using floating-gate transistors have been developed to design precision analog circuits, low-power signal processing primitives and adaptive systems that… (more)

Subjects/Keywords: Programmable multipliers; Adaptive filters; Voltage references; Offset cancellation; Floating-gate transistors; Synapse; Neural networks (Computer science); Signal processing; Adaptive signal processing; Electronic analog computers Circuits; Gate array circuits

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APA (6th Edition):

Srinivasan, V. (2006). Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/11588

Chicago Manual of Style (16th Edition):

Srinivasan, Venkatesh. “Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning.” 2006. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019. http://hdl.handle.net/1853/11588.

MLA Handbook (7th Edition):

Srinivasan, Venkatesh. “Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning.” 2006. Web. 07 Dec 2019.

Vancouver:

Srinivasan V. Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning. [Internet] [Doctoral dissertation]. Georgia Tech; 2006. [cited 2019 Dec 07]. Available from: http://hdl.handle.net/1853/11588.

Council of Science Editors:

Srinivasan V. Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning. [Doctoral Dissertation]. Georgia Tech; 2006. Available from: http://hdl.handle.net/1853/11588


Georgia Tech

16. Rosen, Gail L. Signal processing for biologically-inspired gradient source localization and DNA sequence analysis.

Degree: PhD, Electrical and Computer Engineering, 2006, Georgia Tech

 Biological signal processing can help us gain knowledge about biological complexity, as well as using this knowledge to engineer better systems. Three areas are identified… (more)

Subjects/Keywords: DNA analysis; Ficks second law; Hebbian learning; Biased random walk; Sensor cross-correlation; Delay-and-Sum beamforming; Turbulent plumes; Electronic nose; Tandem repeats; Gradient sensing; Bacterial chemotaxis navigation; Chemotaxis; Sensor networks; Signal processing; Biologically-inspired computing; Chemotaxis; Nervous system Degeneration; Nucleotide sequence

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APA (6th Edition):

Rosen, G. L. (2006). Signal processing for biologically-inspired gradient source localization and DNA sequence analysis. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/11628

Chicago Manual of Style (16th Edition):

Rosen, Gail L. “Signal processing for biologically-inspired gradient source localization and DNA sequence analysis.” 2006. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019. http://hdl.handle.net/1853/11628.

MLA Handbook (7th Edition):

Rosen, Gail L. “Signal processing for biologically-inspired gradient source localization and DNA sequence analysis.” 2006. Web. 07 Dec 2019.

Vancouver:

Rosen GL. Signal processing for biologically-inspired gradient source localization and DNA sequence analysis. [Internet] [Doctoral dissertation]. Georgia Tech; 2006. [cited 2019 Dec 07]. Available from: http://hdl.handle.net/1853/11628.

Council of Science Editors:

Rosen GL. Signal processing for biologically-inspired gradient source localization and DNA sequence analysis. [Doctoral Dissertation]. Georgia Tech; 2006. Available from: http://hdl.handle.net/1853/11628


Georgia Tech

17. Yoo, Heejong. Low-Power Audio Input Enhancement for Portable Devices.

Degree: PhD, Electrical and Computer Engineering, 2005, Georgia Tech

 With the development of VLSI and wireless communication technology, portable devices such as personal digital assistants (PDAs), pocket PCs, and mobile phones have gained a… (more)

Subjects/Keywords: LMS adaptive filter; Low-power processing; CADSP; Floating gate transistors; Speech processing systems; Analog electronic systems; Mobile computing; Portable computers Programming; Signal processing Digital techniques

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APA (6th Edition):

Yoo, H. (2005). Low-Power Audio Input Enhancement for Portable Devices. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/6821

Chicago Manual of Style (16th Edition):

Yoo, Heejong. “Low-Power Audio Input Enhancement for Portable Devices.” 2005. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019. http://hdl.handle.net/1853/6821.

MLA Handbook (7th Edition):

Yoo, Heejong. “Low-Power Audio Input Enhancement for Portable Devices.” 2005. Web. 07 Dec 2019.

Vancouver:

Yoo H. Low-Power Audio Input Enhancement for Portable Devices. [Internet] [Doctoral dissertation]. Georgia Tech; 2005. [cited 2019 Dec 07]. Available from: http://hdl.handle.net/1853/6821.

Council of Science Editors:

Yoo H. Low-Power Audio Input Enhancement for Portable Devices. [Doctoral Dissertation]. Georgia Tech; 2005. Available from: http://hdl.handle.net/1853/6821


Georgia Tech

18. Chawla, Ravi. Power-efficient analog systems to perform signal-processing using floating-gate MOS device for portable applications.

Degree: PhD, Electrical and Computer Engineering, 2005, Georgia Tech

 Digital Signal Processors (DSPs) have been an important component of all signal processing systems for over two decades now. Some of the obvious advantages of… (more)

Subjects/Keywords: Floating gate systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chawla, R. (2005). Power-efficient analog systems to perform signal-processing using floating-gate MOS device for portable applications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/6823

Chicago Manual of Style (16th Edition):

Chawla, Ravi. “Power-efficient analog systems to perform signal-processing using floating-gate MOS device for portable applications.” 2005. Doctoral Dissertation, Georgia Tech. Accessed December 07, 2019. http://hdl.handle.net/1853/6823.

MLA Handbook (7th Edition):

Chawla, Ravi. “Power-efficient analog systems to perform signal-processing using floating-gate MOS device for portable applications.” 2005. Web. 07 Dec 2019.

Vancouver:

Chawla R. Power-efficient analog systems to perform signal-processing using floating-gate MOS device for portable applications. [Internet] [Doctoral dissertation]. Georgia Tech; 2005. [cited 2019 Dec 07]. Available from: http://hdl.handle.net/1853/6823.

Council of Science Editors:

Chawla R. Power-efficient analog systems to perform signal-processing using floating-gate MOS device for portable applications. [Doctoral Dissertation]. Georgia Tech; 2005. Available from: http://hdl.handle.net/1853/6823

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