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You searched for +publisher:"Georgia Tech" +contributor:("Naeemi, Azad J"). Showing records 1 – 13 of 13 total matches.

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Georgia Tech

1. Philip, Timothy. Error analysis of boundary conditions in the Wigner transport equation.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 This work presents a method to quantitatively calculate the error induced through application of approximate boundary conditions in quantum charge transport simulations based on the… (more)

Subjects/Keywords: Wigner transport equation; Boundary conditions; Error analysis

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APA (6th Edition):

Philip, T. (2014). Error analysis of boundary conditions in the Wigner transport equation. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54031

Chicago Manual of Style (16th Edition):

Philip, Timothy. “Error analysis of boundary conditions in the Wigner transport equation.” 2014. Masters Thesis, Georgia Tech. Accessed December 11, 2019. http://hdl.handle.net/1853/54031.

MLA Handbook (7th Edition):

Philip, Timothy. “Error analysis of boundary conditions in the Wigner transport equation.” 2014. Web. 11 Dec 2019.

Vancouver:

Philip T. Error analysis of boundary conditions in the Wigner transport equation. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Dec 11]. Available from: http://hdl.handle.net/1853/54031.

Council of Science Editors:

Philip T. Error analysis of boundary conditions in the Wigner transport equation. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/54031


Georgia Tech

2. Kim, Woongrae. Memory BIST with Statistical Failure Analysis for Diagnosis of Resistive-Open Defects due to Electromigration and Stress-Induced Voiding in an SRAM.

Degree: MS, Electrical and Computer Engineering, 2016, Georgia Tech

 The object of the research has been to develop built-in self-test and statistical failure analysis methodologies for electrical detection and diagnosis of backend wearout mechanisms… (more)

Subjects/Keywords: BIST; statistical failure analysis; EM; SIV; SRAM

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APA (6th Edition):

Kim, W. (2016). Memory BIST with Statistical Failure Analysis for Diagnosis of Resistive-Open Defects due to Electromigration and Stress-Induced Voiding in an SRAM. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56191

Chicago Manual of Style (16th Edition):

Kim, Woongrae. “Memory BIST with Statistical Failure Analysis for Diagnosis of Resistive-Open Defects due to Electromigration and Stress-Induced Voiding in an SRAM.” 2016. Masters Thesis, Georgia Tech. Accessed December 11, 2019. http://hdl.handle.net/1853/56191.

MLA Handbook (7th Edition):

Kim, Woongrae. “Memory BIST with Statistical Failure Analysis for Diagnosis of Resistive-Open Defects due to Electromigration and Stress-Induced Voiding in an SRAM.” 2016. Web. 11 Dec 2019.

Vancouver:

Kim W. Memory BIST with Statistical Failure Analysis for Diagnosis of Resistive-Open Defects due to Electromigration and Stress-Induced Voiding in an SRAM. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2019 Dec 11]. Available from: http://hdl.handle.net/1853/56191.

Council of Science Editors:

Kim W. Memory BIST with Statistical Failure Analysis for Diagnosis of Resistive-Open Defects due to Electromigration and Stress-Induced Voiding in an SRAM. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56191


Georgia Tech

3. Chakraborty, Partha Sarathi. Design, scaling and reliability of devices for high-performance mixed-signal applications.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 This research investigates and gains new understanding on how silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device design couples with both performance scaling and reliability for… (more)

Subjects/Keywords: Silicon-germanium; Heterojunction bipolar transistor; TCAD; Scaling; Reliability; Device design; Mixed-signal; Simulation; High-frequency; Cryogenic temperature; Characterization

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APA (6th Edition):

Chakraborty, P. S. (2015). Design, scaling and reliability of devices for high-performance mixed-signal applications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58137

Chicago Manual of Style (16th Edition):

Chakraborty, Partha Sarathi. “Design, scaling and reliability of devices for high-performance mixed-signal applications.” 2015. Doctoral Dissertation, Georgia Tech. Accessed December 11, 2019. http://hdl.handle.net/1853/58137.

MLA Handbook (7th Edition):

Chakraborty, Partha Sarathi. “Design, scaling and reliability of devices for high-performance mixed-signal applications.” 2015. Web. 11 Dec 2019.

Vancouver:

Chakraborty PS. Design, scaling and reliability of devices for high-performance mixed-signal applications. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Dec 11]. Available from: http://hdl.handle.net/1853/58137.

Council of Science Editors:

Chakraborty PS. Design, scaling and reliability of devices for high-performance mixed-signal applications. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/58137


Georgia Tech

4. Kani, Nickvash. Modeling of magnetization dynamics and applications to spin-based logic and memory devices.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 The objective of this research is to develop models to better evaluate the performance and reliability of proposed spin-based boolean devices. This research will focus… (more)

Subjects/Keywords: Nanomagnet; Dipolar coupling; Spin-transfer torque; Magnetic tunnel junction; Spin-switch; Spintronics; Straintronics; Magnetization dynamics

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APA (6th Edition):

Kani, N. (2017). Modeling of magnetization dynamics and applications to spin-based logic and memory devices. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59242

Chicago Manual of Style (16th Edition):

Kani, Nickvash. “Modeling of magnetization dynamics and applications to spin-based logic and memory devices.” 2017. Doctoral Dissertation, Georgia Tech. Accessed December 11, 2019. http://hdl.handle.net/1853/59242.

MLA Handbook (7th Edition):

Kani, Nickvash. “Modeling of magnetization dynamics and applications to spin-based logic and memory devices.” 2017. Web. 11 Dec 2019.

Vancouver:

Kani N. Modeling of magnetization dynamics and applications to spin-based logic and memory devices. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Dec 11]. Available from: http://hdl.handle.net/1853/59242.

Council of Science Editors:

Kani N. Modeling of magnetization dynamics and applications to spin-based logic and memory devices. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59242


Georgia Tech

5. Zhang, Yang. Thermal and power delivery network modeling for emerging microelectronic integration platforms.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 In this dissertation, thermal management and power delivery challenges in 2.5-D and 3-D integration are presented. To address the thermal coupling issues in heterogeneous 3-D… (more)

Subjects/Keywords: 3D-IC, 2.5-D IC, Thermal, Power delivery, Signaling; 2.5-D IC; Thermal; Power delivery; Signaling

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APA (6th Edition):

Zhang, Y. (2017). Thermal and power delivery network modeling for emerging microelectronic integration platforms. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59199

Chicago Manual of Style (16th Edition):

Zhang, Yang. “Thermal and power delivery network modeling for emerging microelectronic integration platforms.” 2017. Doctoral Dissertation, Georgia Tech. Accessed December 11, 2019. http://hdl.handle.net/1853/59199.

MLA Handbook (7th Edition):

Zhang, Yang. “Thermal and power delivery network modeling for emerging microelectronic integration platforms.” 2017. Web. 11 Dec 2019.

Vancouver:

Zhang Y. Thermal and power delivery network modeling for emerging microelectronic integration platforms. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Dec 11]. Available from: http://hdl.handle.net/1853/59199.

Council of Science Editors:

Zhang Y. Thermal and power delivery network modeling for emerging microelectronic integration platforms. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59199


Georgia Tech

6. Cha, Soonyoung. Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 The objective of this research is to extract NBTI and GOBD model parameters to enable the estimation of the degradation and the remaining life of… (more)

Subjects/Keywords: Design for reliability and yield enhancement; Device-level and system-level reliability modeling

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APA (6th Edition):

Cha, S. (2017). Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59748

Chicago Manual of Style (16th Edition):

Cha, Soonyoung. “Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system.” 2017. Doctoral Dissertation, Georgia Tech. Accessed December 11, 2019. http://hdl.handle.net/1853/59748.

MLA Handbook (7th Edition):

Cha, Soonyoung. “Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system.” 2017. Web. 11 Dec 2019.

Vancouver:

Cha S. Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Dec 11]. Available from: http://hdl.handle.net/1853/59748.

Council of Science Editors:

Cha S. Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59748


Georgia Tech

7. Vail, Owen. Fabrication and characterization of epitaxial graphene nanoribbon transport devices.

Degree: PhD, Physics, 2017, Georgia Tech

 Patterned growth of epitaxial graphene has piqued the interest of the scientific community by revealing an interesting structure with a lot of potential: the sidewall… (more)

Subjects/Keywords: Epitaxial graphene nanoribbons; Superconducting proximity effect; 1/f noise

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APA (6th Edition):

Vail, O. (2017). Fabrication and characterization of epitaxial graphene nanoribbon transport devices. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59774

Chicago Manual of Style (16th Edition):

Vail, Owen. “Fabrication and characterization of epitaxial graphene nanoribbon transport devices.” 2017. Doctoral Dissertation, Georgia Tech. Accessed December 11, 2019. http://hdl.handle.net/1853/59774.

MLA Handbook (7th Edition):

Vail, Owen. “Fabrication and characterization of epitaxial graphene nanoribbon transport devices.” 2017. Web. 11 Dec 2019.

Vancouver:

Vail O. Fabrication and characterization of epitaxial graphene nanoribbon transport devices. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Dec 11]. Available from: http://hdl.handle.net/1853/59774.

Council of Science Editors:

Vail O. Fabrication and characterization of epitaxial graphene nanoribbon transport devices. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59774


Georgia Tech

8. Madapusi Srinivas Prasad, Divya. A Holistic Study of On-Chip Interconnect Technology: From Modeling Theory to Physical Design of Semiconductor ICs.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The objective of this research is to present a holistic study of the on-chip copper interconnect technology, from interconnect modeling to their manifestation in modern… (more)

Subjects/Keywords: On-Chip Interconnect; Design-Technology-Co-Optimization; Physical Design; Rent's Rule; System-level modeling; Performance model.

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APA (6th Edition):

Madapusi Srinivas Prasad, D. (2018). A Holistic Study of On-Chip Interconnect Technology: From Modeling Theory to Physical Design of Semiconductor ICs. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61606

Chicago Manual of Style (16th Edition):

Madapusi Srinivas Prasad, Divya. “A Holistic Study of On-Chip Interconnect Technology: From Modeling Theory to Physical Design of Semiconductor ICs.” 2018. Doctoral Dissertation, Georgia Tech. Accessed December 11, 2019. http://hdl.handle.net/1853/61606.

MLA Handbook (7th Edition):

Madapusi Srinivas Prasad, Divya. “A Holistic Study of On-Chip Interconnect Technology: From Modeling Theory to Physical Design of Semiconductor ICs.” 2018. Web. 11 Dec 2019.

Vancouver:

Madapusi Srinivas Prasad D. A Holistic Study of On-Chip Interconnect Technology: From Modeling Theory to Physical Design of Semiconductor ICs. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Dec 11]. Available from: http://hdl.handle.net/1853/61606.

Council of Science Editors:

Madapusi Srinivas Prasad D. A Holistic Study of On-Chip Interconnect Technology: From Modeling Theory to Physical Design of Semiconductor ICs. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/61606

9. Panth, Shreepad Amar. Physical design methodologies for monolithic 3D ICs.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The objective of this research is to develop physical design methodologies for monolithic 3D ICs and use them to evaluate the improvements in the power-performance… (more)

Subjects/Keywords: 3D IC; Physical design; Monolithic inter-tier via; Placement; Routing

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APA (6th Edition):

Panth, S. A. (2015). Physical design methodologies for monolithic 3D ICs. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53542

Chicago Manual of Style (16th Edition):

Panth, Shreepad Amar. “Physical design methodologies for monolithic 3D ICs.” 2015. Doctoral Dissertation, Georgia Tech. Accessed December 11, 2019. http://hdl.handle.net/1853/53542.

MLA Handbook (7th Edition):

Panth, Shreepad Amar. “Physical design methodologies for monolithic 3D ICs.” 2015. Web. 11 Dec 2019.

Vancouver:

Panth SA. Physical design methodologies for monolithic 3D ICs. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Dec 11]. Available from: http://hdl.handle.net/1853/53542.

Council of Science Editors:

Panth SA. Physical design methodologies for monolithic 3D ICs. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53542

10. Wang, Fengtao. Optical interconnects on printed circuit boards.

Degree: PhD, Electrical and Computer Engineering, 2010, Georgia Tech

 The ever-increasing need for higher bandwidth and density is one of the motivations for extensive research on planar optoelectronic structures on printed circuit board (PCB)… (more)

Subjects/Keywords: Polymer optical waveguides; Printed circuit boards; Optical interconnects; Micro-mirrors; Printed circuits; Photolithography; Optoelectronic devices; Integrated optics

…Center at Georgia Tech. Furthermore, ultra fine copper line routing substrates are demonstrated… 

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APA (6th Edition):

Wang, F. (2010). Optical interconnects on printed circuit boards. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/37133

Chicago Manual of Style (16th Edition):

Wang, Fengtao. “Optical interconnects on printed circuit boards.” 2010. Doctoral Dissertation, Georgia Tech. Accessed December 11, 2019. http://hdl.handle.net/1853/37133.

MLA Handbook (7th Edition):

Wang, Fengtao. “Optical interconnects on printed circuit boards.” 2010. Web. 11 Dec 2019.

Vancouver:

Wang F. Optical interconnects on printed circuit boards. [Internet] [Doctoral dissertation]. Georgia Tech; 2010. [cited 2019 Dec 11]. Available from: http://hdl.handle.net/1853/37133.

Council of Science Editors:

Wang F. Optical interconnects on printed circuit boards. [Doctoral Dissertation]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/37133

11. Samal, Sandeep Kumar. Design challenges and CAD solutions for low power and reliable monolithic 3D ICs.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 The major challenges in low power and reliable monolithic 3D IC design are studied and quantified. New CAD solutions are developed to address these challenges… (more)

Subjects/Keywords: Monolithic; 3D ICs; CAD; Thermal optimization; 3D power delivery; Inter-tier variation; Power-performance-cost analysis

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APA (6th Edition):

Samal, S. K. (2017). Design challenges and CAD solutions for low power and reliable monolithic 3D ICs. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58245

Chicago Manual of Style (16th Edition):

Samal, Sandeep Kumar. “Design challenges and CAD solutions for low power and reliable monolithic 3D ICs.” 2017. Doctoral Dissertation, Georgia Tech. Accessed December 11, 2019. http://hdl.handle.net/1853/58245.

MLA Handbook (7th Edition):

Samal, Sandeep Kumar. “Design challenges and CAD solutions for low power and reliable monolithic 3D ICs.” 2017. Web. 11 Dec 2019.

Vancouver:

Samal SK. Design challenges and CAD solutions for low power and reliable monolithic 3D ICs. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Dec 11]. Available from: http://hdl.handle.net/1853/58245.

Council of Science Editors:

Samal SK. Design challenges and CAD solutions for low power and reliable monolithic 3D ICs. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58245


Georgia Tech

12. Chen, Wei. Design, fabrication, and reliability study of second-level compliant microelectronic interconnects.

Degree: PhD, Mechanical Engineering, 2015, Georgia Tech

 Free-standing off-chip interconnects have high in-plane and out-of-plane compliance and are being pursued in academia and industry to reduce die stresses and to enhance interconnect… (more)

Subjects/Keywords: Compliant interconnect; Microelectronic packaging; Packaging reliability

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APA (6th Edition):

Chen, W. (2015). Design, fabrication, and reliability study of second-level compliant microelectronic interconnects. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55550

Chicago Manual of Style (16th Edition):

Chen, Wei. “Design, fabrication, and reliability study of second-level compliant microelectronic interconnects.” 2015. Doctoral Dissertation, Georgia Tech. Accessed December 11, 2019. http://hdl.handle.net/1853/55550.

MLA Handbook (7th Edition):

Chen, Wei. “Design, fabrication, and reliability study of second-level compliant microelectronic interconnects.” 2015. Web. 11 Dec 2019.

Vancouver:

Chen W. Design, fabrication, and reliability study of second-level compliant microelectronic interconnects. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Dec 11]. Available from: http://hdl.handle.net/1853/55550.

Council of Science Editors:

Chen W. Design, fabrication, and reliability study of second-level compliant microelectronic interconnects. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/55550


Georgia Tech

13. Alam, Mahbub. Nanoscale optical devices based on phase coherent electron transport.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The optical interaction of phase coherent electron in an open system has been investigated. It has been found that after optical excitation electron wavefunction evolves… (more)

Subjects/Keywords: Opto coherent electronics; Quantum interference; Bloch scale illumination

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APA (6th Edition):

Alam, M. (2016). Nanoscale optical devices based on phase coherent electron transport. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59119

Chicago Manual of Style (16th Edition):

Alam, Mahbub. “Nanoscale optical devices based on phase coherent electron transport.” 2016. Doctoral Dissertation, Georgia Tech. Accessed December 11, 2019. http://hdl.handle.net/1853/59119.

MLA Handbook (7th Edition):

Alam, Mahbub. “Nanoscale optical devices based on phase coherent electron transport.” 2016. Web. 11 Dec 2019.

Vancouver:

Alam M. Nanoscale optical devices based on phase coherent electron transport. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Dec 11]. Available from: http://hdl.handle.net/1853/59119.

Council of Science Editors:

Alam M. Nanoscale optical devices based on phase coherent electron transport. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/59119

.