Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies.
Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech
Modeling approaches are developed to optimize emerging on-chip and off-chip electrical interconnect technologies and benchmark them against conventional technologies. While transistor scaling results in an improvement in power and performance, interconnect scaling results in a degradation in performance and electromigration reliability. Although graphene potentially has superior transport properties compared to copper, it is shown that several technology improvements like smooth edges, edge doping, good contacts, and good substrates are essential for graphene to outperform copper in high performance on-chip interconnect applications. However, for low power applications, the low capacitance of graphene results in 31% energy savings compared to copper interconnects, for a fixed performance. Further, for characterization of the circuit parameters of multi-layer graphene, multi-conductor transmission line models that account for an alignment margin and finite width of the contact are developed.
Although it is essential to push for an improvement in chip performance by improving on-chip interconnects, devices, and architectures, the system level performance can get severely limited by the bandwidth of off-chip interconnects. As a result, three dimensional integration and airgap interconnects are studied as potential replacements for conventional off-chip interconnects. The key parameters that limit the performance of a 3D IC are identified as the Through Silicon Via (TSV) capacitance, driver resistance, and on-chip wire resistance on the driver side. Further, the impact of on-chip wires on the performance of 3D ICs is shown to be more pronounced at advanced technology nodes and when the TSV diameter is scaled down. Airgap interconnects are shown to improve aggregate bandwidth by 3x to 5x for backplane and Printed Circuit Board (PCB) links, and by 2x for silicon interposer links, at comparable energy consumption.
Advisors/Committee Members: Naaemi, Azad J. (advisor), Bakir, Muhannad S. (advisor), Mukhopadhyay, Saibal (committee member), Kohl, Paul A. (committee member), Davis, Jeffrey A. (committee member).
Subjects/Keywords: Interconnect modeling; Graphene nanoribbons; Through silicon via, airgap interconnects
to Zotero / EndNote / Reference
APA (6th Edition):
Kumar, V. (2014). Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54280
Chicago Manual of Style (16th Edition):
Kumar, Vachan. “Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 23, 2019.
MLA Handbook (7th Edition):
Kumar, Vachan. “Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies.” 2014. Web. 23 Feb 2019.
Kumar V. Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Feb 23].
Available from: http://hdl.handle.net/1853/54280.
Council of Science Editors:
Kumar V. Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/54280