Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · date | New search

You searched for +publisher:"Georgia Tech" +contributor:("Mukhopadhyay, Saibal"). Showing records 1 – 30 of 88 total matches.

[1] [2] [3]

Search Limiters

Last 2 Years | English Only

Degrees

Levels

▼ Search Limiters


Georgia Tech

1. Rao, Karthik. Coordinated management of the processor and memory for optimizing energy efficiency.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 Energy efficiency is a key design goal for future computing systems. With diverse components interacting with each other on the System-on-Chip (SoC), dynamically managing performance,… (more)

Subjects/Keywords: Feedback control; Optimization; Adaptive control; 3D stacked architecture; Thermal management; Energy efficiency; Android

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rao, K. (2018). Coordinated management of the processor and memory for optimizing energy efficiency. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60234

Chicago Manual of Style (16th Edition):

Rao, Karthik. “Coordinated management of the processor and memory for optimizing energy efficiency.” 2018. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/60234.

MLA Handbook (7th Edition):

Rao, Karthik. “Coordinated management of the processor and memory for optimizing energy efficiency.” 2018. Web. 21 Feb 2019.

Vancouver:

Rao K. Coordinated management of the processor and memory for optimizing energy efficiency. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/60234.

Council of Science Editors:

Rao K. Coordinated management of the processor and memory for optimizing energy efficiency. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60234


Georgia Tech

2. Pardue, Colin Andrew. Wireless power transfer using integrated and emerging technologies.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 To support the next generation of compact low power devices, a wireless power transfer solution needs to have an improved combination of receiver coil area… (more)

Subjects/Keywords: Wireless power transfer; Internet of things; Integrated inductor; Packaging; Rf near field coupling; Power integrity

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pardue, C. A. (2018). Wireless power transfer using integrated and emerging technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60216

Chicago Manual of Style (16th Edition):

Pardue, Colin Andrew. “Wireless power transfer using integrated and emerging technologies.” 2018. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/60216.

MLA Handbook (7th Edition):

Pardue, Colin Andrew. “Wireless power transfer using integrated and emerging technologies.” 2018. Web. 21 Feb 2019.

Vancouver:

Pardue CA. Wireless power transfer using integrated and emerging technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/60216.

Council of Science Editors:

Pardue CA. Wireless power transfer using integrated and emerging technologies. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60216


Georgia Tech

3. Kim, Sihwan. Low power mixed signal system design environment using floating-gate FPAAs.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The objective of this research is to create a low-power mixed-signal system design environment using FG FPAAs. To achieve this, my research focused on implementing… (more)

Subjects/Keywords: Floating-gate; FG; Field programmable analog array (FPAA)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, S. (2018). Low power mixed signal system design environment using floating-gate FPAAs. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59923

Chicago Manual of Style (16th Edition):

Kim, Sihwan. “Low power mixed signal system design environment using floating-gate FPAAs.” 2018. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/59923.

MLA Handbook (7th Edition):

Kim, Sihwan. “Low power mixed signal system design environment using floating-gate FPAAs.” 2018. Web. 21 Feb 2019.

Vancouver:

Kim S. Low power mixed signal system design environment using floating-gate FPAAs. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/59923.

Council of Science Editors:

Kim S. Low power mixed signal system design environment using floating-gate FPAAs. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59923


Georgia Tech

4. Chen, Xinwei. Performance and power management for multi-core processors.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 This dissertation addresses the problem of power and performance management for various computing systems, from single voltage island multicore processors to power constrained extreme scale… (more)

Subjects/Keywords: Performance and power management; Multi-core processors; Cloud systems; Power efficiency optimization; Feedback control

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, X. (2018). Performance and power management for multi-core processors. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59898

Chicago Manual of Style (16th Edition):

Chen, Xinwei. “Performance and power management for multi-core processors.” 2018. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/59898.

MLA Handbook (7th Edition):

Chen, Xinwei. “Performance and power management for multi-core processors.” 2018. Web. 21 Feb 2019.

Vancouver:

Chen X. Performance and power management for multi-core processors. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/59898.

Council of Science Editors:

Chen X. Performance and power management for multi-core processors. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59898


Georgia Tech

5. Xiao, He. A Multi-physics approach to the co-design of 3D multi-core processors.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The three-dimensional integrated circuit (3D IC) is a promising solution for processors in the post-Moore era. The 3D integration stacks multiple dies vertically in a… (more)

Subjects/Keywords: Performance; Energy efficiency; 3D IC; Multi-core systems; Multi-physics analysis; Microarchitecture co-design

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xiao, H. (2018). A Multi-physics approach to the co-design of 3D multi-core processors. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59810

Chicago Manual of Style (16th Edition):

Xiao, He. “A Multi-physics approach to the co-design of 3D multi-core processors.” 2018. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/59810.

MLA Handbook (7th Edition):

Xiao, He. “A Multi-physics approach to the co-design of 3D multi-core processors.” 2018. Web. 21 Feb 2019.

Vancouver:

Xiao H. A Multi-physics approach to the co-design of 3D multi-core processors. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/59810.

Council of Science Editors:

Xiao H. A Multi-physics approach to the co-design of 3D multi-core processors. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59810


Georgia Tech

6. Kar, Monodeep. Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 The energy-efficiency and security needs in computing systems, ranging from high performance processors to low-power devices are steadily increasing. State-of-the-art digital systems use dedicated encryption… (more)

Subjects/Keywords: Side channel attack; Power attack; Differential power analysis; DPA; Correlation power analysis; CPA; Differential electromagnetic analysis; DEMA; Test vector leakage assessment; TVLA; Integrated voltage regulators; IVR; Voltage regulation; Haswell; FIVR; Security guard extension; SGX; DC-DC converters; Buck regulators; IoT; Countermeasures; Advanced encryption standard; AES; AES-NI; Randomization; Security; Masking countermeasure; Dual rail logic

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kar, M. (2017). Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59182

Chicago Manual of Style (16th Edition):

Kar, Monodeep. “Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/59182.

MLA Handbook (7th Edition):

Kar, Monodeep. “Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines.” 2017. Web. 21 Feb 2019.

Vancouver:

Kar M. Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/59182.

Council of Science Editors:

Kar M. Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59182


Georgia Tech

7. Zhang, Yang. Thermal and power delivery network modeling for emerging microelectronic integration platforms.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 In this dissertation, thermal management and power delivery challenges in 2.5-D and 3-D integration are presented. To address the thermal coupling issues in heterogeneous 3-D… (more)

Subjects/Keywords: 3D-IC, 2.5-D IC, Thermal, Power delivery, Signaling; 2.5-D IC; Thermal; Power delivery; Signaling

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhang, Y. (2017). Thermal and power delivery network modeling for emerging microelectronic integration platforms. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59199

Chicago Manual of Style (16th Edition):

Zhang, Yang. “Thermal and power delivery network modeling for emerging microelectronic integration platforms.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/59199.

MLA Handbook (7th Edition):

Zhang, Yang. “Thermal and power delivery network modeling for emerging microelectronic integration platforms.” 2017. Web. 21 Feb 2019.

Vancouver:

Zhang Y. Thermal and power delivery network modeling for emerging microelectronic integration platforms. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/59199.

Council of Science Editors:

Zhang Y. Thermal and power delivery network modeling for emerging microelectronic integration platforms. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59199


Georgia Tech

8. Kim, Duckhwan. NEUROCUBE: ENERGY-EFFICIENT PROGRAMMABLE DIGITAL DEEP LEARNING ACCELERATOR BASED ON PROCESSOR IN MEMORY PLATFORM.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 Deep learning, machine learning algorithm based on artificial neural network, shows great success in numerous pattern recognition problems, such as image recognition or speech recognition.… (more)

Subjects/Keywords: deep learning; deep learning accelerator; processor in memory; near memory process

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, D. (2017). NEUROCUBE: ENERGY-EFFICIENT PROGRAMMABLE DIGITAL DEEP LEARNING ACCELERATOR BASED ON PROCESSOR IN MEMORY PLATFORM. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60660

Chicago Manual of Style (16th Edition):

Kim, Duckhwan. “NEUROCUBE: ENERGY-EFFICIENT PROGRAMMABLE DIGITAL DEEP LEARNING ACCELERATOR BASED ON PROCESSOR IN MEMORY PLATFORM.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/60660.

MLA Handbook (7th Edition):

Kim, Duckhwan. “NEUROCUBE: ENERGY-EFFICIENT PROGRAMMABLE DIGITAL DEEP LEARNING ACCELERATOR BASED ON PROCESSOR IN MEMORY PLATFORM.” 2017. Web. 21 Feb 2019.

Vancouver:

Kim D. NEUROCUBE: ENERGY-EFFICIENT PROGRAMMABLE DIGITAL DEEP LEARNING ACCELERATOR BASED ON PROCESSOR IN MEMORY PLATFORM. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/60660.

Council of Science Editors:

Kim D. NEUROCUBE: ENERGY-EFFICIENT PROGRAMMABLE DIGITAL DEEP LEARNING ACCELERATOR BASED ON PROCESSOR IN MEMORY PLATFORM. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/60660

9. Deyati, Sabyasachi. Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 With the advent of SOCs and SOPs, more functionalities are integrated into an IC or package. Higher level of integration has made testing, validation of… (more)

Subjects/Keywords: Adaptive testing; Analog/RF testing; Mixed signal validation; Machine learning; Beam forming MIMO systems; Trojan detection; Analog physically unclonable function

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Deyati, S. (2017). Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58757

Chicago Manual of Style (16th Edition):

Deyati, Sabyasachi. “Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/58757.

MLA Handbook (7th Edition):

Deyati, Sabyasachi. “Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems.” 2017. Web. 21 Feb 2019.

Vancouver:

Deyati S. Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/58757.

Council of Science Editors:

Deyati S. Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58757

10. Blanco, Andres Arturo. Fast-waking and low-voltage thermoelectric and photovoltaic CMOS chargers for energy-harvesting wireless microsensors.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 The small size of wireless microsystems allows them to be deployed within larger systems to sense and monitor various indicators throughout many applications. However, their… (more)

Subjects/Keywords: Energy harvesters; Low power circuits; Low voltage starters

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Blanco, A. A. (2017). Fast-waking and low-voltage thermoelectric and photovoltaic CMOS chargers for energy-harvesting wireless microsensors. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58707

Chicago Manual of Style (16th Edition):

Blanco, Andres Arturo. “Fast-waking and low-voltage thermoelectric and photovoltaic CMOS chargers for energy-harvesting wireless microsensors.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/58707.

MLA Handbook (7th Edition):

Blanco, Andres Arturo. “Fast-waking and low-voltage thermoelectric and photovoltaic CMOS chargers for energy-harvesting wireless microsensors.” 2017. Web. 21 Feb 2019.

Vancouver:

Blanco AA. Fast-waking and low-voltage thermoelectric and photovoltaic CMOS chargers for energy-harvesting wireless microsensors. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/58707.

Council of Science Editors:

Blanco AA. Fast-waking and low-voltage thermoelectric and photovoltaic CMOS chargers for energy-harvesting wireless microsensors. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58707

11. Ku, Bon Woong Woong. Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node.

Degree: MS, Electrical and Computer Engineering, 2017, Georgia Tech

 The nature of device scaling in the 7nm era is changing from the traditional scheme driven by Moore’s law because of the physical and economic… (more)

Subjects/Keywords: Gate-level; Monolithic 3D IC; PPC tradeoff; 7nm technology node

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ku, B. W. W. (2017). Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58257

Chicago Manual of Style (16th Edition):

Ku, Bon Woong Woong. “Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node.” 2017. Masters Thesis, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/58257.

MLA Handbook (7th Edition):

Ku, Bon Woong Woong. “Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node.” 2017. Web. 21 Feb 2019.

Vancouver:

Ku BWW. Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/58257.

Council of Science Editors:

Ku BWW. Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58257

12. Nair, Prashant J. Architectural techniques to enable reliable and scalable memory systems.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 High capacity and scalable memory systems play a vital role in enabling our desk- tops, smartphones, and pervasive technologies like Internet of Things (IoT). Unfortunately,… (more)

Subjects/Keywords: Memory systems; Reliability; Moore's law; Computer architecture; Scaling

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nair, P. J. (2017). Architectural techniques to enable reliable and scalable memory systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58309

Chicago Manual of Style (16th Edition):

Nair, Prashant J. “Architectural techniques to enable reliable and scalable memory systems.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/58309.

MLA Handbook (7th Edition):

Nair, Prashant J. “Architectural techniques to enable reliable and scalable memory systems.” 2017. Web. 21 Feb 2019.

Vancouver:

Nair PJ. Architectural techniques to enable reliable and scalable memory systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/58309.

Council of Science Editors:

Nair PJ. Architectural techniques to enable reliable and scalable memory systems. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58309

13. Kung, Jae Ha. Energy-efficient digital hardware platform for learning complex systems.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 System learning is the most fundamental research area in engineering domain. It is a modeling method to map external inputs to the corresponding outputs with/without… (more)

Subjects/Keywords: Energy-efficiency; Digital accelerator

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kung, J. H. (2017). Energy-efficient digital hardware platform for learning complex systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58316

Chicago Manual of Style (16th Edition):

Kung, Jae Ha. “Energy-efficient digital hardware platform for learning complex systems.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/58316.

MLA Handbook (7th Edition):

Kung, Jae Ha. “Energy-efficient digital hardware platform for learning complex systems.” 2017. Web. 21 Feb 2019.

Vancouver:

Kung JH. Energy-efficient digital hardware platform for learning complex systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/58316.

Council of Science Editors:

Kung JH. Energy-efficient digital hardware platform for learning complex systems. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58316

14. Samal, Sandeep Kumar. Design challenges and CAD solutions for low power and reliable monolithic 3D ICs.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 The major challenges in low power and reliable monolithic 3D IC design are studied and quantified. New CAD solutions are developed to address these challenges… (more)

Subjects/Keywords: Monolithic; 3D ICs; CAD; Thermal optimization; 3D power delivery; Inter-tier variation; Power-performance-cost analysis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Samal, S. K. (2017). Design challenges and CAD solutions for low power and reliable monolithic 3D ICs. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58245

Chicago Manual of Style (16th Edition):

Samal, Sandeep Kumar. “Design challenges and CAD solutions for low power and reliable monolithic 3D ICs.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/58245.

MLA Handbook (7th Edition):

Samal, Sandeep Kumar. “Design challenges and CAD solutions for low power and reliable monolithic 3D ICs.” 2017. Web. 21 Feb 2019.

Vancouver:

Samal SK. Design challenges and CAD solutions for low power and reliable monolithic 3D ICs. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/58245.

Council of Science Editors:

Samal SK. Design challenges and CAD solutions for low power and reliable monolithic 3D ICs. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58245


Georgia Tech

15. Peng, Yarui. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 As one of more-than-Moore technologies, 3D ICs enable next-generation systems with much higher device density without needs for technology scaling. However, designing reliable 3D IC… (more)

Subjects/Keywords: 3D IC; CAD; Methodology; Reliable; Power integrity; Signal integrity

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Peng, Y. (2016). CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56330

Chicago Manual of Style (16th Edition):

Peng, Yarui. “CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/56330.

MLA Handbook (7th Edition):

Peng, Yarui. “CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.” 2016. Web. 21 Feb 2019.

Vancouver:

Peng Y. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/56330.

Council of Science Editors:

Peng Y. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56330


Georgia Tech

16. Wang, Cheng-Yin. Organic field-effect transistors on novel renewable substrates.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 With the increasing awareness of environmental impact from electronic waste and increasing demand for flexible electronic devices, novel substrates with both biodegradability and flexibility have… (more)

Subjects/Keywords: Organic field-effect transistors; Novel renewable substrates; Top-gate geometry; CNC; Reliability; Stability; Nanolaminate; Flexible; Paper

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, C. (2016). Organic field-effect transistors on novel renewable substrates. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59137

Chicago Manual of Style (16th Edition):

Wang, Cheng-Yin. “Organic field-effect transistors on novel renewable substrates.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/59137.

MLA Handbook (7th Edition):

Wang, Cheng-Yin. “Organic field-effect transistors on novel renewable substrates.” 2016. Web. 21 Feb 2019.

Vancouver:

Wang C. Organic field-effect transistors on novel renewable substrates. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/59137.

Council of Science Editors:

Wang C. Organic field-effect transistors on novel renewable substrates. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/59137

17. Chang, Sou-Chi. Beyond-CMOS spintronic logic and ferroelectric memory.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The objective of this thesis is to explore spintronic logic and ferroelectric memory as potential solutions to beyond complementary metal-oxide-semiconductor (CMOS) technologies, since devices based… (more)

Subjects/Keywords: Spintronic logic; Ferroelectric memory

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, S. (2016). Beyond-CMOS spintronic logic and ferroelectric memory. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56278

Chicago Manual of Style (16th Edition):

Chang, Sou-Chi. “Beyond-CMOS spintronic logic and ferroelectric memory.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/56278.

MLA Handbook (7th Edition):

Chang, Sou-Chi. “Beyond-CMOS spintronic logic and ferroelectric memory.” 2016. Web. 21 Feb 2019.

Vancouver:

Chang S. Beyond-CMOS spintronic logic and ferroelectric memory. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/56278.

Council of Science Editors:

Chang S. Beyond-CMOS spintronic logic and ferroelectric memory. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56278


Georgia Tech

18. Hassan, Syed Minhaj. Exploiting on-chip memory concurrency in 3d manycore architectures.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The objective of this thesis is to optimize the uncore of 3D many-core architectures. More specifically, we note that technology trends point to large increases… (more)

Subjects/Keywords: 3D memory systems; Network-on-chip; 3D system thermal analysis; Memory-level parallelism; DRAM

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hassan, S. M. (2016). Exploiting on-chip memory concurrency in 3d manycore architectures. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56251

Chicago Manual of Style (16th Edition):

Hassan, Syed Minhaj. “Exploiting on-chip memory concurrency in 3d manycore architectures.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/56251.

MLA Handbook (7th Edition):

Hassan, Syed Minhaj. “Exploiting on-chip memory concurrency in 3d manycore architectures.” 2016. Web. 21 Feb 2019.

Vancouver:

Hassan SM. Exploiting on-chip memory concurrency in 3d manycore architectures. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/56251.

Council of Science Editors:

Hassan SM. Exploiting on-chip memory concurrency in 3d manycore architectures. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56251

19. Ahmed, Khondker Zakir. EFFICIENT POWER MANAGEMENT CIRCUITS FOR ENERGY HARVESTING APPLICATIONS.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 Low power IoT devices are growing in numbers and by 2020 there will be more than 25 Billion of those in areas such as wearables,… (more)

Subjects/Keywords: boost regulator; pulse frequency modulation; PFM; buck regulator; single inductor multiple output; SIMO; energy harvesting; TEG; photovoltaic cell; low power circuits; internet of things; wireless sensor network; WSN; IOT

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ahmed, K. Z. (2016). EFFICIENT POWER MANAGEMENT CIRCUITS FOR ENERGY HARVESTING APPLICATIONS. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56236

Chicago Manual of Style (16th Edition):

Ahmed, Khondker Zakir. “EFFICIENT POWER MANAGEMENT CIRCUITS FOR ENERGY HARVESTING APPLICATIONS.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/56236.

MLA Handbook (7th Edition):

Ahmed, Khondker Zakir. “EFFICIENT POWER MANAGEMENT CIRCUITS FOR ENERGY HARVESTING APPLICATIONS.” 2016. Web. 21 Feb 2019.

Vancouver:

Ahmed KZ. EFFICIENT POWER MANAGEMENT CIRCUITS FOR ENERGY HARVESTING APPLICATIONS. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/56236.

Council of Science Editors:

Ahmed KZ. EFFICIENT POWER MANAGEMENT CIRCUITS FOR ENERGY HARVESTING APPLICATIONS. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56236


Georgia Tech

20. Natarajan, Jayaram. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 One of the challenges faced today in the design of microprocessors is to obtain power, performance scalability and reliability at the same time with technology… (more)

Subjects/Keywords: Microprocessor; Low power; Process variation; Timing variation tolerant; Timing margins; Better than worse-case design; Error resilient pipeline; Reliability

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Natarajan, J. (2016). Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55577

Chicago Manual of Style (16th Edition):

Natarajan, Jayaram. “Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/55577.

MLA Handbook (7th Edition):

Natarajan, Jayaram. “Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.” 2016. Web. 21 Feb 2019.

Vancouver:

Natarajan J. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/55577.

Council of Science Editors:

Natarajan J. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55577


Georgia Tech

21. Chintaluri, Ashwin K. Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays.

Degree: MS, Electrical and Computer Engineering, 2016, Georgia Tech

 Spin transfer torque magnetic random access memory (STT-MRAM) is a competitive, future memory technology that has gained immense interest in recent years due to its… (more)

Subjects/Keywords: STT-MRAM; Variation; Faults

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chintaluri, A. K. (2016). Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55060

Chicago Manual of Style (16th Edition):

Chintaluri, Ashwin K. “Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays.” 2016. Masters Thesis, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/55060.

MLA Handbook (7th Edition):

Chintaluri, Ashwin K. “Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays.” 2016. Web. 21 Feb 2019.

Vancouver:

Chintaluri AK. Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/55060.

Council of Science Editors:

Chintaluri AK. Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55060


Georgia Tech

22. Wan, Zhimin. Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling.

Degree: PhD, Mechanical Engineering, 2016, Georgia Tech

 Microfluidic convection cooling is a promising technique for future high power microprocessors, radio-frequency (RF) transceivers, solid-state lasers, and light emitting diodes (LED). Three-dimensional (3D) stacking… (more)

Subjects/Keywords: Microfluidic cooling; Pin fin; 3D ICs; Microfabrication; Flow boiling

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wan, Z. (2016). Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55480

Chicago Manual of Style (16th Edition):

Wan, Zhimin. “Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/55480.

MLA Handbook (7th Edition):

Wan, Zhimin. “Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling.” 2016. Web. 21 Feb 2019.

Vancouver:

Wan Z. Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/55480.

Council of Science Editors:

Wan Z. Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55480

23. Samal, Kruttidipta. FPGA acceleration of CNN training.

Degree: MS, Electrical and Computer Engineering, 2015, Georgia Tech

 This thesis presents the results of an architectural study on the design of FPGA- based architectures for convolutional neural networks (CNNs). We have analyzed the… (more)

Subjects/Keywords: CNN; FPGA; Deep learning

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Samal, K. (2015). FPGA acceleration of CNN training. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54467

Chicago Manual of Style (16th Edition):

Samal, Kruttidipta. “FPGA acceleration of CNN training.” 2015. Masters Thesis, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/54467.

MLA Handbook (7th Edition):

Samal, Kruttidipta. “FPGA acceleration of CNN training.” 2015. Web. 21 Feb 2019.

Vancouver:

Samal K. FPGA acceleration of CNN training. [Internet] [Masters thesis]. Georgia Tech; 2015. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/54467.

Council of Science Editors:

Samal K. FPGA acceleration of CNN training. [Masters Thesis]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/54467

24. Subramanian, Ashwin Srinath. Enhancing microprocessor power efficiency through clock-data compensation.

Degree: MS, Electrical and Computer Engineering, 2015, Georgia Tech

 The Smartphone revolution and the Internet of Things (IoTs) have triggered rapid advances in complex system-on-chips (SoCs) that increasing provide more functionality within a tight… (more)

Subjects/Keywords: Power management; Adaptive Clocking; Clock-data compensation; Power efficiency

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Subramanian, A. S. (2015). Enhancing microprocessor power efficiency through clock-data compensation. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54471

Chicago Manual of Style (16th Edition):

Subramanian, Ashwin Srinath. “Enhancing microprocessor power efficiency through clock-data compensation.” 2015. Masters Thesis, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/54471.

MLA Handbook (7th Edition):

Subramanian, Ashwin Srinath. “Enhancing microprocessor power efficiency through clock-data compensation.” 2015. Web. 21 Feb 2019.

Vancouver:

Subramanian AS. Enhancing microprocessor power efficiency through clock-data compensation. [Internet] [Masters thesis]. Georgia Tech; 2015. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/54471.

Council of Science Editors:

Subramanian AS. Enhancing microprocessor power efficiency through clock-data compensation. [Masters Thesis]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/54471


Georgia Tech

25. Carlo, Sergio. Load-Aware Power Conversion and Integration for Heterogeneous Systems.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 In this thesis we develop a holistic co-design approach to optimize the conversion systems in order to perform relevant trade-offs taking into account system-level converter,… (more)

Subjects/Keywords: Power conversion 3D single inductor multiple output SIMO control design power management

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Carlo, S. (2015). Load-Aware Power Conversion and Integration for Heterogeneous Systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56182

Chicago Manual of Style (16th Edition):

Carlo, Sergio. “Load-Aware Power Conversion and Integration for Heterogeneous Systems.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/56182.

MLA Handbook (7th Edition):

Carlo, Sergio. “Load-Aware Power Conversion and Integration for Heterogeneous Systems.” 2015. Web. 21 Feb 2019.

Vancouver:

Carlo S. Load-Aware Power Conversion and Integration for Heterogeneous Systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/56182.

Council of Science Editors:

Carlo S. Load-Aware Power Conversion and Integration for Heterogeneous Systems. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56182


Georgia Tech

26. Song, Taigon. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The objective of this research is to study and develop computer-aided-design (CAD) methodologies for reliability in chip-package co-designed three-dimensional integrated circuit (3D IC) systems. 3D… (more)

Subjects/Keywords: 3D IC; Design Methodologies

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Song, T. (2015). CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56188

Chicago Manual of Style (16th Edition):

Song, Taigon. “CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/56188.

MLA Handbook (7th Edition):

Song, Taigon. “CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.” 2015. Web. 21 Feb 2019.

Vancouver:

Song T. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/56188.

Council of Science Editors:

Song T. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56188

27. Song, William J. Managing lifetime reliability, performance, and power tradeoffs in multicore microarchitectures.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The objective of this research is to characterize and manage lifetime reliability, microarchitectural performance, and power tradeoffs in multicore processors. This dissertation is comprised of… (more)

Subjects/Keywords: Computer architecture; Lifetime reliability; Modeling; Performance; Energy efficiency; Heterogeneous processor

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Song, W. J. (2015). Managing lifetime reliability, performance, and power tradeoffs in multicore microarchitectures. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54399

Chicago Manual of Style (16th Edition):

Song, William J. “Managing lifetime reliability, performance, and power tradeoffs in multicore microarchitectures.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/54399.

MLA Handbook (7th Edition):

Song, William J. “Managing lifetime reliability, performance, and power tradeoffs in multicore microarchitectures.” 2015. Web. 21 Feb 2019.

Vancouver:

Song WJ. Managing lifetime reliability, performance, and power tradeoffs in multicore microarchitectures. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/54399.

Council of Science Editors:

Song WJ. Managing lifetime reliability, performance, and power tradeoffs in multicore microarchitectures. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/54399

28. Trivedi, Amit R. Ultra low power non-Boolean computing with tunneling field-effect-transistors.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 This dissertation explores cohesive design methodologies integrating emerging computing technologies/paradigms and computing applications. At first the limitations of conventional technology CMOS-based digital designs are mitigated… (more)

Subjects/Keywords: Tunnel FET; Non Boolean computing; Ultra low power computing; Power gating; Process induced variability; Associative processing; Cellular neural network; Image processing; Associative memory; Oxygen vacancy; Three dimensional integration

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Trivedi, A. R. (2015). Ultra low power non-Boolean computing with tunneling field-effect-transistors. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56178

Chicago Manual of Style (16th Edition):

Trivedi, Amit R. “Ultra low power non-Boolean computing with tunneling field-effect-transistors.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/56178.

MLA Handbook (7th Edition):

Trivedi, Amit R. “Ultra low power non-Boolean computing with tunneling field-effect-transistors.” 2015. Web. 21 Feb 2019.

Vancouver:

Trivedi AR. Ultra low power non-Boolean computing with tunneling field-effect-transistors. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/56178.

Council of Science Editors:

Trivedi AR. Ultra low power non-Boolean computing with tunneling field-effect-transistors. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56178


Georgia Tech

29. Yueh, Wen. Modeling, characterization, and control of the electrical-thermal interactions in advanced packages.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The multi-chip integration in an advanced packaging has made the multi-physics interactions increasingly important. The objective of this research is to address the thermal coupling… (more)

Subjects/Keywords: Cooling; VLSI; SRAM; EDRAM; 3D IC; Packaging

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yueh, W. (2015). Modeling, characterization, and control of the electrical-thermal interactions in advanced packages. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56171

Chicago Manual of Style (16th Edition):

Yueh, Wen. “Modeling, characterization, and control of the electrical-thermal interactions in advanced packages.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/56171.

MLA Handbook (7th Edition):

Yueh, Wen. “Modeling, characterization, and control of the electrical-thermal interactions in advanced packages.” 2015. Web. 21 Feb 2019.

Vancouver:

Yueh W. Modeling, characterization, and control of the electrical-thermal interactions in advanced packages. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/56171.

Council of Science Editors:

Yueh W. Modeling, characterization, and control of the electrical-thermal interactions in advanced packages. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56171

30. Alexandrov, Borislav P. Design methodology for thermal management using embedded thermoelectric devices.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The main objectives of this dissertation is to investigate the prospects of embedded thermoelectric devices integrated in a chip package and to develop a design… (more)

Subjects/Keywords: VLSI; Thermal management; Thermoelectric cooling; Energy harvesting; CMOS control circuits; Temperature control

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Alexandrov, B. P. (2015). Design methodology for thermal management using embedded thermoelectric devices. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54352

Chicago Manual of Style (16th Edition):

Alexandrov, Borislav P. “Design methodology for thermal management using embedded thermoelectric devices.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/54352.

MLA Handbook (7th Edition):

Alexandrov, Borislav P. “Design methodology for thermal management using embedded thermoelectric devices.” 2015. Web. 21 Feb 2019.

Vancouver:

Alexandrov BP. Design methodology for thermal management using embedded thermoelectric devices. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/54352.

Council of Science Editors:

Alexandrov BP. Design methodology for thermal management using embedded thermoelectric devices. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/54352

[1] [2] [3]

.