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Dates: 2010 – 2014

You searched for +publisher:"Georgia Tech" +contributor:("Mukhopadhyay, Saibal"). Showing records 1 – 30 of 44 total matches.

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Georgia Tech

1. VanDerheyden, Andrew Louis. Characterization of thermal coupling in chip multiprocessors.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 For semiconductor processors temperature increases leakage current, which in turn in- creases the temperature of the processor. This increase in heat is seen by other… (more)

Subjects/Keywords: Thermal management; Thermal characterization; Thermal coupling; High performance processors; Thermal analysis

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APA (6th Edition):

VanDerheyden, A. L. (2014). Characterization of thermal coupling in chip multiprocessors. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51892

Chicago Manual of Style (16th Edition):

VanDerheyden, Andrew Louis. “Characterization of thermal coupling in chip multiprocessors.” 2014. Masters Thesis, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/51892.

MLA Handbook (7th Edition):

VanDerheyden, Andrew Louis. “Characterization of thermal coupling in chip multiprocessors.” 2014. Web. 19 Feb 2019.

Vancouver:

VanDerheyden AL. Characterization of thermal coupling in chip multiprocessors. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/51892.

Council of Science Editors:

VanDerheyden AL. Characterization of thermal coupling in chip multiprocessors. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51892

2. Bonhomme, Phillip. Circuit modeling of spintronic devices: a SPICE implementation.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 Every engineer that has worked on designing an integrated circuit has to leverage an under- standing of device physics. Understanding device physics is essential when… (more)

Subjects/Keywords: SPICE; Spintronics; Circuit simulation; Magnetization dynamics; Spintronics; Mathematical models

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APA (6th Edition):

Bonhomme, P. (2014). Circuit modeling of spintronic devices: a SPICE implementation. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51818

Chicago Manual of Style (16th Edition):

Bonhomme, Phillip. “Circuit modeling of spintronic devices: a SPICE implementation.” 2014. Masters Thesis, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/51818.

MLA Handbook (7th Edition):

Bonhomme, Phillip. “Circuit modeling of spintronic devices: a SPICE implementation.” 2014. Web. 19 Feb 2019.

Vancouver:

Bonhomme P. Circuit modeling of spintronic devices: a SPICE implementation. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/51818.

Council of Science Editors:

Bonhomme P. Circuit modeling of spintronic devices: a SPICE implementation. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51818


Georgia Tech

3. Wunderlich, Richard Bryan. Floating-gate-programmable and reconfigurable, digital and mixed-signal systems.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 This body of work as whole has the theme of using floating-gates and reconfigurable systems to explore and implement non-traditional computing solutions to difficult problems.… (more)

Subjects/Keywords: Floating-gate; Reconfigurable; Digital; Analog processing; Field programmable gate arrays

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APA (6th Edition):

Wunderlich, R. B. (2014). Floating-gate-programmable and reconfigurable, digital and mixed-signal systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51815

Chicago Manual of Style (16th Edition):

Wunderlich, Richard Bryan. “Floating-gate-programmable and reconfigurable, digital and mixed-signal systems.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/51815.

MLA Handbook (7th Edition):

Wunderlich, Richard Bryan. “Floating-gate-programmable and reconfigurable, digital and mixed-signal systems.” 2014. Web. 19 Feb 2019.

Vancouver:

Wunderlich RB. Floating-gate-programmable and reconfigurable, digital and mixed-signal systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/51815.

Council of Science Editors:

Wunderlich RB. Floating-gate-programmable and reconfigurable, digital and mixed-signal systems. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51815


Georgia Tech

4. Chae, Kwanyeob. Design methodologies for robust low-power digital systems under static and dynamic variations.

Degree: PhD, Electrical and Computer Engineering, 2013, Georgia Tech

 Variability affects the performance and power of a circuit. Along with static variations, dynamic variations, which occur during chip operation, necessitate a safety margin. The… (more)

Subjects/Keywords: Adaptive circuit; Resilient design; Static variation; Dynamic variation; Error prevention

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APA (6th Edition):

Chae, K. (2013). Design methodologies for robust low-power digital systems under static and dynamic variations. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52174

Chicago Manual of Style (16th Edition):

Chae, Kwanyeob. “Design methodologies for robust low-power digital systems under static and dynamic variations.” 2013. Doctoral Dissertation, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/52174.

MLA Handbook (7th Edition):

Chae, Kwanyeob. “Design methodologies for robust low-power digital systems under static and dynamic variations.” 2013. Web. 19 Feb 2019.

Vancouver:

Chae K. Design methodologies for robust low-power digital systems under static and dynamic variations. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/52174.

Council of Science Editors:

Chae K. Design methodologies for robust low-power digital systems under static and dynamic variations. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/52174


Georgia Tech

5. Saha, Prabir K. SiGe BiCMOS RF front-ends for adaptive wideband receivers.

Degree: PhD, Electrical and Computer Engineering, 2013, Georgia Tech

 The pursuit of dense monolithic integration and higher operating speed continues to push the integrated circuit (IC) fabrication technologies to their limits. The increasing process… (more)

Subjects/Keywords: Self-healing; Adaptive; Mixer; Image-rejection; RF; LNA; SPDT

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APA (6th Edition):

Saha, P. K. (2013). SiGe BiCMOS RF front-ends for adaptive wideband receivers. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52184

Chicago Manual of Style (16th Edition):

Saha, Prabir K. “SiGe BiCMOS RF front-ends for adaptive wideband receivers.” 2013. Doctoral Dissertation, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/52184.

MLA Handbook (7th Edition):

Saha, Prabir K. “SiGe BiCMOS RF front-ends for adaptive wideband receivers.” 2013. Web. 19 Feb 2019.

Vancouver:

Saha PK. SiGe BiCMOS RF front-ends for adaptive wideband receivers. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/52184.

Council of Science Editors:

Saha PK. SiGe BiCMOS RF front-ends for adaptive wideband receivers. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/52184


Georgia Tech

6. Onyewuchi, Urenna. Managing environmentally stressed aging assets in electric power utilities.

Degree: PhD, Electrical and Computer Engineering, 2012, Georgia Tech

 A model for optimizing the differential cost between a preventive maintenance program and a traditional run-to-failure program on managing assets under uncertainty is developed to… (more)

Subjects/Keywords: Asset management; Environmental stress; Decision making; Electric utility; Aging infrastructure

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APA (6th Edition):

Onyewuchi, U. (2012). Managing environmentally stressed aging assets in electric power utilities. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53150

Chicago Manual of Style (16th Edition):

Onyewuchi, Urenna. “Managing environmentally stressed aging assets in electric power utilities.” 2012. Doctoral Dissertation, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/53150.

MLA Handbook (7th Edition):

Onyewuchi, Urenna. “Managing environmentally stressed aging assets in electric power utilities.” 2012. Web. 19 Feb 2019.

Vancouver:

Onyewuchi U. Managing environmentally stressed aging assets in electric power utilities. [Internet] [Doctoral dissertation]. Georgia Tech; 2012. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/53150.

Council of Science Editors:

Onyewuchi U. Managing environmentally stressed aging assets in electric power utilities. [Doctoral Dissertation]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/53150


Georgia Tech

7. Adil, Farhan. Applications of floating-gate based programmable mixed-signal reconfigurable systems.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 A mixed-signal reconfigurable platform gives the designer the choice of implementing systems using the benefits of both analog and digital circuits. The subject of this… (more)

Subjects/Keywords: FPAA; Mixed-signal IC; Reconfigurable systems

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APA (6th Edition):

Adil, F. (2014). Applications of floating-gate based programmable mixed-signal reconfigurable systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54272

Chicago Manual of Style (16th Edition):

Adil, Farhan. “Applications of floating-gate based programmable mixed-signal reconfigurable systems.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/54272.

MLA Handbook (7th Edition):

Adil, Farhan. “Applications of floating-gate based programmable mixed-signal reconfigurable systems.” 2014. Web. 19 Feb 2019.

Vancouver:

Adil F. Applications of floating-gate based programmable mixed-signal reconfigurable systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/54272.

Council of Science Editors:

Adil F. Applications of floating-gate based programmable mixed-signal reconfigurable systems. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/54272


Georgia Tech

8. Kumar, Vachan. Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 Modeling approaches are developed to optimize emerging on-chip and off-chip electrical interconnect technologies and benchmark them against conventional technologies. While transistor scaling results in an… (more)

Subjects/Keywords: Interconnect modeling; Graphene nanoribbons; Through silicon via, airgap interconnects

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APA (6th Edition):

Kumar, V. (2014). Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54280

Chicago Manual of Style (16th Edition):

Kumar, Vachan. “Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/54280.

MLA Handbook (7th Edition):

Kumar, Vachan. “Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies.” 2014. Web. 19 Feb 2019.

Vancouver:

Kumar V. Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/54280.

Council of Science Editors:

Kumar V. Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/54280


Georgia Tech

9. Song, Tae Joong. A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing.

Degree: PhD, Electrical and Computer Engineering, 2010, Georgia Tech

 This dissertation focuses on design and implementation of a fully-integrated SRAM-based arbitrary waveform generator for analog signal processing applications in a CMOS technology. The dissertation… (more)

Subjects/Keywords: Digital circuit; Spectrum sensing; SRAM; Arbitrary waveform generator; Analog signal processing; Low-power; MRSS; Metal oxide semiconductors, Complementary; Signal processing; Random access memory

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APA (6th Edition):

Song, T. J. (2010). A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/34760

Chicago Manual of Style (16th Edition):

Song, Tae Joong. “A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing.” 2010. Doctoral Dissertation, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/34760.

MLA Handbook (7th Edition):

Song, Tae Joong. “A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing.” 2010. Web. 19 Feb 2019.

Vancouver:

Song TJ. A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing. [Internet] [Doctoral dissertation]. Georgia Tech; 2010. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/34760.

Council of Science Editors:

Song TJ. A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing. [Doctoral Dissertation]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/34760


Georgia Tech

10. Kim, Hyungwook. CMOS radio-frequency power amplifiers for multi-standard wireless communications.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 The development of multi-standard wireless communication systems with low cost and high integration is continuously requested and accompanied by the explosive growth of the wireless… (more)

Subjects/Keywords: CMOS; Power amplifier; RF PA; Multi-standard wireless communications; Wireless communication systems; Power amplifiers; Metal oxide semiconductors, Complementary; Radio Transmitter-receivers

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APA (6th Edition):

Kim, H. (2011). CMOS radio-frequency power amplifiers for multi-standard wireless communications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/44786

Chicago Manual of Style (16th Edition):

Kim, Hyungwook. “CMOS radio-frequency power amplifiers for multi-standard wireless communications.” 2011. Doctoral Dissertation, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/44786.

MLA Handbook (7th Edition):

Kim, Hyungwook. “CMOS radio-frequency power amplifiers for multi-standard wireless communications.” 2011. Web. 19 Feb 2019.

Vancouver:

Kim H. CMOS radio-frequency power amplifiers for multi-standard wireless communications. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/44786.

Council of Science Editors:

Kim H. CMOS radio-frequency power amplifiers for multi-standard wireless communications. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/44786


Georgia Tech

11. Barale, Francesco. Design of integrated frequency synthesizers and clock-data recovery for 60 GHz wireless communications.

Degree: PhD, Electrical and Computer Engineering, 2010, Georgia Tech

 In this dissertation, the development of the first 60 GHz-standard compatible fully integrated 4-channel phase-locked loop (PLL) frequency synthesizer has been presented. The frequency synthesizer… (more)

Subjects/Keywords: CMOS; VCO; Frequency dividers; Clock-data recovery; Phase-locked loops; Frequency synthesizers; Wireless communication systems; Radio Transmitter-receivers; Metal oxide semiconductors, Complementary

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APA (6th Edition):

Barale, F. (2010). Design of integrated frequency synthesizers and clock-data recovery for 60 GHz wireless communications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/37216

Chicago Manual of Style (16th Edition):

Barale, Francesco. “Design of integrated frequency synthesizers and clock-data recovery for 60 GHz wireless communications.” 2010. Doctoral Dissertation, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/37216.

MLA Handbook (7th Edition):

Barale, Francesco. “Design of integrated frequency synthesizers and clock-data recovery for 60 GHz wireless communications.” 2010. Web. 19 Feb 2019.

Vancouver:

Barale F. Design of integrated frequency synthesizers and clock-data recovery for 60 GHz wireless communications. [Internet] [Doctoral dissertation]. Georgia Tech; 2010. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/37216.

Council of Science Editors:

Barale F. Design of integrated frequency synthesizers and clock-data recovery for 60 GHz wireless communications. [Doctoral Dissertation]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/37216

12. Lohith, Penmetsa Neela. Monolithic 3D integration of asynchronous systems.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 The goal of this thesis is to study the impact of 3D integration on asynchronous circuits and explore the benefits in power, performance and area… (more)

Subjects/Keywords: Asynchronous; 3DIC; Monolithic

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APA (6th Edition):

Lohith, P. N. (2014). Monolithic 3D integration of asynchronous systems. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53113

Chicago Manual of Style (16th Edition):

Lohith, Penmetsa Neela. “Monolithic 3D integration of asynchronous systems.” 2014. Masters Thesis, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/53113.

MLA Handbook (7th Edition):

Lohith, Penmetsa Neela. “Monolithic 3D integration of asynchronous systems.” 2014. Web. 19 Feb 2019.

Vancouver:

Lohith PN. Monolithic 3D integration of asynchronous systems. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/53113.

Council of Science Editors:

Lohith PN. Monolithic 3D integration of asynchronous systems. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/53113

13. Magudilu Vijayaraj, Thejasvi Magudilu. An empirical power model of a low power mobile platform.

Degree: MS, Electrical and Computer Engineering, 2013, Georgia Tech

 Power is one of the today’s major constraints for both hardware and software design. Thus the need to understand the statistics and distribution of power… (more)

Subjects/Keywords: Empirical power model; OMAP4460; Pandaboard; Power electronics; Energy consumption

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APA (6th Edition):

Magudilu Vijayaraj, T. M. (2013). An empirical power model of a low power mobile platform. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/49054

Chicago Manual of Style (16th Edition):

Magudilu Vijayaraj, Thejasvi Magudilu. “An empirical power model of a low power mobile platform.” 2013. Masters Thesis, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/49054.

MLA Handbook (7th Edition):

Magudilu Vijayaraj, Thejasvi Magudilu. “An empirical power model of a low power mobile platform.” 2013. Web. 19 Feb 2019.

Vancouver:

Magudilu Vijayaraj TM. An empirical power model of a low power mobile platform. [Internet] [Masters thesis]. Georgia Tech; 2013. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/49054.

Council of Science Editors:

Magudilu Vijayaraj TM. An empirical power model of a low power mobile platform. [Masters Thesis]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/49054

14. Parthasarathy, Swarrnna Karthik. Energy efficient active cooling of integrated circuits using embedded thermoelectric devices.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 With technology scaling, the amount of transistors on a single chip doubles itself every 18 months giving rise to increased power density levels. This has… (more)

Subjects/Keywords: Thermoelectric devices; Seebeck effect; Peltier effect; Thin-film TE devices; Mode switching

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APA (6th Edition):

Parthasarathy, S. K. (2014). Energy efficient active cooling of integrated circuits using embedded thermoelectric devices. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53047

Chicago Manual of Style (16th Edition):

Parthasarathy, Swarrnna Karthik. “Energy efficient active cooling of integrated circuits using embedded thermoelectric devices.” 2014. Masters Thesis, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/53047.

MLA Handbook (7th Edition):

Parthasarathy, Swarrnna Karthik. “Energy efficient active cooling of integrated circuits using embedded thermoelectric devices.” 2014. Web. 19 Feb 2019.

Vancouver:

Parthasarathy SK. Energy efficient active cooling of integrated circuits using embedded thermoelectric devices. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/53047.

Council of Science Editors:

Parthasarathy SK. Energy efficient active cooling of integrated circuits using embedded thermoelectric devices. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/53047

15. Nigania, Nimit. FPGA prototyping of custom GPGPUs.

Degree: MS, Computer Science, 2014, Georgia Tech

 Prototyping new systems on hardware is a time-consuming task with limited scope for architectural exploration. The aim of this work was to perform fast prototyping… (more)

Subjects/Keywords: General purpose graphic processing units (GPGPU); Field programmable gate arrays (FPGA); ISA; Cache; Field programmable gate arrays; Rapid prototyping; Computer simulation; Graphics processing units

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APA (6th Edition):

Nigania, N. (2014). FPGA prototyping of custom GPGPUs. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51966

Chicago Manual of Style (16th Edition):

Nigania, Nimit. “FPGA prototyping of custom GPGPUs.” 2014. Masters Thesis, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/51966.

MLA Handbook (7th Edition):

Nigania, Nimit. “FPGA prototyping of custom GPGPUs.” 2014. Web. 19 Feb 2019.

Vancouver:

Nigania N. FPGA prototyping of custom GPGPUs. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/51966.

Council of Science Editors:

Nigania N. FPGA prototyping of custom GPGPUs. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51966

16. Yeleswarapu, Krishnamurthy. TCAD simulation framework for the study of TSV-device interaction.

Degree: MS, Electrical and Computer Engineering, 2013, Georgia Tech

 With the reduction in transistor dimensions to a few tens of nanometers as a result of aggressive scaling, interconnect delay has now become one of… (more)

Subjects/Keywords: Through silicon via; 3D IC; Three-dimensional integrated circuits

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APA (6th Edition):

Yeleswarapu, K. (2013). TCAD simulation framework for the study of TSV-device interaction. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51785

Chicago Manual of Style (16th Edition):

Yeleswarapu, Krishnamurthy. “TCAD simulation framework for the study of TSV-device interaction.” 2013. Masters Thesis, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/51785.

MLA Handbook (7th Edition):

Yeleswarapu, Krishnamurthy. “TCAD simulation framework for the study of TSV-device interaction.” 2013. Web. 19 Feb 2019.

Vancouver:

Yeleswarapu K. TCAD simulation framework for the study of TSV-device interaction. [Internet] [Masters thesis]. Georgia Tech; 2013. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/51785.

Council of Science Editors:

Yeleswarapu K. TCAD simulation framework for the study of TSV-device interaction. [Masters Thesis]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/51785

17. Zaveri, Jesal. Electrical and fluidic interconnect design and technology for 3D ICS.

Degree: MS, Electrical and Computer Engineering, 2011, Georgia Tech

 For decades, advances in device scaling has proven to be critical in improving the performance and productivity of 2D systems. In this thesis, we explore… (more)

Subjects/Keywords: Through-silicon via; Microchannel cooling; Three dimensional integration; Multichip modules (Microelectronics); Microelectronics; Three-dimensional integrated circuits; Integrated circuits; Interconnects (Integrated circuit technology)

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APA (6th Edition):

Zaveri, J. (2011). Electrical and fluidic interconnect design and technology for 3D ICS. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/39550

Chicago Manual of Style (16th Edition):

Zaveri, Jesal. “Electrical and fluidic interconnect design and technology for 3D ICS.” 2011. Masters Thesis, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/39550.

MLA Handbook (7th Edition):

Zaveri, Jesal. “Electrical and fluidic interconnect design and technology for 3D ICS.” 2011. Web. 19 Feb 2019.

Vancouver:

Zaveri J. Electrical and fluidic interconnect design and technology for 3D ICS. [Internet] [Masters thesis]. Georgia Tech; 2011. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/39550.

Council of Science Editors:

Zaveri J. Electrical and fluidic interconnect design and technology for 3D ICS. [Masters Thesis]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/39550

18. Rasquinha, Mitchelle. An energy efficient cache design using spin torque transfer (STT) RAM.

Degree: MS, Electrical and Computer Engineering, 2011, Georgia Tech

 The advent of many core architectures has coincided with the energy and power limited design of modern processors. Projections for main memory clearly show widening… (more)

Subjects/Keywords: Non volatile memory; Cache memory; Random access memory

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APA (6th Edition):

Rasquinha, M. (2011). An energy efficient cache design using spin torque transfer (STT) RAM. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/42715

Chicago Manual of Style (16th Edition):

Rasquinha, Mitchelle. “An energy efficient cache design using spin torque transfer (STT) RAM.” 2011. Masters Thesis, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/42715.

MLA Handbook (7th Edition):

Rasquinha, Mitchelle. “An energy efficient cache design using spin torque transfer (STT) RAM.” 2011. Web. 19 Feb 2019.

Vancouver:

Rasquinha M. An energy efficient cache design using spin torque transfer (STT) RAM. [Internet] [Masters thesis]. Georgia Tech; 2011. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/42715.

Council of Science Editors:

Rasquinha M. An energy efficient cache design using spin torque transfer (STT) RAM. [Masters Thesis]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/42715

19. Nair, Prashant. Designing low power SRAM system using energy compression.

Degree: MS, Electrical and Computer Engineering, 2013, Georgia Tech

 The power consumption in commercial processors and application specific integrated circuits increases with decreasing technology nodes. Power saving techniques have become a first class design… (more)

Subjects/Keywords: Computer architecture; Leakage reduction; SRAM; VLSI; Low power; Random access memory; Image processing Digital techniques; Digital video

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APA (6th Edition):

Nair, P. (2013). Designing low power SRAM system using energy compression. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/47663

Chicago Manual of Style (16th Edition):

Nair, Prashant. “Designing low power SRAM system using energy compression.” 2013. Masters Thesis, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/47663.

MLA Handbook (7th Edition):

Nair, Prashant. “Designing low power SRAM system using energy compression.” 2013. Web. 19 Feb 2019.

Vancouver:

Nair P. Designing low power SRAM system using energy compression. [Internet] [Masters thesis]. Georgia Tech; 2013. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/47663.

Council of Science Editors:

Nair P. Designing low power SRAM system using energy compression. [Masters Thesis]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/47663

20. McLaughlin, Adam Thomas. Power-constrained performance optimization of GPU graph traversal.

Degree: MS, Electrical and Computer Engineering, 2013, Georgia Tech

 Graph traversal represents an important class of graph algorithms that is the nucleus of many large scale graph analytics applications. While improving the performance of… (more)

Subjects/Keywords: GPU architecture; Graph algorithms; Power-constrained environments; Graph algorithms; Graphics processing units

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APA (6th Edition):

McLaughlin, A. T. (2013). Power-constrained performance optimization of GPU graph traversal. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/50209

Chicago Manual of Style (16th Edition):

McLaughlin, Adam Thomas. “Power-constrained performance optimization of GPU graph traversal.” 2013. Masters Thesis, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/50209.

MLA Handbook (7th Edition):

McLaughlin, Adam Thomas. “Power-constrained performance optimization of GPU graph traversal.” 2013. Web. 19 Feb 2019.

Vancouver:

McLaughlin AT. Power-constrained performance optimization of GPU graph traversal. [Internet] [Masters thesis]. Georgia Tech; 2013. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/50209.

Council of Science Editors:

McLaughlin AT. Power-constrained performance optimization of GPU graph traversal. [Masters Thesis]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/50209

21. Sullivan, Owen A. Embedded thermoelectric devices for on-chip cooling and power generation.

Degree: MS, Mechanical Engineering, 2012, Georgia Tech

 Thermoelectric devices are capable of providing both localized active cooling and waste heat power generation. This work will explore the possibility of embedding thermoelectric devices… (more)

Subjects/Keywords: Numerical modelling; Seebeck; Peltier; FLUENT; SPICE; Contact resistance; Load resistance; Thermoelectric materials; Semiconductors; Thermoelectric cooling; Thermoelectricity

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APA (6th Edition):

Sullivan, O. A. (2012). Embedded thermoelectric devices for on-chip cooling and power generation. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/45867

Chicago Manual of Style (16th Edition):

Sullivan, Owen A. “Embedded thermoelectric devices for on-chip cooling and power generation.” 2012. Masters Thesis, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/45867.

MLA Handbook (7th Edition):

Sullivan, Owen A. “Embedded thermoelectric devices for on-chip cooling and power generation.” 2012. Web. 19 Feb 2019.

Vancouver:

Sullivan OA. Embedded thermoelectric devices for on-chip cooling and power generation. [Internet] [Masters thesis]. Georgia Tech; 2012. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/45867.

Council of Science Editors:

Sullivan OA. Embedded thermoelectric devices for on-chip cooling and power generation. [Masters Thesis]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/45867

22. Zia, Muneeb. SRAM system design for memory based computing.

Degree: MS, Electrical and Computer Engineering, 2013, Georgia Tech

 The objective of the research was to design and test an SRAM system which can meet the performance criteria for Memory Based Computing (MBC). This… (more)

Subjects/Keywords: Look-up table; Asymmetric SRAM; Spatial computing; Temporal computing; Re-configurable computing; Memory based computing; Pulsed read operation; Memory management (Computer science); Random access memory

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APA (6th Edition):

Zia, M. (2013). SRAM system design for memory based computing. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/47636

Chicago Manual of Style (16th Edition):

Zia, Muneeb. “SRAM system design for memory based computing.” 2013. Masters Thesis, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/47636.

MLA Handbook (7th Edition):

Zia, Muneeb. “SRAM system design for memory based computing.” 2013. Web. 19 Feb 2019.

Vancouver:

Zia M. SRAM system design for memory based computing. [Internet] [Masters thesis]. Georgia Tech; 2013. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/47636.

Council of Science Editors:

Zia M. SRAM system design for memory based computing. [Masters Thesis]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/47636

23. Ceyhan, Ahmet. Interconnects for future technology generations - conventional CMOS with copper/low-k and beyond.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 The limitations of the conventional Cu/low-k interconnect technology for use in future ultra-scaled integrated circuits down to 7 nm in the year 2020 are investigated… (more)

Subjects/Keywords: Interconnects; Cu/low-k; Carbon nanotubes; Benchmarking; Tunneling FETs; Carbon nanotube FETs; Physical design and optimization

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APA (6th Edition):

Ceyhan, A. (2014). Interconnects for future technology generations - conventional CMOS with copper/low-k and beyond. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53080

Chicago Manual of Style (16th Edition):

Ceyhan, Ahmet. “Interconnects for future technology generations - conventional CMOS with copper/low-k and beyond.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/53080.

MLA Handbook (7th Edition):

Ceyhan, Ahmet. “Interconnects for future technology generations - conventional CMOS with copper/low-k and beyond.” 2014. Web. 19 Feb 2019.

Vancouver:

Ceyhan A. Interconnects for future technology generations - conventional CMOS with copper/low-k and beyond. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/53080.

Council of Science Editors:

Ceyhan A. Interconnects for future technology generations - conventional CMOS with copper/low-k and beyond. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/53080

24. Jung, Moongon. Low power and reliable design methodologies for 3D ICs.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 The main objective of this dissertation is to explore and develop computer-aided-design methodologies and optimization techniques for reliability, performance, and power of through-silicon-via-based 3D IC… (more)

Subjects/Keywords: 3D IC; TSV; Low power design; Thermo-mechanical reliability; Power delivery; Three-dimensional integrated circuits; Integrated circuits; Integrated circuits Design and construction

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APA (6th Edition):

Jung, M. (2014). Low power and reliable design methodologies for 3D ICs. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51824

Chicago Manual of Style (16th Edition):

Jung, Moongon. “Low power and reliable design methodologies for 3D ICs.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/51824.

MLA Handbook (7th Edition):

Jung, Moongon. “Low power and reliable design methodologies for 3D ICs.” 2014. Web. 19 Feb 2019.

Vancouver:

Jung M. Low power and reliable design methodologies for 3D ICs. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/51824.

Council of Science Editors:

Jung M. Low power and reliable design methodologies for 3D ICs. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51824

25. Kim, Jungbae. Organic-inorganic hybrid thin film transistors and electronic circuits.

Degree: PhD, Electrical and Computer Engineering, 2010, Georgia Tech

 Thin-film transistors (TFTs) capable of low-voltage and high-frequency operation will be required to reduce the power consumption of next generation electronic devices driven by microelectronic… (more)

Subjects/Keywords: Transistor; Oxide; Organic; InGaZnO; Pentacene; Thin film transistors; Organic semiconductors; Microelectronics; Electric inverters

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APA (6th Edition):

Kim, J. (2010). Organic-inorganic hybrid thin film transistors and electronic circuits. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/34683

Chicago Manual of Style (16th Edition):

Kim, Jungbae. “Organic-inorganic hybrid thin film transistors and electronic circuits.” 2010. Doctoral Dissertation, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/34683.

MLA Handbook (7th Edition):

Kim, Jungbae. “Organic-inorganic hybrid thin film transistors and electronic circuits.” 2010. Web. 19 Feb 2019.

Vancouver:

Kim J. Organic-inorganic hybrid thin film transistors and electronic circuits. [Internet] [Doctoral dissertation]. Georgia Tech; 2010. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/34683.

Council of Science Editors:

Kim J. Organic-inorganic hybrid thin film transistors and electronic circuits. [Doctoral Dissertation]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/34683

26. Natarajan, Vishwanath. Self-healing RF SoCs: low cost built-in test and control driven simultaneous tuning of multiple performance metrics.

Degree: PhD, Electrical and Computer Engineering, 2010, Georgia Tech

 The advent of deep submicron technology coupled with ever increasing demands from the customer for more functionality on a compact silicon real estate has led… (more)

Subjects/Keywords: Embedded sensors; Low-cost testing; Behavioral modeling; Wireless; OFDM; Calibration; Compensation; Tuning; Self-healing; Production testing; RF testing; Loop-back; Black box modeling; Parameter identification; Process variations; Yield; Receiver; Transmitter; Wireless communication systems; Microelectronics

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APA (6th Edition):

Natarajan, V. (2010). Self-healing RF SoCs: low cost built-in test and control driven simultaneous tuning of multiple performance metrics. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/37165

Chicago Manual of Style (16th Edition):

Natarajan, Vishwanath. “Self-healing RF SoCs: low cost built-in test and control driven simultaneous tuning of multiple performance metrics.” 2010. Doctoral Dissertation, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/37165.

MLA Handbook (7th Edition):

Natarajan, Vishwanath. “Self-healing RF SoCs: low cost built-in test and control driven simultaneous tuning of multiple performance metrics.” 2010. Web. 19 Feb 2019.

Vancouver:

Natarajan V. Self-healing RF SoCs: low cost built-in test and control driven simultaneous tuning of multiple performance metrics. [Internet] [Doctoral dissertation]. Georgia Tech; 2010. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/37165.

Council of Science Editors:

Natarajan V. Self-healing RF SoCs: low cost built-in test and control driven simultaneous tuning of multiple performance metrics. [Doctoral Dissertation]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/37165

27. Lee, Dongwon. High-performance computer system architectures for embedded computing.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 The main objective of this thesis is to propose new methods for designing high-performance embedded computer system architectures. To achieve the goal, three major components… (more)

Subjects/Keywords: Turbo decoding; GPU architecture; SDF graph; DRAM system; Embedded computer systems; High performance computing; Electronic data processing; Parallel processing (Electronic computers)

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APA (6th Edition):

Lee, D. (2011). High-performance computer system architectures for embedded computing. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/42766

Chicago Manual of Style (16th Edition):

Lee, Dongwon. “High-performance computer system architectures for embedded computing.” 2011. Doctoral Dissertation, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/42766.

MLA Handbook (7th Edition):

Lee, Dongwon. “High-performance computer system architectures for embedded computing.” 2011. Web. 19 Feb 2019.

Vancouver:

Lee D. High-performance computer system architectures for embedded computing. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/42766.

Council of Science Editors:

Lee D. High-performance computer system architectures for embedded computing. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/42766

28. Das, Debrup. Dynamic control of grid power flow using controllable network transformers.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 The objective of the research is to develop a cost-effective, dynamic grid controller called the controllable network transformer (CNT) that can be implemented by augmenting… (more)

Subjects/Keywords: Transmission power flow control; FACTS; Electricity; Electric power distribution; Electric power distribution Automation; Smart power grids

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APA (6th Edition):

Das, D. (2011). Dynamic control of grid power flow using controllable network transformers. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/43739

Chicago Manual of Style (16th Edition):

Das, Debrup. “Dynamic control of grid power flow using controllable network transformers.” 2011. Doctoral Dissertation, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/43739.

MLA Handbook (7th Edition):

Das, Debrup. “Dynamic control of grid power flow using controllable network transformers.” 2011. Web. 19 Feb 2019.

Vancouver:

Das D. Dynamic control of grid power flow using controllable network transformers. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/43739.

Council of Science Editors:

Das D. Dynamic control of grid power flow using controllable network transformers. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/43739

29. Kim, Se Hun. Accuracy-energy tradeoffs in digital image processing using embedded computing platforms.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 As more and more multimedia applications are integrated in mobile devices, a significant amount of energy is devoted to digital signal processing (DSP). Thus, reducing… (more)

Subjects/Keywords: Digital image processing; Low power; Aggressive votlage scaling; Image processing Digital techniques; Signal processing Digital techniques

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APA (6th Edition):

Kim, S. H. (2011). Accuracy-energy tradeoffs in digital image processing using embedded computing platforms. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/42881

Chicago Manual of Style (16th Edition):

Kim, Se Hun. “Accuracy-energy tradeoffs in digital image processing using embedded computing platforms.” 2011. Doctoral Dissertation, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/42881.

MLA Handbook (7th Edition):

Kim, Se Hun. “Accuracy-energy tradeoffs in digital image processing using embedded computing platforms.” 2011. Web. 19 Feb 2019.

Vancouver:

Kim SH. Accuracy-energy tradeoffs in digital image processing using embedded computing platforms. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/42881.

Council of Science Editors:

Kim SH. Accuracy-energy tradeoffs in digital image processing using embedded computing platforms. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/42881

30. Chatterjee, Subho. A design methodology for robust, energy-efficient, application-aware memory systems.

Degree: PhD, Electrical and Computer Engineering, 2012, Georgia Tech

 Memory design is a crucial component of VLSI system design from area, power and performance perspectives. To meet the increasingly challenging system specifications, architecture, circuit… (more)

Subjects/Keywords: Application-aware; SRAM; STTRAM; Integrated circuits Very large scale integration; Memory management (Computer science); Computer storage devices; Random access memory

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APA (6th Edition):

Chatterjee, S. (2012). A design methodology for robust, energy-efficient, application-aware memory systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/50146

Chicago Manual of Style (16th Edition):

Chatterjee, Subho. “A design methodology for robust, energy-efficient, application-aware memory systems.” 2012. Doctoral Dissertation, Georgia Tech. Accessed February 19, 2019. http://hdl.handle.net/1853/50146.

MLA Handbook (7th Edition):

Chatterjee, Subho. “A design methodology for robust, energy-efficient, application-aware memory systems.” 2012. Web. 19 Feb 2019.

Vancouver:

Chatterjee S. A design methodology for robust, energy-efficient, application-aware memory systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2012. [cited 2019 Feb 19]. Available from: http://hdl.handle.net/1853/50146.

Council of Science Editors:

Chatterjee S. A design methodology for robust, energy-efficient, application-aware memory systems. [Doctoral Dissertation]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/50146

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