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Level: masters

You searched for +publisher:"Georgia Tech" +contributor:("Mukhopadhyay, Saibal"). Showing records 1 – 20 of 20 total matches.

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Georgia Tech

1. VanDerheyden, Andrew Louis. Characterization of thermal coupling in chip multiprocessors.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 For semiconductor processors temperature increases leakage current, which in turn in- creases the temperature of the processor. This increase in heat is seen by other… (more)

Subjects/Keywords: Thermal management; Thermal characterization; Thermal coupling; High performance processors; Thermal analysis

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APA (6th Edition):

VanDerheyden, A. L. (2014). Characterization of thermal coupling in chip multiprocessors. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51892

Chicago Manual of Style (16th Edition):

VanDerheyden, Andrew Louis. “Characterization of thermal coupling in chip multiprocessors.” 2014. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/51892.

MLA Handbook (7th Edition):

VanDerheyden, Andrew Louis. “Characterization of thermal coupling in chip multiprocessors.” 2014. Web. 16 Feb 2019.

Vancouver:

VanDerheyden AL. Characterization of thermal coupling in chip multiprocessors. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/51892.

Council of Science Editors:

VanDerheyden AL. Characterization of thermal coupling in chip multiprocessors. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51892

2. Bonhomme, Phillip. Circuit modeling of spintronic devices: a SPICE implementation.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 Every engineer that has worked on designing an integrated circuit has to leverage an under- standing of device physics. Understanding device physics is essential when… (more)

Subjects/Keywords: SPICE; Spintronics; Circuit simulation; Magnetization dynamics; Spintronics; Mathematical models

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APA (6th Edition):

Bonhomme, P. (2014). Circuit modeling of spintronic devices: a SPICE implementation. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51818

Chicago Manual of Style (16th Edition):

Bonhomme, Phillip. “Circuit modeling of spintronic devices: a SPICE implementation.” 2014. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/51818.

MLA Handbook (7th Edition):

Bonhomme, Phillip. “Circuit modeling of spintronic devices: a SPICE implementation.” 2014. Web. 16 Feb 2019.

Vancouver:

Bonhomme P. Circuit modeling of spintronic devices: a SPICE implementation. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/51818.

Council of Science Editors:

Bonhomme P. Circuit modeling of spintronic devices: a SPICE implementation. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51818

3. Ku, Bon Woong Woong. Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node.

Degree: MS, Electrical and Computer Engineering, 2017, Georgia Tech

 The nature of device scaling in the 7nm era is changing from the traditional scheme driven by Moore’s law because of the physical and economic… (more)

Subjects/Keywords: Gate-level; Monolithic 3D IC; PPC tradeoff; 7nm technology node

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APA (6th Edition):

Ku, B. W. W. (2017). Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58257

Chicago Manual of Style (16th Edition):

Ku, Bon Woong Woong. “Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node.” 2017. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/58257.

MLA Handbook (7th Edition):

Ku, Bon Woong Woong. “Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node.” 2017. Web. 16 Feb 2019.

Vancouver:

Ku BWW. Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/58257.

Council of Science Editors:

Ku BWW. Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58257


Georgia Tech

4. Chintaluri, Ashwin K. Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays.

Degree: MS, Electrical and Computer Engineering, 2016, Georgia Tech

 Spin transfer torque magnetic random access memory (STT-MRAM) is a competitive, future memory technology that has gained immense interest in recent years due to its… (more)

Subjects/Keywords: STT-MRAM; Variation; Faults

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APA (6th Edition):

Chintaluri, A. K. (2016). Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55060

Chicago Manual of Style (16th Edition):

Chintaluri, Ashwin K. “Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays.” 2016. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/55060.

MLA Handbook (7th Edition):

Chintaluri, Ashwin K. “Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays.” 2016. Web. 16 Feb 2019.

Vancouver:

Chintaluri AK. Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/55060.

Council of Science Editors:

Chintaluri AK. Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55060

5. Lohith, Penmetsa Neela. Monolithic 3D integration of asynchronous systems.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 The goal of this thesis is to study the impact of 3D integration on asynchronous circuits and explore the benefits in power, performance and area… (more)

Subjects/Keywords: Asynchronous; 3DIC; Monolithic

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APA (6th Edition):

Lohith, P. N. (2014). Monolithic 3D integration of asynchronous systems. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53113

Chicago Manual of Style (16th Edition):

Lohith, Penmetsa Neela. “Monolithic 3D integration of asynchronous systems.” 2014. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/53113.

MLA Handbook (7th Edition):

Lohith, Penmetsa Neela. “Monolithic 3D integration of asynchronous systems.” 2014. Web. 16 Feb 2019.

Vancouver:

Lohith PN. Monolithic 3D integration of asynchronous systems. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/53113.

Council of Science Editors:

Lohith PN. Monolithic 3D integration of asynchronous systems. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/53113

6. Samal, Kruttidipta. FPGA acceleration of CNN training.

Degree: MS, Electrical and Computer Engineering, 2015, Georgia Tech

 This thesis presents the results of an architectural study on the design of FPGA- based architectures for convolutional neural networks (CNNs). We have analyzed the… (more)

Subjects/Keywords: CNN; FPGA; Deep learning

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APA (6th Edition):

Samal, K. (2015). FPGA acceleration of CNN training. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54467

Chicago Manual of Style (16th Edition):

Samal, Kruttidipta. “FPGA acceleration of CNN training.” 2015. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/54467.

MLA Handbook (7th Edition):

Samal, Kruttidipta. “FPGA acceleration of CNN training.” 2015. Web. 16 Feb 2019.

Vancouver:

Samal K. FPGA acceleration of CNN training. [Internet] [Masters thesis]. Georgia Tech; 2015. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/54467.

Council of Science Editors:

Samal K. FPGA acceleration of CNN training. [Masters Thesis]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/54467

7. Subramanian, Ashwin Srinath. Enhancing microprocessor power efficiency through clock-data compensation.

Degree: MS, Electrical and Computer Engineering, 2015, Georgia Tech

 The Smartphone revolution and the Internet of Things (IoTs) have triggered rapid advances in complex system-on-chips (SoCs) that increasing provide more functionality within a tight… (more)

Subjects/Keywords: Power management; Adaptive Clocking; Clock-data compensation; Power efficiency

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APA (6th Edition):

Subramanian, A. S. (2015). Enhancing microprocessor power efficiency through clock-data compensation. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54471

Chicago Manual of Style (16th Edition):

Subramanian, Ashwin Srinath. “Enhancing microprocessor power efficiency through clock-data compensation.” 2015. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/54471.

MLA Handbook (7th Edition):

Subramanian, Ashwin Srinath. “Enhancing microprocessor power efficiency through clock-data compensation.” 2015. Web. 16 Feb 2019.

Vancouver:

Subramanian AS. Enhancing microprocessor power efficiency through clock-data compensation. [Internet] [Masters thesis]. Georgia Tech; 2015. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/54471.

Council of Science Editors:

Subramanian AS. Enhancing microprocessor power efficiency through clock-data compensation. [Masters Thesis]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/54471

8. Ahmed, Khondker Zakir. Low voltage autonomous buck-boost regulator for wide input energy harvesting.

Degree: MS, Electrical and Computer Engineering, 2015, Georgia Tech

 While high power buck-boost regulators have been extensively researched and developed in the academia and industry, low power counterparts have only recently gained momentum due… (more)

Subjects/Keywords: Buck-boost regulator; |Low voltage energy harvesting; Low current regulator; nA bias current regulator

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APA (6th Edition):

Ahmed, K. Z. (2015). Low voltage autonomous buck-boost regulator for wide input energy harvesting. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53604

Chicago Manual of Style (16th Edition):

Ahmed, Khondker Zakir. “Low voltage autonomous buck-boost regulator for wide input energy harvesting.” 2015. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/53604.

MLA Handbook (7th Edition):

Ahmed, Khondker Zakir. “Low voltage autonomous buck-boost regulator for wide input energy harvesting.” 2015. Web. 16 Feb 2019.

Vancouver:

Ahmed KZ. Low voltage autonomous buck-boost regulator for wide input energy harvesting. [Internet] [Masters thesis]. Georgia Tech; 2015. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/53604.

Council of Science Editors:

Ahmed KZ. Low voltage autonomous buck-boost regulator for wide input energy harvesting. [Masters Thesis]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53604

9. Mudassar, Burhan Ahmad. Design and implementation of a content aware image processing module on FPGA.

Degree: MS, Electrical and Computer Engineering, 2015, Georgia Tech

 In this thesis, we tackle the problem of designing and implementing a wireless video sensor network for a surveillance application. The goal was to design… (more)

Subjects/Keywords: Content aware; Image processing; Edge detection; Image preprocessing; Low power; FPGA

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APA (6th Edition):

Mudassar, B. A. (2015). Design and implementation of a content aware image processing module on FPGA. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53618

Chicago Manual of Style (16th Edition):

Mudassar, Burhan Ahmad. “Design and implementation of a content aware image processing module on FPGA.” 2015. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/53618.

MLA Handbook (7th Edition):

Mudassar, Burhan Ahmad. “Design and implementation of a content aware image processing module on FPGA.” 2015. Web. 16 Feb 2019.

Vancouver:

Mudassar BA. Design and implementation of a content aware image processing module on FPGA. [Internet] [Masters thesis]. Georgia Tech; 2015. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/53618.

Council of Science Editors:

Mudassar BA. Design and implementation of a content aware image processing module on FPGA. [Masters Thesis]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53618

10. Magudilu Vijayaraj, Thejasvi Magudilu. An empirical power model of a low power mobile platform.

Degree: MS, Electrical and Computer Engineering, 2013, Georgia Tech

 Power is one of the today’s major constraints for both hardware and software design. Thus the need to understand the statistics and distribution of power… (more)

Subjects/Keywords: Empirical power model; OMAP4460; Pandaboard; Power electronics; Energy consumption

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APA (6th Edition):

Magudilu Vijayaraj, T. M. (2013). An empirical power model of a low power mobile platform. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/49054

Chicago Manual of Style (16th Edition):

Magudilu Vijayaraj, Thejasvi Magudilu. “An empirical power model of a low power mobile platform.” 2013. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/49054.

MLA Handbook (7th Edition):

Magudilu Vijayaraj, Thejasvi Magudilu. “An empirical power model of a low power mobile platform.” 2013. Web. 16 Feb 2019.

Vancouver:

Magudilu Vijayaraj TM. An empirical power model of a low power mobile platform. [Internet] [Masters thesis]. Georgia Tech; 2013. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/49054.

Council of Science Editors:

Magudilu Vijayaraj TM. An empirical power model of a low power mobile platform. [Masters Thesis]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/49054

11. Parthasarathy, Swarrnna Karthik. Energy efficient active cooling of integrated circuits using embedded thermoelectric devices.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 With technology scaling, the amount of transistors on a single chip doubles itself every 18 months giving rise to increased power density levels. This has… (more)

Subjects/Keywords: Thermoelectric devices; Seebeck effect; Peltier effect; Thin-film TE devices; Mode switching

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APA (6th Edition):

Parthasarathy, S. K. (2014). Energy efficient active cooling of integrated circuits using embedded thermoelectric devices. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53047

Chicago Manual of Style (16th Edition):

Parthasarathy, Swarrnna Karthik. “Energy efficient active cooling of integrated circuits using embedded thermoelectric devices.” 2014. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/53047.

MLA Handbook (7th Edition):

Parthasarathy, Swarrnna Karthik. “Energy efficient active cooling of integrated circuits using embedded thermoelectric devices.” 2014. Web. 16 Feb 2019.

Vancouver:

Parthasarathy SK. Energy efficient active cooling of integrated circuits using embedded thermoelectric devices. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/53047.

Council of Science Editors:

Parthasarathy SK. Energy efficient active cooling of integrated circuits using embedded thermoelectric devices. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/53047

12. Nigania, Nimit. FPGA prototyping of custom GPGPUs.

Degree: MS, Computer Science, 2014, Georgia Tech

 Prototyping new systems on hardware is a time-consuming task with limited scope for architectural exploration. The aim of this work was to perform fast prototyping… (more)

Subjects/Keywords: General purpose graphic processing units (GPGPU); Field programmable gate arrays (FPGA); ISA; Cache; Field programmable gate arrays; Rapid prototyping; Computer simulation; Graphics processing units

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APA (6th Edition):

Nigania, N. (2014). FPGA prototyping of custom GPGPUs. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51966

Chicago Manual of Style (16th Edition):

Nigania, Nimit. “FPGA prototyping of custom GPGPUs.” 2014. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/51966.

MLA Handbook (7th Edition):

Nigania, Nimit. “FPGA prototyping of custom GPGPUs.” 2014. Web. 16 Feb 2019.

Vancouver:

Nigania N. FPGA prototyping of custom GPGPUs. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/51966.

Council of Science Editors:

Nigania N. FPGA prototyping of custom GPGPUs. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51966

13. Yeleswarapu, Krishnamurthy. TCAD simulation framework for the study of TSV-device interaction.

Degree: MS, Electrical and Computer Engineering, 2013, Georgia Tech

 With the reduction in transistor dimensions to a few tens of nanometers as a result of aggressive scaling, interconnect delay has now become one of… (more)

Subjects/Keywords: Through silicon via; 3D IC; Three-dimensional integrated circuits

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APA (6th Edition):

Yeleswarapu, K. (2013). TCAD simulation framework for the study of TSV-device interaction. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51785

Chicago Manual of Style (16th Edition):

Yeleswarapu, Krishnamurthy. “TCAD simulation framework for the study of TSV-device interaction.” 2013. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/51785.

MLA Handbook (7th Edition):

Yeleswarapu, Krishnamurthy. “TCAD simulation framework for the study of TSV-device interaction.” 2013. Web. 16 Feb 2019.

Vancouver:

Yeleswarapu K. TCAD simulation framework for the study of TSV-device interaction. [Internet] [Masters thesis]. Georgia Tech; 2013. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/51785.

Council of Science Editors:

Yeleswarapu K. TCAD simulation framework for the study of TSV-device interaction. [Masters Thesis]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/51785

14. Zaveri, Jesal. Electrical and fluidic interconnect design and technology for 3D ICS.

Degree: MS, Electrical and Computer Engineering, 2011, Georgia Tech

 For decades, advances in device scaling has proven to be critical in improving the performance and productivity of 2D systems. In this thesis, we explore… (more)

Subjects/Keywords: Through-silicon via; Microchannel cooling; Three dimensional integration; Multichip modules (Microelectronics); Microelectronics; Three-dimensional integrated circuits; Integrated circuits; Interconnects (Integrated circuit technology)

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APA (6th Edition):

Zaveri, J. (2011). Electrical and fluidic interconnect design and technology for 3D ICS. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/39550

Chicago Manual of Style (16th Edition):

Zaveri, Jesal. “Electrical and fluidic interconnect design and technology for 3D ICS.” 2011. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/39550.

MLA Handbook (7th Edition):

Zaveri, Jesal. “Electrical and fluidic interconnect design and technology for 3D ICS.” 2011. Web. 16 Feb 2019.

Vancouver:

Zaveri J. Electrical and fluidic interconnect design and technology for 3D ICS. [Internet] [Masters thesis]. Georgia Tech; 2011. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/39550.

Council of Science Editors:

Zaveri J. Electrical and fluidic interconnect design and technology for 3D ICS. [Masters Thesis]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/39550

15. Rasquinha, Mitchelle. An energy efficient cache design using spin torque transfer (STT) RAM.

Degree: MS, Electrical and Computer Engineering, 2011, Georgia Tech

 The advent of many core architectures has coincided with the energy and power limited design of modern processors. Projections for main memory clearly show widening… (more)

Subjects/Keywords: Non volatile memory; Cache memory; Random access memory

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APA (6th Edition):

Rasquinha, M. (2011). An energy efficient cache design using spin torque transfer (STT) RAM. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/42715

Chicago Manual of Style (16th Edition):

Rasquinha, Mitchelle. “An energy efficient cache design using spin torque transfer (STT) RAM.” 2011. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/42715.

MLA Handbook (7th Edition):

Rasquinha, Mitchelle. “An energy efficient cache design using spin torque transfer (STT) RAM.” 2011. Web. 16 Feb 2019.

Vancouver:

Rasquinha M. An energy efficient cache design using spin torque transfer (STT) RAM. [Internet] [Masters thesis]. Georgia Tech; 2011. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/42715.

Council of Science Editors:

Rasquinha M. An energy efficient cache design using spin torque transfer (STT) RAM. [Masters Thesis]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/42715

16. Nair, Prashant. Designing low power SRAM system using energy compression.

Degree: MS, Electrical and Computer Engineering, 2013, Georgia Tech

 The power consumption in commercial processors and application specific integrated circuits increases with decreasing technology nodes. Power saving techniques have become a first class design… (more)

Subjects/Keywords: Computer architecture; Leakage reduction; SRAM; VLSI; Low power; Random access memory; Image processing Digital techniques; Digital video

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APA (6th Edition):

Nair, P. (2013). Designing low power SRAM system using energy compression. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/47663

Chicago Manual of Style (16th Edition):

Nair, Prashant. “Designing low power SRAM system using energy compression.” 2013. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/47663.

MLA Handbook (7th Edition):

Nair, Prashant. “Designing low power SRAM system using energy compression.” 2013. Web. 16 Feb 2019.

Vancouver:

Nair P. Designing low power SRAM system using energy compression. [Internet] [Masters thesis]. Georgia Tech; 2013. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/47663.

Council of Science Editors:

Nair P. Designing low power SRAM system using energy compression. [Masters Thesis]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/47663

17. McLaughlin, Adam Thomas. Power-constrained performance optimization of GPU graph traversal.

Degree: MS, Electrical and Computer Engineering, 2013, Georgia Tech

 Graph traversal represents an important class of graph algorithms that is the nucleus of many large scale graph analytics applications. While improving the performance of… (more)

Subjects/Keywords: GPU architecture; Graph algorithms; Power-constrained environments; Graph algorithms; Graphics processing units

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APA (6th Edition):

McLaughlin, A. T. (2013). Power-constrained performance optimization of GPU graph traversal. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/50209

Chicago Manual of Style (16th Edition):

McLaughlin, Adam Thomas. “Power-constrained performance optimization of GPU graph traversal.” 2013. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/50209.

MLA Handbook (7th Edition):

McLaughlin, Adam Thomas. “Power-constrained performance optimization of GPU graph traversal.” 2013. Web. 16 Feb 2019.

Vancouver:

McLaughlin AT. Power-constrained performance optimization of GPU graph traversal. [Internet] [Masters thesis]. Georgia Tech; 2013. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/50209.

Council of Science Editors:

McLaughlin AT. Power-constrained performance optimization of GPU graph traversal. [Masters Thesis]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/50209

18. Laddha, Vishal. Correlation of PDN impedance with jitter and voltage margin in high speed channels.

Degree: MS, Electrical and Computer Engineering, 2008, Georgia Tech

 Jitter and noise on package and printed circuit board interconnects are limiting factors in the performance of high speed digital channels. The simultaneous switching noise… (more)

Subjects/Keywords: PDN impedance; Jitter; Noise margin; Impedance (Electricity); Genetic algorithms

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APA (6th Edition):

Laddha, V. (2008). Correlation of PDN impedance with jitter and voltage margin in high speed channels. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/26521

Chicago Manual of Style (16th Edition):

Laddha, Vishal. “Correlation of PDN impedance with jitter and voltage margin in high speed channels.” 2008. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/26521.

MLA Handbook (7th Edition):

Laddha, Vishal. “Correlation of PDN impedance with jitter and voltage margin in high speed channels.” 2008. Web. 16 Feb 2019.

Vancouver:

Laddha V. Correlation of PDN impedance with jitter and voltage margin in high speed channels. [Internet] [Masters thesis]. Georgia Tech; 2008. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/26521.

Council of Science Editors:

Laddha V. Correlation of PDN impedance with jitter and voltage margin in high speed channels. [Masters Thesis]. Georgia Tech; 2008. Available from: http://hdl.handle.net/1853/26521

19. Sullivan, Owen A. Embedded thermoelectric devices for on-chip cooling and power generation.

Degree: MS, Mechanical Engineering, 2012, Georgia Tech

 Thermoelectric devices are capable of providing both localized active cooling and waste heat power generation. This work will explore the possibility of embedding thermoelectric devices… (more)

Subjects/Keywords: Numerical modelling; Seebeck; Peltier; FLUENT; SPICE; Contact resistance; Load resistance; Thermoelectric materials; Semiconductors; Thermoelectric cooling; Thermoelectricity

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APA (6th Edition):

Sullivan, O. A. (2012). Embedded thermoelectric devices for on-chip cooling and power generation. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/45867

Chicago Manual of Style (16th Edition):

Sullivan, Owen A. “Embedded thermoelectric devices for on-chip cooling and power generation.” 2012. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/45867.

MLA Handbook (7th Edition):

Sullivan, Owen A. “Embedded thermoelectric devices for on-chip cooling and power generation.” 2012. Web. 16 Feb 2019.

Vancouver:

Sullivan OA. Embedded thermoelectric devices for on-chip cooling and power generation. [Internet] [Masters thesis]. Georgia Tech; 2012. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/45867.

Council of Science Editors:

Sullivan OA. Embedded thermoelectric devices for on-chip cooling and power generation. [Masters Thesis]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/45867

20. Zia, Muneeb. SRAM system design for memory based computing.

Degree: MS, Electrical and Computer Engineering, 2013, Georgia Tech

 The objective of the research was to design and test an SRAM system which can meet the performance criteria for Memory Based Computing (MBC). This… (more)

Subjects/Keywords: Look-up table; Asymmetric SRAM; Spatial computing; Temporal computing; Re-configurable computing; Memory based computing; Pulsed read operation; Memory management (Computer science); Random access memory

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zia, M. (2013). SRAM system design for memory based computing. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/47636

Chicago Manual of Style (16th Edition):

Zia, Muneeb. “SRAM system design for memory based computing.” 2013. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/47636.

MLA Handbook (7th Edition):

Zia, Muneeb. “SRAM system design for memory based computing.” 2013. Web. 16 Feb 2019.

Vancouver:

Zia M. SRAM system design for memory based computing. [Internet] [Masters thesis]. Georgia Tech; 2013. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/47636.

Council of Science Editors:

Zia M. SRAM system design for memory based computing. [Masters Thesis]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/47636

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