Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

Language: English

You searched for +publisher:"Georgia Tech" +contributor:("Mukhopadhyay, Saibal"). Showing records 1 – 30 of 57 total matches.

[1] [2]

Search Limiters

Last 2 Years | English Only

Degrees

Levels

▼ Search Limiters

1. Bonhomme, Phillip. Circuit modeling of spintronic devices: a SPICE implementation.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 Every engineer that has worked on designing an integrated circuit has to leverage an under- standing of device physics. Understanding device physics is essential when… (more)

Subjects/Keywords: SPICE; Spintronics; Circuit simulation; Magnetization dynamics; Spintronics; Mathematical models

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bonhomme, P. (2014). Circuit modeling of spintronic devices: a SPICE implementation. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51818

Chicago Manual of Style (16th Edition):

Bonhomme, Phillip. “Circuit modeling of spintronic devices: a SPICE implementation.” 2014. Masters Thesis, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/51818.

MLA Handbook (7th Edition):

Bonhomme, Phillip. “Circuit modeling of spintronic devices: a SPICE implementation.” 2014. Web. 17 Feb 2019.

Vancouver:

Bonhomme P. Circuit modeling of spintronic devices: a SPICE implementation. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/51818.

Council of Science Editors:

Bonhomme P. Circuit modeling of spintronic devices: a SPICE implementation. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51818

2. Ku, Bon Woong Woong. Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node.

Degree: MS, Electrical and Computer Engineering, 2017, Georgia Tech

 The nature of device scaling in the 7nm era is changing from the traditional scheme driven by Moore’s law because of the physical and economic… (more)

Subjects/Keywords: Gate-level; Monolithic 3D IC; PPC tradeoff; 7nm technology node

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ku, B. W. W. (2017). Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58257

Chicago Manual of Style (16th Edition):

Ku, Bon Woong Woong. “Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node.” 2017. Masters Thesis, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/58257.

MLA Handbook (7th Edition):

Ku, Bon Woong Woong. “Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node.” 2017. Web. 17 Feb 2019.

Vancouver:

Ku BWW. Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/58257.

Council of Science Editors:

Ku BWW. Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58257


Georgia Tech

3. Chintaluri, Ashwin K. Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays.

Degree: MS, Electrical and Computer Engineering, 2016, Georgia Tech

 Spin transfer torque magnetic random access memory (STT-MRAM) is a competitive, future memory technology that has gained immense interest in recent years due to its… (more)

Subjects/Keywords: STT-MRAM; Variation; Faults

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chintaluri, A. K. (2016). Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55060

Chicago Manual of Style (16th Edition):

Chintaluri, Ashwin K. “Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays.” 2016. Masters Thesis, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/55060.

MLA Handbook (7th Edition):

Chintaluri, Ashwin K. “Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays.” 2016. Web. 17 Feb 2019.

Vancouver:

Chintaluri AK. Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/55060.

Council of Science Editors:

Chintaluri AK. Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55060


Georgia Tech

4. Carlo, Sergio. Load-Aware Power Conversion and Integration for Heterogeneous Systems.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 In this thesis we develop a holistic co-design approach to optimize the conversion systems in order to perform relevant trade-offs taking into account system-level converter,… (more)

Subjects/Keywords: Power conversion 3D single inductor multiple output SIMO control design power management

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Carlo, S. (2015). Load-Aware Power Conversion and Integration for Heterogeneous Systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56182

Chicago Manual of Style (16th Edition):

Carlo, Sergio. “Load-Aware Power Conversion and Integration for Heterogeneous Systems.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/56182.

MLA Handbook (7th Edition):

Carlo, Sergio. “Load-Aware Power Conversion and Integration for Heterogeneous Systems.” 2015. Web. 17 Feb 2019.

Vancouver:

Carlo S. Load-Aware Power Conversion and Integration for Heterogeneous Systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/56182.

Council of Science Editors:

Carlo S. Load-Aware Power Conversion and Integration for Heterogeneous Systems. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56182


Georgia Tech

5. Yueh, Wen. Modeling, characterization, and control of the electrical-thermal interactions in advanced packages.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The multi-chip integration in an advanced packaging has made the multi-physics interactions increasingly important. The objective of this research is to address the thermal coupling… (more)

Subjects/Keywords: Cooling; VLSI; SRAM; EDRAM; 3D IC; Packaging

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yueh, W. (2015). Modeling, characterization, and control of the electrical-thermal interactions in advanced packages. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56171

Chicago Manual of Style (16th Edition):

Yueh, Wen. “Modeling, characterization, and control of the electrical-thermal interactions in advanced packages.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/56171.

MLA Handbook (7th Edition):

Yueh, Wen. “Modeling, characterization, and control of the electrical-thermal interactions in advanced packages.” 2015. Web. 17 Feb 2019.

Vancouver:

Yueh W. Modeling, characterization, and control of the electrical-thermal interactions in advanced packages. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/56171.

Council of Science Editors:

Yueh W. Modeling, characterization, and control of the electrical-thermal interactions in advanced packages. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56171


Georgia Tech

6. Hassan, Syed Minhaj. Exploiting on-chip memory concurrency in 3d manycore architectures.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The objective of this thesis is to optimize the uncore of 3D many-core architectures. More specifically, we note that technology trends point to large increases… (more)

Subjects/Keywords: 3D memory systems; Network-on-chip; 3D system thermal analysis; Memory-level parallelism; DRAM

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hassan, S. M. (2016). Exploiting on-chip memory concurrency in 3d manycore architectures. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56251

Chicago Manual of Style (16th Edition):

Hassan, Syed Minhaj. “Exploiting on-chip memory concurrency in 3d manycore architectures.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/56251.

MLA Handbook (7th Edition):

Hassan, Syed Minhaj. “Exploiting on-chip memory concurrency in 3d manycore architectures.” 2016. Web. 17 Feb 2019.

Vancouver:

Hassan SM. Exploiting on-chip memory concurrency in 3d manycore architectures. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/56251.

Council of Science Editors:

Hassan SM. Exploiting on-chip memory concurrency in 3d manycore architectures. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56251


Georgia Tech

7. Chakraborty, Partha Sarathi. Design, scaling and reliability of devices for high-performance mixed-signal applications.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 This research investigates and gains new understanding on how silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device design couples with both performance scaling and reliability for… (more)

Subjects/Keywords: Silicon-germanium; Heterojunction bipolar transistor; TCAD; Scaling; Reliability; Device design; Mixed-signal; Simulation; High-frequency; Cryogenic temperature; Characterization

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chakraborty, P. S. (2015). Design, scaling and reliability of devices for high-performance mixed-signal applications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58137

Chicago Manual of Style (16th Edition):

Chakraborty, Partha Sarathi. “Design, scaling and reliability of devices for high-performance mixed-signal applications.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/58137.

MLA Handbook (7th Edition):

Chakraborty, Partha Sarathi. “Design, scaling and reliability of devices for high-performance mixed-signal applications.” 2015. Web. 17 Feb 2019.

Vancouver:

Chakraborty PS. Design, scaling and reliability of devices for high-performance mixed-signal applications. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/58137.

Council of Science Editors:

Chakraborty PS. Design, scaling and reliability of devices for high-performance mixed-signal applications. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/58137


Georgia Tech

8. Wan, Zhimin. Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling.

Degree: PhD, Mechanical Engineering, 2016, Georgia Tech

 Microfluidic convection cooling is a promising technique for future high power microprocessors, radio-frequency (RF) transceivers, solid-state lasers, and light emitting diodes (LED). Three-dimensional (3D) stacking… (more)

Subjects/Keywords: Microfluidic cooling; Pin fin; 3D ICs; Microfabrication; Flow boiling

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wan, Z. (2016). Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55480

Chicago Manual of Style (16th Edition):

Wan, Zhimin. “Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/55480.

MLA Handbook (7th Edition):

Wan, Zhimin. “Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling.” 2016. Web. 17 Feb 2019.

Vancouver:

Wan Z. Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/55480.

Council of Science Editors:

Wan Z. Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55480


Georgia Tech

9. Wunderlich, Richard Bryan. Floating-gate-programmable and reconfigurable, digital and mixed-signal systems.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 This body of work as whole has the theme of using floating-gates and reconfigurable systems to explore and implement non-traditional computing solutions to difficult problems.… (more)

Subjects/Keywords: Floating-gate; Reconfigurable; Digital; Analog processing; Field programmable gate arrays

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wunderlich, R. B. (2014). Floating-gate-programmable and reconfigurable, digital and mixed-signal systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51815

Chicago Manual of Style (16th Edition):

Wunderlich, Richard Bryan. “Floating-gate-programmable and reconfigurable, digital and mixed-signal systems.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/51815.

MLA Handbook (7th Edition):

Wunderlich, Richard Bryan. “Floating-gate-programmable and reconfigurable, digital and mixed-signal systems.” 2014. Web. 17 Feb 2019.

Vancouver:

Wunderlich RB. Floating-gate-programmable and reconfigurable, digital and mixed-signal systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/51815.

Council of Science Editors:

Wunderlich RB. Floating-gate-programmable and reconfigurable, digital and mixed-signal systems. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51815


Georgia Tech

10. Chae, Kwanyeob. Design methodologies for robust low-power digital systems under static and dynamic variations.

Degree: PhD, Electrical and Computer Engineering, 2013, Georgia Tech

 Variability affects the performance and power of a circuit. Along with static variations, dynamic variations, which occur during chip operation, necessitate a safety margin. The… (more)

Subjects/Keywords: Adaptive circuit; Resilient design; Static variation; Dynamic variation; Error prevention

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chae, K. (2013). Design methodologies for robust low-power digital systems under static and dynamic variations. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52174

Chicago Manual of Style (16th Edition):

Chae, Kwanyeob. “Design methodologies for robust low-power digital systems under static and dynamic variations.” 2013. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/52174.

MLA Handbook (7th Edition):

Chae, Kwanyeob. “Design methodologies for robust low-power digital systems under static and dynamic variations.” 2013. Web. 17 Feb 2019.

Vancouver:

Chae K. Design methodologies for robust low-power digital systems under static and dynamic variations. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/52174.

Council of Science Editors:

Chae K. Design methodologies for robust low-power digital systems under static and dynamic variations. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/52174


Georgia Tech

11. Saha, Prabir K. SiGe BiCMOS RF front-ends for adaptive wideband receivers.

Degree: PhD, Electrical and Computer Engineering, 2013, Georgia Tech

 The pursuit of dense monolithic integration and higher operating speed continues to push the integrated circuit (IC) fabrication technologies to their limits. The increasing process… (more)

Subjects/Keywords: Self-healing; Adaptive; Mixer; Image-rejection; RF; LNA; SPDT

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Saha, P. K. (2013). SiGe BiCMOS RF front-ends for adaptive wideband receivers. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52184

Chicago Manual of Style (16th Edition):

Saha, Prabir K. “SiGe BiCMOS RF front-ends for adaptive wideband receivers.” 2013. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/52184.

MLA Handbook (7th Edition):

Saha, Prabir K. “SiGe BiCMOS RF front-ends for adaptive wideband receivers.” 2013. Web. 17 Feb 2019.

Vancouver:

Saha PK. SiGe BiCMOS RF front-ends for adaptive wideband receivers. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/52184.

Council of Science Editors:

Saha PK. SiGe BiCMOS RF front-ends for adaptive wideband receivers. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/52184


Georgia Tech

12. Onyewuchi, Urenna. Managing environmentally stressed aging assets in electric power utilities.

Degree: PhD, Electrical and Computer Engineering, 2012, Georgia Tech

 A model for optimizing the differential cost between a preventive maintenance program and a traditional run-to-failure program on managing assets under uncertainty is developed to… (more)

Subjects/Keywords: Asset management; Environmental stress; Decision making; Electric utility; Aging infrastructure

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Onyewuchi, U. (2012). Managing environmentally stressed aging assets in electric power utilities. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53150

Chicago Manual of Style (16th Edition):

Onyewuchi, Urenna. “Managing environmentally stressed aging assets in electric power utilities.” 2012. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/53150.

MLA Handbook (7th Edition):

Onyewuchi, Urenna. “Managing environmentally stressed aging assets in electric power utilities.” 2012. Web. 17 Feb 2019.

Vancouver:

Onyewuchi U. Managing environmentally stressed aging assets in electric power utilities. [Internet] [Doctoral dissertation]. Georgia Tech; 2012. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/53150.

Council of Science Editors:

Onyewuchi U. Managing environmentally stressed aging assets in electric power utilities. [Doctoral Dissertation]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/53150


Georgia Tech

13. Kumar, Vachan. Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 Modeling approaches are developed to optimize emerging on-chip and off-chip electrical interconnect technologies and benchmark them against conventional technologies. While transistor scaling results in an… (more)

Subjects/Keywords: Interconnect modeling; Graphene nanoribbons; Through silicon via, airgap interconnects

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kumar, V. (2014). Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54280

Chicago Manual of Style (16th Edition):

Kumar, Vachan. “Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/54280.

MLA Handbook (7th Edition):

Kumar, Vachan. “Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies.” 2014. Web. 17 Feb 2019.

Vancouver:

Kumar V. Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/54280.

Council of Science Editors:

Kumar V. Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/54280


Georgia Tech

14. Natarajan, Jayaram. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 One of the challenges faced today in the design of microprocessors is to obtain power, performance scalability and reliability at the same time with technology… (more)

Subjects/Keywords: Microprocessor; Low power; Process variation; Timing variation tolerant; Timing margins; Better than worse-case design; Error resilient pipeline; Reliability

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Natarajan, J. (2016). Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55577

Chicago Manual of Style (16th Edition):

Natarajan, Jayaram. “Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/55577.

MLA Handbook (7th Edition):

Natarajan, Jayaram. “Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.” 2016. Web. 17 Feb 2019.

Vancouver:

Natarajan J. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/55577.

Council of Science Editors:

Natarajan J. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55577


Georgia Tech

15. Song, Taigon. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The objective of this research is to study and develop computer-aided-design (CAD) methodologies for reliability in chip-package co-designed three-dimensional integrated circuit (3D IC) systems. 3D… (more)

Subjects/Keywords: 3D IC; Design Methodologies

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Song, T. (2015). CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56188

Chicago Manual of Style (16th Edition):

Song, Taigon. “CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/56188.

MLA Handbook (7th Edition):

Song, Taigon. “CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.” 2015. Web. 17 Feb 2019.

Vancouver:

Song T. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/56188.

Council of Science Editors:

Song T. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56188


Georgia Tech

16. Peng, Yarui. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 As one of more-than-Moore technologies, 3D ICs enable next-generation systems with much higher device density without needs for technology scaling. However, designing reliable 3D IC… (more)

Subjects/Keywords: 3D IC; CAD; Methodology; Reliable; Power integrity; Signal integrity

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Peng, Y. (2016). CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56330

Chicago Manual of Style (16th Edition):

Peng, Yarui. “CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/56330.

MLA Handbook (7th Edition):

Peng, Yarui. “CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.” 2016. Web. 17 Feb 2019.

Vancouver:

Peng Y. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/56330.

Council of Science Editors:

Peng Y. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56330


Georgia Tech

17. Zhang, Yang. Thermal and power delivery network modeling for emerging microelectronic integration platforms.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 In this dissertation, thermal management and power delivery challenges in 2.5-D and 3-D integration are presented. To address the thermal coupling issues in heterogeneous 3-D… (more)

Subjects/Keywords: 3D-IC, 2.5-D IC, Thermal, Power delivery, Signaling; 2.5-D IC; Thermal; Power delivery; Signaling

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhang, Y. (2017). Thermal and power delivery network modeling for emerging microelectronic integration platforms. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59199

Chicago Manual of Style (16th Edition):

Zhang, Yang. “Thermal and power delivery network modeling for emerging microelectronic integration platforms.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/59199.

MLA Handbook (7th Edition):

Zhang, Yang. “Thermal and power delivery network modeling for emerging microelectronic integration platforms.” 2017. Web. 17 Feb 2019.

Vancouver:

Zhang Y. Thermal and power delivery network modeling for emerging microelectronic integration platforms. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/59199.

Council of Science Editors:

Zhang Y. Thermal and power delivery network modeling for emerging microelectronic integration platforms. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59199


Georgia Tech

18. Kim, Duckhwan. NEUROCUBE: ENERGY-EFFICIENT PROGRAMMABLE DIGITAL DEEP LEARNING ACCELERATOR BASED ON PROCESSOR IN MEMORY PLATFORM.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 Deep learning, machine learning algorithm based on artificial neural network, shows great success in numerous pattern recognition problems, such as image recognition or speech recognition.… (more)

Subjects/Keywords: deep learning; deep learning accelerator; processor in memory; near memory process

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, D. (2017). NEUROCUBE: ENERGY-EFFICIENT PROGRAMMABLE DIGITAL DEEP LEARNING ACCELERATOR BASED ON PROCESSOR IN MEMORY PLATFORM. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60660

Chicago Manual of Style (16th Edition):

Kim, Duckhwan. “NEUROCUBE: ENERGY-EFFICIENT PROGRAMMABLE DIGITAL DEEP LEARNING ACCELERATOR BASED ON PROCESSOR IN MEMORY PLATFORM.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/60660.

MLA Handbook (7th Edition):

Kim, Duckhwan. “NEUROCUBE: ENERGY-EFFICIENT PROGRAMMABLE DIGITAL DEEP LEARNING ACCELERATOR BASED ON PROCESSOR IN MEMORY PLATFORM.” 2017. Web. 17 Feb 2019.

Vancouver:

Kim D. NEUROCUBE: ENERGY-EFFICIENT PROGRAMMABLE DIGITAL DEEP LEARNING ACCELERATOR BASED ON PROCESSOR IN MEMORY PLATFORM. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/60660.

Council of Science Editors:

Kim D. NEUROCUBE: ENERGY-EFFICIENT PROGRAMMABLE DIGITAL DEEP LEARNING ACCELERATOR BASED ON PROCESSOR IN MEMORY PLATFORM. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/60660


Georgia Tech

19. Wang, Cheng-Yin. Organic field-effect transistors on novel renewable substrates.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 With the increasing awareness of environmental impact from electronic waste and increasing demand for flexible electronic devices, novel substrates with both biodegradability and flexibility have… (more)

Subjects/Keywords: Organic field-effect transistors; Novel renewable substrates; Top-gate geometry; CNC; Reliability; Stability; Nanolaminate; Flexible; Paper

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, C. (2016). Organic field-effect transistors on novel renewable substrates. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59137

Chicago Manual of Style (16th Edition):

Wang, Cheng-Yin. “Organic field-effect transistors on novel renewable substrates.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/59137.

MLA Handbook (7th Edition):

Wang, Cheng-Yin. “Organic field-effect transistors on novel renewable substrates.” 2016. Web. 17 Feb 2019.

Vancouver:

Wang C. Organic field-effect transistors on novel renewable substrates. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/59137.

Council of Science Editors:

Wang C. Organic field-effect transistors on novel renewable substrates. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/59137


Georgia Tech

20. Rao, Karthik. Coordinated management of the processor and memory for optimizing energy efficiency.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 Energy efficiency is a key design goal for future computing systems. With diverse components interacting with each other on the System-on-Chip (SoC), dynamically managing performance,… (more)

Subjects/Keywords: Feedback control; Optimization; Adaptive control; 3D stacked architecture; Thermal management; Energy efficiency; Android

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rao, K. (2018). Coordinated management of the processor and memory for optimizing energy efficiency. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60234

Chicago Manual of Style (16th Edition):

Rao, Karthik. “Coordinated management of the processor and memory for optimizing energy efficiency.” 2018. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/60234.

MLA Handbook (7th Edition):

Rao, Karthik. “Coordinated management of the processor and memory for optimizing energy efficiency.” 2018. Web. 17 Feb 2019.

Vancouver:

Rao K. Coordinated management of the processor and memory for optimizing energy efficiency. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/60234.

Council of Science Editors:

Rao K. Coordinated management of the processor and memory for optimizing energy efficiency. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60234


Georgia Tech

21. Kar, Monodeep. Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 The energy-efficiency and security needs in computing systems, ranging from high performance processors to low-power devices are steadily increasing. State-of-the-art digital systems use dedicated encryption… (more)

Subjects/Keywords: Side channel attack; Power attack; Differential power analysis; DPA; Correlation power analysis; CPA; Differential electromagnetic analysis; DEMA; Test vector leakage assessment; TVLA; Integrated voltage regulators; IVR; Voltage regulation; Haswell; FIVR; Security guard extension; SGX; DC-DC converters; Buck regulators; IoT; Countermeasures; Advanced encryption standard; AES; AES-NI; Randomization; Security; Masking countermeasure; Dual rail logic

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kar, M. (2017). Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59182

Chicago Manual of Style (16th Edition):

Kar, Monodeep. “Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/59182.

MLA Handbook (7th Edition):

Kar, Monodeep. “Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines.” 2017. Web. 17 Feb 2019.

Vancouver:

Kar M. Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/59182.

Council of Science Editors:

Kar M. Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59182


Georgia Tech

22. Xiao, He. A Multi-physics approach to the co-design of 3D multi-core processors.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The three-dimensional integrated circuit (3D IC) is a promising solution for processors in the post-Moore era. The 3D integration stacks multiple dies vertically in a… (more)

Subjects/Keywords: Performance; Energy efficiency; 3D IC; Multi-core systems; Multi-physics analysis; Microarchitecture co-design

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xiao, H. (2018). A Multi-physics approach to the co-design of 3D multi-core processors. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59810

Chicago Manual of Style (16th Edition):

Xiao, He. “A Multi-physics approach to the co-design of 3D multi-core processors.” 2018. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/59810.

MLA Handbook (7th Edition):

Xiao, He. “A Multi-physics approach to the co-design of 3D multi-core processors.” 2018. Web. 17 Feb 2019.

Vancouver:

Xiao H. A Multi-physics approach to the co-design of 3D multi-core processors. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/59810.

Council of Science Editors:

Xiao H. A Multi-physics approach to the co-design of 3D multi-core processors. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59810


Georgia Tech

23. Kim, Sihwan. Low power mixed signal system design environment using floating-gate FPAAs.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The objective of this research is to create a low-power mixed-signal system design environment using FG FPAAs. To achieve this, my research focused on implementing… (more)

Subjects/Keywords: Floating-gate; FG; Field programmable analog array (FPAA)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, S. (2018). Low power mixed signal system design environment using floating-gate FPAAs. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59923

Chicago Manual of Style (16th Edition):

Kim, Sihwan. “Low power mixed signal system design environment using floating-gate FPAAs.” 2018. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/59923.

MLA Handbook (7th Edition):

Kim, Sihwan. “Low power mixed signal system design environment using floating-gate FPAAs.” 2018. Web. 17 Feb 2019.

Vancouver:

Kim S. Low power mixed signal system design environment using floating-gate FPAAs. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/59923.

Council of Science Editors:

Kim S. Low power mixed signal system design environment using floating-gate FPAAs. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59923


Georgia Tech

24. Pardue, Colin Andrew. Wireless power transfer using integrated and emerging technologies.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 To support the next generation of compact low power devices, a wireless power transfer solution needs to have an improved combination of receiver coil area… (more)

Subjects/Keywords: Wireless power transfer; Internet of things; Integrated inductor; Packaging; Rf near field coupling; Power integrity

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pardue, C. A. (2018). Wireless power transfer using integrated and emerging technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60216

Chicago Manual of Style (16th Edition):

Pardue, Colin Andrew. “Wireless power transfer using integrated and emerging technologies.” 2018. Doctoral Dissertation, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/60216.

MLA Handbook (7th Edition):

Pardue, Colin Andrew. “Wireless power transfer using integrated and emerging technologies.” 2018. Web. 17 Feb 2019.

Vancouver:

Pardue CA. Wireless power transfer using integrated and emerging technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/60216.

Council of Science Editors:

Pardue CA. Wireless power transfer using integrated and emerging technologies. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60216

25. Lohith, Penmetsa Neela. Monolithic 3D integration of asynchronous systems.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 The goal of this thesis is to study the impact of 3D integration on asynchronous circuits and explore the benefits in power, performance and area… (more)

Subjects/Keywords: Asynchronous; 3DIC; Monolithic

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lohith, P. N. (2014). Monolithic 3D integration of asynchronous systems. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53113

Chicago Manual of Style (16th Edition):

Lohith, Penmetsa Neela. “Monolithic 3D integration of asynchronous systems.” 2014. Masters Thesis, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/53113.

MLA Handbook (7th Edition):

Lohith, Penmetsa Neela. “Monolithic 3D integration of asynchronous systems.” 2014. Web. 17 Feb 2019.

Vancouver:

Lohith PN. Monolithic 3D integration of asynchronous systems. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/53113.

Council of Science Editors:

Lohith PN. Monolithic 3D integration of asynchronous systems. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/53113

26. Samal, Kruttidipta. FPGA acceleration of CNN training.

Degree: MS, Electrical and Computer Engineering, 2015, Georgia Tech

 This thesis presents the results of an architectural study on the design of FPGA- based architectures for convolutional neural networks (CNNs). We have analyzed the… (more)

Subjects/Keywords: CNN; FPGA; Deep learning

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Samal, K. (2015). FPGA acceleration of CNN training. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54467

Chicago Manual of Style (16th Edition):

Samal, Kruttidipta. “FPGA acceleration of CNN training.” 2015. Masters Thesis, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/54467.

MLA Handbook (7th Edition):

Samal, Kruttidipta. “FPGA acceleration of CNN training.” 2015. Web. 17 Feb 2019.

Vancouver:

Samal K. FPGA acceleration of CNN training. [Internet] [Masters thesis]. Georgia Tech; 2015. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/54467.

Council of Science Editors:

Samal K. FPGA acceleration of CNN training. [Masters Thesis]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/54467

27. Subramanian, Ashwin Srinath. Enhancing microprocessor power efficiency through clock-data compensation.

Degree: MS, Electrical and Computer Engineering, 2015, Georgia Tech

 The Smartphone revolution and the Internet of Things (IoTs) have triggered rapid advances in complex system-on-chips (SoCs) that increasing provide more functionality within a tight… (more)

Subjects/Keywords: Power management; Adaptive Clocking; Clock-data compensation; Power efficiency

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Subramanian, A. S. (2015). Enhancing microprocessor power efficiency through clock-data compensation. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54471

Chicago Manual of Style (16th Edition):

Subramanian, Ashwin Srinath. “Enhancing microprocessor power efficiency through clock-data compensation.” 2015. Masters Thesis, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/54471.

MLA Handbook (7th Edition):

Subramanian, Ashwin Srinath. “Enhancing microprocessor power efficiency through clock-data compensation.” 2015. Web. 17 Feb 2019.

Vancouver:

Subramanian AS. Enhancing microprocessor power efficiency through clock-data compensation. [Internet] [Masters thesis]. Georgia Tech; 2015. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/54471.

Council of Science Editors:

Subramanian AS. Enhancing microprocessor power efficiency through clock-data compensation. [Masters Thesis]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/54471

28. Ahmed, Khondker Zakir. Low voltage autonomous buck-boost regulator for wide input energy harvesting.

Degree: MS, Electrical and Computer Engineering, 2015, Georgia Tech

 While high power buck-boost regulators have been extensively researched and developed in the academia and industry, low power counterparts have only recently gained momentum due… (more)

Subjects/Keywords: Buck-boost regulator; |Low voltage energy harvesting; Low current regulator; nA bias current regulator

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ahmed, K. Z. (2015). Low voltage autonomous buck-boost regulator for wide input energy harvesting. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53604

Chicago Manual of Style (16th Edition):

Ahmed, Khondker Zakir. “Low voltage autonomous buck-boost regulator for wide input energy harvesting.” 2015. Masters Thesis, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/53604.

MLA Handbook (7th Edition):

Ahmed, Khondker Zakir. “Low voltage autonomous buck-boost regulator for wide input energy harvesting.” 2015. Web. 17 Feb 2019.

Vancouver:

Ahmed KZ. Low voltage autonomous buck-boost regulator for wide input energy harvesting. [Internet] [Masters thesis]. Georgia Tech; 2015. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/53604.

Council of Science Editors:

Ahmed KZ. Low voltage autonomous buck-boost regulator for wide input energy harvesting. [Masters Thesis]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53604

29. Mudassar, Burhan Ahmad. Design and implementation of a content aware image processing module on FPGA.

Degree: MS, Electrical and Computer Engineering, 2015, Georgia Tech

 In this thesis, we tackle the problem of designing and implementing a wireless video sensor network for a surveillance application. The goal was to design… (more)

Subjects/Keywords: Content aware; Image processing; Edge detection; Image preprocessing; Low power; FPGA

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mudassar, B. A. (2015). Design and implementation of a content aware image processing module on FPGA. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53618

Chicago Manual of Style (16th Edition):

Mudassar, Burhan Ahmad. “Design and implementation of a content aware image processing module on FPGA.” 2015. Masters Thesis, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/53618.

MLA Handbook (7th Edition):

Mudassar, Burhan Ahmad. “Design and implementation of a content aware image processing module on FPGA.” 2015. Web. 17 Feb 2019.

Vancouver:

Mudassar BA. Design and implementation of a content aware image processing module on FPGA. [Internet] [Masters thesis]. Georgia Tech; 2015. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/53618.

Council of Science Editors:

Mudassar BA. Design and implementation of a content aware image processing module on FPGA. [Masters Thesis]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53618

30. Magudilu Vijayaraj, Thejasvi Magudilu. An empirical power model of a low power mobile platform.

Degree: MS, Electrical and Computer Engineering, 2013, Georgia Tech

 Power is one of the today’s major constraints for both hardware and software design. Thus the need to understand the statistics and distribution of power… (more)

Subjects/Keywords: Empirical power model; OMAP4460; Pandaboard; Power electronics; Energy consumption

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Magudilu Vijayaraj, T. M. (2013). An empirical power model of a low power mobile platform. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/49054

Chicago Manual of Style (16th Edition):

Magudilu Vijayaraj, Thejasvi Magudilu. “An empirical power model of a low power mobile platform.” 2013. Masters Thesis, Georgia Tech. Accessed February 17, 2019. http://hdl.handle.net/1853/49054.

MLA Handbook (7th Edition):

Magudilu Vijayaraj, Thejasvi Magudilu. “An empirical power model of a low power mobile platform.” 2013. Web. 17 Feb 2019.

Vancouver:

Magudilu Vijayaraj TM. An empirical power model of a low power mobile platform. [Internet] [Masters thesis]. Georgia Tech; 2013. [cited 2019 Feb 17]. Available from: http://hdl.handle.net/1853/49054.

Council of Science Editors:

Magudilu Vijayaraj TM. An empirical power model of a low power mobile platform. [Masters Thesis]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/49054

[1] [2]

.