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You searched for +publisher:"Georgia Tech" +contributor:("Mukhopadhyay, Saibal"). Showing records 1 – 30 of 68 total matches.

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Georgia Tech

1. Carlo, Sergio. Load-Aware Power Conversion and Integration for Heterogeneous Systems.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 In this thesis we develop a holistic co-design approach to optimize the conversion systems in order to perform relevant trade-offs taking into account system-level converter,… (more)

Subjects/Keywords: Power conversion 3D single inductor multiple output SIMO control design power management

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APA (6th Edition):

Carlo, S. (2015). Load-Aware Power Conversion and Integration for Heterogeneous Systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56182

Chicago Manual of Style (16th Edition):

Carlo, Sergio. “Load-Aware Power Conversion and Integration for Heterogeneous Systems.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/56182.

MLA Handbook (7th Edition):

Carlo, Sergio. “Load-Aware Power Conversion and Integration for Heterogeneous Systems.” 2015. Web. 21 Feb 2019.

Vancouver:

Carlo S. Load-Aware Power Conversion and Integration for Heterogeneous Systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/56182.

Council of Science Editors:

Carlo S. Load-Aware Power Conversion and Integration for Heterogeneous Systems. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56182


Georgia Tech

2. Yueh, Wen. Modeling, characterization, and control of the electrical-thermal interactions in advanced packages.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The multi-chip integration in an advanced packaging has made the multi-physics interactions increasingly important. The objective of this research is to address the thermal coupling… (more)

Subjects/Keywords: Cooling; VLSI; SRAM; EDRAM; 3D IC; Packaging

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APA (6th Edition):

Yueh, W. (2015). Modeling, characterization, and control of the electrical-thermal interactions in advanced packages. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56171

Chicago Manual of Style (16th Edition):

Yueh, Wen. “Modeling, characterization, and control of the electrical-thermal interactions in advanced packages.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/56171.

MLA Handbook (7th Edition):

Yueh, Wen. “Modeling, characterization, and control of the electrical-thermal interactions in advanced packages.” 2015. Web. 21 Feb 2019.

Vancouver:

Yueh W. Modeling, characterization, and control of the electrical-thermal interactions in advanced packages. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/56171.

Council of Science Editors:

Yueh W. Modeling, characterization, and control of the electrical-thermal interactions in advanced packages. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56171


Georgia Tech

3. Hassan, Syed Minhaj. Exploiting on-chip memory concurrency in 3d manycore architectures.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The objective of this thesis is to optimize the uncore of 3D many-core architectures. More specifically, we note that technology trends point to large increases… (more)

Subjects/Keywords: 3D memory systems; Network-on-chip; 3D system thermal analysis; Memory-level parallelism; DRAM

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APA (6th Edition):

Hassan, S. M. (2016). Exploiting on-chip memory concurrency in 3d manycore architectures. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56251

Chicago Manual of Style (16th Edition):

Hassan, Syed Minhaj. “Exploiting on-chip memory concurrency in 3d manycore architectures.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/56251.

MLA Handbook (7th Edition):

Hassan, Syed Minhaj. “Exploiting on-chip memory concurrency in 3d manycore architectures.” 2016. Web. 21 Feb 2019.

Vancouver:

Hassan SM. Exploiting on-chip memory concurrency in 3d manycore architectures. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/56251.

Council of Science Editors:

Hassan SM. Exploiting on-chip memory concurrency in 3d manycore architectures. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56251


Georgia Tech

4. Chakraborty, Partha Sarathi. Design, scaling and reliability of devices for high-performance mixed-signal applications.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 This research investigates and gains new understanding on how silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device design couples with both performance scaling and reliability for… (more)

Subjects/Keywords: Silicon-germanium; Heterojunction bipolar transistor; TCAD; Scaling; Reliability; Device design; Mixed-signal; Simulation; High-frequency; Cryogenic temperature; Characterization

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APA (6th Edition):

Chakraborty, P. S. (2015). Design, scaling and reliability of devices for high-performance mixed-signal applications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58137

Chicago Manual of Style (16th Edition):

Chakraborty, Partha Sarathi. “Design, scaling and reliability of devices for high-performance mixed-signal applications.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/58137.

MLA Handbook (7th Edition):

Chakraborty, Partha Sarathi. “Design, scaling and reliability of devices for high-performance mixed-signal applications.” 2015. Web. 21 Feb 2019.

Vancouver:

Chakraborty PS. Design, scaling and reliability of devices for high-performance mixed-signal applications. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/58137.

Council of Science Editors:

Chakraborty PS. Design, scaling and reliability of devices for high-performance mixed-signal applications. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/58137


Georgia Tech

5. Wan, Zhimin. Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling.

Degree: PhD, Mechanical Engineering, 2016, Georgia Tech

 Microfluidic convection cooling is a promising technique for future high power microprocessors, radio-frequency (RF) transceivers, solid-state lasers, and light emitting diodes (LED). Three-dimensional (3D) stacking… (more)

Subjects/Keywords: Microfluidic cooling; Pin fin; 3D ICs; Microfabrication; Flow boiling

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APA (6th Edition):

Wan, Z. (2016). Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55480

Chicago Manual of Style (16th Edition):

Wan, Zhimin. “Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/55480.

MLA Handbook (7th Edition):

Wan, Zhimin. “Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling.” 2016. Web. 21 Feb 2019.

Vancouver:

Wan Z. Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/55480.

Council of Science Editors:

Wan Z. Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55480


Georgia Tech

6. Wunderlich, Richard Bryan. Floating-gate-programmable and reconfigurable, digital and mixed-signal systems.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 This body of work as whole has the theme of using floating-gates and reconfigurable systems to explore and implement non-traditional computing solutions to difficult problems.… (more)

Subjects/Keywords: Floating-gate; Reconfigurable; Digital; Analog processing; Field programmable gate arrays

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APA (6th Edition):

Wunderlich, R. B. (2014). Floating-gate-programmable and reconfigurable, digital and mixed-signal systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51815

Chicago Manual of Style (16th Edition):

Wunderlich, Richard Bryan. “Floating-gate-programmable and reconfigurable, digital and mixed-signal systems.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/51815.

MLA Handbook (7th Edition):

Wunderlich, Richard Bryan. “Floating-gate-programmable and reconfigurable, digital and mixed-signal systems.” 2014. Web. 21 Feb 2019.

Vancouver:

Wunderlich RB. Floating-gate-programmable and reconfigurable, digital and mixed-signal systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/51815.

Council of Science Editors:

Wunderlich RB. Floating-gate-programmable and reconfigurable, digital and mixed-signal systems. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51815


Georgia Tech

7. Chae, Kwanyeob. Design methodologies for robust low-power digital systems under static and dynamic variations.

Degree: PhD, Electrical and Computer Engineering, 2013, Georgia Tech

 Variability affects the performance and power of a circuit. Along with static variations, dynamic variations, which occur during chip operation, necessitate a safety margin. The… (more)

Subjects/Keywords: Adaptive circuit; Resilient design; Static variation; Dynamic variation; Error prevention

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APA (6th Edition):

Chae, K. (2013). Design methodologies for robust low-power digital systems under static and dynamic variations. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52174

Chicago Manual of Style (16th Edition):

Chae, Kwanyeob. “Design methodologies for robust low-power digital systems under static and dynamic variations.” 2013. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/52174.

MLA Handbook (7th Edition):

Chae, Kwanyeob. “Design methodologies for robust low-power digital systems under static and dynamic variations.” 2013. Web. 21 Feb 2019.

Vancouver:

Chae K. Design methodologies for robust low-power digital systems under static and dynamic variations. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/52174.

Council of Science Editors:

Chae K. Design methodologies for robust low-power digital systems under static and dynamic variations. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/52174


Georgia Tech

8. Saha, Prabir K. SiGe BiCMOS RF front-ends for adaptive wideband receivers.

Degree: PhD, Electrical and Computer Engineering, 2013, Georgia Tech

 The pursuit of dense monolithic integration and higher operating speed continues to push the integrated circuit (IC) fabrication technologies to their limits. The increasing process… (more)

Subjects/Keywords: Self-healing; Adaptive; Mixer; Image-rejection; RF; LNA; SPDT

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APA (6th Edition):

Saha, P. K. (2013). SiGe BiCMOS RF front-ends for adaptive wideband receivers. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52184

Chicago Manual of Style (16th Edition):

Saha, Prabir K. “SiGe BiCMOS RF front-ends for adaptive wideband receivers.” 2013. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/52184.

MLA Handbook (7th Edition):

Saha, Prabir K. “SiGe BiCMOS RF front-ends for adaptive wideband receivers.” 2013. Web. 21 Feb 2019.

Vancouver:

Saha PK. SiGe BiCMOS RF front-ends for adaptive wideband receivers. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/52184.

Council of Science Editors:

Saha PK. SiGe BiCMOS RF front-ends for adaptive wideband receivers. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/52184


Georgia Tech

9. Onyewuchi, Urenna. Managing environmentally stressed aging assets in electric power utilities.

Degree: PhD, Electrical and Computer Engineering, 2012, Georgia Tech

 A model for optimizing the differential cost between a preventive maintenance program and a traditional run-to-failure program on managing assets under uncertainty is developed to… (more)

Subjects/Keywords: Asset management; Environmental stress; Decision making; Electric utility; Aging infrastructure

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APA (6th Edition):

Onyewuchi, U. (2012). Managing environmentally stressed aging assets in electric power utilities. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53150

Chicago Manual of Style (16th Edition):

Onyewuchi, Urenna. “Managing environmentally stressed aging assets in electric power utilities.” 2012. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/53150.

MLA Handbook (7th Edition):

Onyewuchi, Urenna. “Managing environmentally stressed aging assets in electric power utilities.” 2012. Web. 21 Feb 2019.

Vancouver:

Onyewuchi U. Managing environmentally stressed aging assets in electric power utilities. [Internet] [Doctoral dissertation]. Georgia Tech; 2012. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/53150.

Council of Science Editors:

Onyewuchi U. Managing environmentally stressed aging assets in electric power utilities. [Doctoral Dissertation]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/53150


Georgia Tech

10. Wu, Jiadong. Improving the throughput of novel cluster computing systems.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 Traditional cluster computing systems such as the supercomputers are equipped with specially designed high-performance hardware, which escalates the manufacturing cost and the energy cost of… (more)

Subjects/Keywords: GPU; Hadoop; Computer cluster; Parallel computing

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APA (6th Edition):

Wu, J. (2015). Improving the throughput of novel cluster computing systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53890

Chicago Manual of Style (16th Edition):

Wu, Jiadong. “Improving the throughput of novel cluster computing systems.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/53890.

MLA Handbook (7th Edition):

Wu, Jiadong. “Improving the throughput of novel cluster computing systems.” 2015. Web. 21 Feb 2019.

Vancouver:

Wu J. Improving the throughput of novel cluster computing systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/53890.

Council of Science Editors:

Wu J. Improving the throughput of novel cluster computing systems. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53890


Georgia Tech

11. Adil, Farhan. Applications of floating-gate based programmable mixed-signal reconfigurable systems.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 A mixed-signal reconfigurable platform gives the designer the choice of implementing systems using the benefits of both analog and digital circuits. The subject of this… (more)

Subjects/Keywords: FPAA; Mixed-signal IC; Reconfigurable systems

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APA (6th Edition):

Adil, F. (2014). Applications of floating-gate based programmable mixed-signal reconfigurable systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54272

Chicago Manual of Style (16th Edition):

Adil, Farhan. “Applications of floating-gate based programmable mixed-signal reconfigurable systems.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/54272.

MLA Handbook (7th Edition):

Adil, Farhan. “Applications of floating-gate based programmable mixed-signal reconfigurable systems.” 2014. Web. 21 Feb 2019.

Vancouver:

Adil F. Applications of floating-gate based programmable mixed-signal reconfigurable systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/54272.

Council of Science Editors:

Adil F. Applications of floating-gate based programmable mixed-signal reconfigurable systems. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/54272


Georgia Tech

12. Kumar, Vachan. Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 Modeling approaches are developed to optimize emerging on-chip and off-chip electrical interconnect technologies and benchmark them against conventional technologies. While transistor scaling results in an… (more)

Subjects/Keywords: Interconnect modeling; Graphene nanoribbons; Through silicon via, airgap interconnects

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APA (6th Edition):

Kumar, V. (2014). Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54280

Chicago Manual of Style (16th Edition):

Kumar, Vachan. “Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/54280.

MLA Handbook (7th Edition):

Kumar, Vachan. “Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies.” 2014. Web. 21 Feb 2019.

Vancouver:

Kumar V. Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/54280.

Council of Science Editors:

Kumar V. Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/54280


Georgia Tech

13. Natarajan, Jayaram. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 One of the challenges faced today in the design of microprocessors is to obtain power, performance scalability and reliability at the same time with technology… (more)

Subjects/Keywords: Microprocessor; Low power; Process variation; Timing variation tolerant; Timing margins; Better than worse-case design; Error resilient pipeline; Reliability

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APA (6th Edition):

Natarajan, J. (2016). Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55577

Chicago Manual of Style (16th Edition):

Natarajan, Jayaram. “Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/55577.

MLA Handbook (7th Edition):

Natarajan, Jayaram. “Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.” 2016. Web. 21 Feb 2019.

Vancouver:

Natarajan J. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/55577.

Council of Science Editors:

Natarajan J. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55577


Georgia Tech

14. Song, Taigon. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The objective of this research is to study and develop computer-aided-design (CAD) methodologies for reliability in chip-package co-designed three-dimensional integrated circuit (3D IC) systems. 3D… (more)

Subjects/Keywords: 3D IC; Design Methodologies

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APA (6th Edition):

Song, T. (2015). CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56188

Chicago Manual of Style (16th Edition):

Song, Taigon. “CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/56188.

MLA Handbook (7th Edition):

Song, Taigon. “CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.” 2015. Web. 21 Feb 2019.

Vancouver:

Song T. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/56188.

Council of Science Editors:

Song T. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56188


Georgia Tech

15. Peng, Yarui. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 As one of more-than-Moore technologies, 3D ICs enable next-generation systems with much higher device density without needs for technology scaling. However, designing reliable 3D IC… (more)

Subjects/Keywords: 3D IC; CAD; Methodology; Reliable; Power integrity; Signal integrity

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APA (6th Edition):

Peng, Y. (2016). CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56330

Chicago Manual of Style (16th Edition):

Peng, Yarui. “CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/56330.

MLA Handbook (7th Edition):

Peng, Yarui. “CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.” 2016. Web. 21 Feb 2019.

Vancouver:

Peng Y. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/56330.

Council of Science Editors:

Peng Y. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56330


Georgia Tech

16. Ghosh, Mrinmoy. Microarchitectural techniques to reduce energy consumption in the memory hierarchy.

Degree: PhD, Electrical and Computer Engineering, 2009, Georgia Tech

 This thesis states that dynamic profiling of the memory reference stream can improve energy and performance in the memory hierarchy. The research presented in this… (more)

Subjects/Keywords: Energy; Cache; Dram; Microarchitecture; Memory management (Computer science) Power supply; Computer architecture

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APA (6th Edition):

Ghosh, M. (2009). Microarchitectural techniques to reduce energy consumption in the memory hierarchy. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/28265

Chicago Manual of Style (16th Edition):

Ghosh, Mrinmoy. “Microarchitectural techniques to reduce energy consumption in the memory hierarchy.” 2009. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/28265.

MLA Handbook (7th Edition):

Ghosh, Mrinmoy. “Microarchitectural techniques to reduce energy consumption in the memory hierarchy.” 2009. Web. 21 Feb 2019.

Vancouver:

Ghosh M. Microarchitectural techniques to reduce energy consumption in the memory hierarchy. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/28265.

Council of Science Editors:

Ghosh M. Microarchitectural techniques to reduce energy consumption in the memory hierarchy. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/28265


Georgia Tech

17. Song, Tae Joong. A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing.

Degree: PhD, Electrical and Computer Engineering, 2010, Georgia Tech

 This dissertation focuses on design and implementation of a fully-integrated SRAM-based arbitrary waveform generator for analog signal processing applications in a CMOS technology. The dissertation… (more)

Subjects/Keywords: Digital circuit; Spectrum sensing; SRAM; Arbitrary waveform generator; Analog signal processing; Low-power; MRSS; Metal oxide semiconductors, Complementary; Signal processing; Random access memory

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APA (6th Edition):

Song, T. J. (2010). A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/34760

Chicago Manual of Style (16th Edition):

Song, Tae Joong. “A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing.” 2010. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/34760.

MLA Handbook (7th Edition):

Song, Tae Joong. “A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing.” 2010. Web. 21 Feb 2019.

Vancouver:

Song TJ. A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing. [Internet] [Doctoral dissertation]. Georgia Tech; 2010. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/34760.

Council of Science Editors:

Song TJ. A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing. [Doctoral Dissertation]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/34760


Georgia Tech

18. Kim, Hyungwook. CMOS radio-frequency power amplifiers for multi-standard wireless communications.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 The development of multi-standard wireless communication systems with low cost and high integration is continuously requested and accompanied by the explosive growth of the wireless… (more)

Subjects/Keywords: CMOS; Power amplifier; RF PA; Multi-standard wireless communications; Wireless communication systems; Power amplifiers; Metal oxide semiconductors, Complementary; Radio Transmitter-receivers

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APA (6th Edition):

Kim, H. (2011). CMOS radio-frequency power amplifiers for multi-standard wireless communications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/44786

Chicago Manual of Style (16th Edition):

Kim, Hyungwook. “CMOS radio-frequency power amplifiers for multi-standard wireless communications.” 2011. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/44786.

MLA Handbook (7th Edition):

Kim, Hyungwook. “CMOS radio-frequency power amplifiers for multi-standard wireless communications.” 2011. Web. 21 Feb 2019.

Vancouver:

Kim H. CMOS radio-frequency power amplifiers for multi-standard wireless communications. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/44786.

Council of Science Editors:

Kim H. CMOS radio-frequency power amplifiers for multi-standard wireless communications. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/44786


Georgia Tech

19. Barale, Francesco. Design of integrated frequency synthesizers and clock-data recovery for 60 GHz wireless communications.

Degree: PhD, Electrical and Computer Engineering, 2010, Georgia Tech

 In this dissertation, the development of the first 60 GHz-standard compatible fully integrated 4-channel phase-locked loop (PLL) frequency synthesizer has been presented. The frequency synthesizer… (more)

Subjects/Keywords: CMOS; VCO; Frequency dividers; Clock-data recovery; Phase-locked loops; Frequency synthesizers; Wireless communication systems; Radio Transmitter-receivers; Metal oxide semiconductors, Complementary

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APA (6th Edition):

Barale, F. (2010). Design of integrated frequency synthesizers and clock-data recovery for 60 GHz wireless communications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/37216

Chicago Manual of Style (16th Edition):

Barale, Francesco. “Design of integrated frequency synthesizers and clock-data recovery for 60 GHz wireless communications.” 2010. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/37216.

MLA Handbook (7th Edition):

Barale, Francesco. “Design of integrated frequency synthesizers and clock-data recovery for 60 GHz wireless communications.” 2010. Web. 21 Feb 2019.

Vancouver:

Barale F. Design of integrated frequency synthesizers and clock-data recovery for 60 GHz wireless communications. [Internet] [Doctoral dissertation]. Georgia Tech; 2010. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/37216.

Council of Science Editors:

Barale F. Design of integrated frequency synthesizers and clock-data recovery for 60 GHz wireless communications. [Doctoral Dissertation]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/37216


Georgia Tech

20. Zhang, Yang. Thermal and power delivery network modeling for emerging microelectronic integration platforms.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 In this dissertation, thermal management and power delivery challenges in 2.5-D and 3-D integration are presented. To address the thermal coupling issues in heterogeneous 3-D… (more)

Subjects/Keywords: 3D-IC, 2.5-D IC, Thermal, Power delivery, Signaling; 2.5-D IC; Thermal; Power delivery; Signaling

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APA (6th Edition):

Zhang, Y. (2017). Thermal and power delivery network modeling for emerging microelectronic integration platforms. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59199

Chicago Manual of Style (16th Edition):

Zhang, Yang. “Thermal and power delivery network modeling for emerging microelectronic integration platforms.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/59199.

MLA Handbook (7th Edition):

Zhang, Yang. “Thermal and power delivery network modeling for emerging microelectronic integration platforms.” 2017. Web. 21 Feb 2019.

Vancouver:

Zhang Y. Thermal and power delivery network modeling for emerging microelectronic integration platforms. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/59199.

Council of Science Editors:

Zhang Y. Thermal and power delivery network modeling for emerging microelectronic integration platforms. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59199


Georgia Tech

21. Kim, Duckhwan. NEUROCUBE: ENERGY-EFFICIENT PROGRAMMABLE DIGITAL DEEP LEARNING ACCELERATOR BASED ON PROCESSOR IN MEMORY PLATFORM.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 Deep learning, machine learning algorithm based on artificial neural network, shows great success in numerous pattern recognition problems, such as image recognition or speech recognition.… (more)

Subjects/Keywords: deep learning; deep learning accelerator; processor in memory; near memory process

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APA (6th Edition):

Kim, D. (2017). NEUROCUBE: ENERGY-EFFICIENT PROGRAMMABLE DIGITAL DEEP LEARNING ACCELERATOR BASED ON PROCESSOR IN MEMORY PLATFORM. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60660

Chicago Manual of Style (16th Edition):

Kim, Duckhwan. “NEUROCUBE: ENERGY-EFFICIENT PROGRAMMABLE DIGITAL DEEP LEARNING ACCELERATOR BASED ON PROCESSOR IN MEMORY PLATFORM.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/60660.

MLA Handbook (7th Edition):

Kim, Duckhwan. “NEUROCUBE: ENERGY-EFFICIENT PROGRAMMABLE DIGITAL DEEP LEARNING ACCELERATOR BASED ON PROCESSOR IN MEMORY PLATFORM.” 2017. Web. 21 Feb 2019.

Vancouver:

Kim D. NEUROCUBE: ENERGY-EFFICIENT PROGRAMMABLE DIGITAL DEEP LEARNING ACCELERATOR BASED ON PROCESSOR IN MEMORY PLATFORM. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/60660.

Council of Science Editors:

Kim D. NEUROCUBE: ENERGY-EFFICIENT PROGRAMMABLE DIGITAL DEEP LEARNING ACCELERATOR BASED ON PROCESSOR IN MEMORY PLATFORM. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/60660


Georgia Tech

22. Wang, Cheng-Yin. Organic field-effect transistors on novel renewable substrates.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 With the increasing awareness of environmental impact from electronic waste and increasing demand for flexible electronic devices, novel substrates with both biodegradability and flexibility have… (more)

Subjects/Keywords: Organic field-effect transistors; Novel renewable substrates; Top-gate geometry; CNC; Reliability; Stability; Nanolaminate; Flexible; Paper

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APA (6th Edition):

Wang, C. (2016). Organic field-effect transistors on novel renewable substrates. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59137

Chicago Manual of Style (16th Edition):

Wang, Cheng-Yin. “Organic field-effect transistors on novel renewable substrates.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/59137.

MLA Handbook (7th Edition):

Wang, Cheng-Yin. “Organic field-effect transistors on novel renewable substrates.” 2016. Web. 21 Feb 2019.

Vancouver:

Wang C. Organic field-effect transistors on novel renewable substrates. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/59137.

Council of Science Editors:

Wang C. Organic field-effect transistors on novel renewable substrates. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/59137


Georgia Tech

23. Rao, Karthik. Coordinated management of the processor and memory for optimizing energy efficiency.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 Energy efficiency is a key design goal for future computing systems. With diverse components interacting with each other on the System-on-Chip (SoC), dynamically managing performance,… (more)

Subjects/Keywords: Feedback control; Optimization; Adaptive control; 3D stacked architecture; Thermal management; Energy efficiency; Android

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APA (6th Edition):

Rao, K. (2018). Coordinated management of the processor and memory for optimizing energy efficiency. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60234

Chicago Manual of Style (16th Edition):

Rao, Karthik. “Coordinated management of the processor and memory for optimizing energy efficiency.” 2018. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/60234.

MLA Handbook (7th Edition):

Rao, Karthik. “Coordinated management of the processor and memory for optimizing energy efficiency.” 2018. Web. 21 Feb 2019.

Vancouver:

Rao K. Coordinated management of the processor and memory for optimizing energy efficiency. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/60234.

Council of Science Editors:

Rao K. Coordinated management of the processor and memory for optimizing energy efficiency. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60234


Georgia Tech

24. Kar, Monodeep. Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 The energy-efficiency and security needs in computing systems, ranging from high performance processors to low-power devices are steadily increasing. State-of-the-art digital systems use dedicated encryption… (more)

Subjects/Keywords: Side channel attack; Power attack; Differential power analysis; DPA; Correlation power analysis; CPA; Differential electromagnetic analysis; DEMA; Test vector leakage assessment; TVLA; Integrated voltage regulators; IVR; Voltage regulation; Haswell; FIVR; Security guard extension; SGX; DC-DC converters; Buck regulators; IoT; Countermeasures; Advanced encryption standard; AES; AES-NI; Randomization; Security; Masking countermeasure; Dual rail logic

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APA (6th Edition):

Kar, M. (2017). Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59182

Chicago Manual of Style (16th Edition):

Kar, Monodeep. “Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/59182.

MLA Handbook (7th Edition):

Kar, Monodeep. “Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines.” 2017. Web. 21 Feb 2019.

Vancouver:

Kar M. Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/59182.

Council of Science Editors:

Kar M. Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59182


Georgia Tech

25. Xiao, He. A Multi-physics approach to the co-design of 3D multi-core processors.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The three-dimensional integrated circuit (3D IC) is a promising solution for processors in the post-Moore era. The 3D integration stacks multiple dies vertically in a… (more)

Subjects/Keywords: Performance; Energy efficiency; 3D IC; Multi-core systems; Multi-physics analysis; Microarchitecture co-design

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APA (6th Edition):

Xiao, H. (2018). A Multi-physics approach to the co-design of 3D multi-core processors. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59810

Chicago Manual of Style (16th Edition):

Xiao, He. “A Multi-physics approach to the co-design of 3D multi-core processors.” 2018. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/59810.

MLA Handbook (7th Edition):

Xiao, He. “A Multi-physics approach to the co-design of 3D multi-core processors.” 2018. Web. 21 Feb 2019.

Vancouver:

Xiao H. A Multi-physics approach to the co-design of 3D multi-core processors. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/59810.

Council of Science Editors:

Xiao H. A Multi-physics approach to the co-design of 3D multi-core processors. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59810


Georgia Tech

26. Kim, Sihwan. Low power mixed signal system design environment using floating-gate FPAAs.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The objective of this research is to create a low-power mixed-signal system design environment using FG FPAAs. To achieve this, my research focused on implementing… (more)

Subjects/Keywords: Floating-gate; FG; Field programmable analog array (FPAA)

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APA (6th Edition):

Kim, S. (2018). Low power mixed signal system design environment using floating-gate FPAAs. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59923

Chicago Manual of Style (16th Edition):

Kim, Sihwan. “Low power mixed signal system design environment using floating-gate FPAAs.” 2018. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/59923.

MLA Handbook (7th Edition):

Kim, Sihwan. “Low power mixed signal system design environment using floating-gate FPAAs.” 2018. Web. 21 Feb 2019.

Vancouver:

Kim S. Low power mixed signal system design environment using floating-gate FPAAs. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/59923.

Council of Science Editors:

Kim S. Low power mixed signal system design environment using floating-gate FPAAs. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59923


Georgia Tech

27. Pardue, Colin Andrew. Wireless power transfer using integrated and emerging technologies.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 To support the next generation of compact low power devices, a wireless power transfer solution needs to have an improved combination of receiver coil area… (more)

Subjects/Keywords: Wireless power transfer; Internet of things; Integrated inductor; Packaging; Rf near field coupling; Power integrity

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APA (6th Edition):

Pardue, C. A. (2018). Wireless power transfer using integrated and emerging technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60216

Chicago Manual of Style (16th Edition):

Pardue, Colin Andrew. “Wireless power transfer using integrated and emerging technologies.” 2018. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/60216.

MLA Handbook (7th Edition):

Pardue, Colin Andrew. “Wireless power transfer using integrated and emerging technologies.” 2018. Web. 21 Feb 2019.

Vancouver:

Pardue CA. Wireless power transfer using integrated and emerging technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/60216.

Council of Science Editors:

Pardue CA. Wireless power transfer using integrated and emerging technologies. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60216


Georgia Tech

28. Chen, Xinwei. Performance and power management for multi-core processors.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 This dissertation addresses the problem of power and performance management for various computing systems, from single voltage island multicore processors to power constrained extreme scale… (more)

Subjects/Keywords: Performance and power management; Multi-core processors; Cloud systems; Power efficiency optimization; Feedback control

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APA (6th Edition):

Chen, X. (2018). Performance and power management for multi-core processors. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59898

Chicago Manual of Style (16th Edition):

Chen, Xinwei. “Performance and power management for multi-core processors.” 2018. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/59898.

MLA Handbook (7th Edition):

Chen, Xinwei. “Performance and power management for multi-core processors.” 2018. Web. 21 Feb 2019.

Vancouver:

Chen X. Performance and power management for multi-core processors. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/59898.

Council of Science Editors:

Chen X. Performance and power management for multi-core processors. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59898

29. Alexandrov, Borislav P. Design methodology for thermal management using embedded thermoelectric devices.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The main objectives of this dissertation is to investigate the prospects of embedded thermoelectric devices integrated in a chip package and to develop a design… (more)

Subjects/Keywords: VLSI; Thermal management; Thermoelectric cooling; Energy harvesting; CMOS control circuits; Temperature control

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APA (6th Edition):

Alexandrov, B. P. (2015). Design methodology for thermal management using embedded thermoelectric devices. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54352

Chicago Manual of Style (16th Edition):

Alexandrov, Borislav P. “Design methodology for thermal management using embedded thermoelectric devices.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/54352.

MLA Handbook (7th Edition):

Alexandrov, Borislav P. “Design methodology for thermal management using embedded thermoelectric devices.” 2015. Web. 21 Feb 2019.

Vancouver:

Alexandrov BP. Design methodology for thermal management using embedded thermoelectric devices. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/54352.

Council of Science Editors:

Alexandrov BP. Design methodology for thermal management using embedded thermoelectric devices. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/54352

30. Pan, Chenyun. A hierarchical optimization engine for nanoelectronic systems using emerging device and interconnect technologies.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 A fast and efficient hierarchical optimization engine was developed to benchmark and optimize various emerging device and interconnect technologies and system-level innovations at the early… (more)

Subjects/Keywords: Device; Interconnect; Graphene; Tunneling FET; Package; Emerging technology; Process variation; 3D integration; Heterogeneous integration; Design technology co-optimization

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APA (6th Edition):

Pan, C. (2015). A hierarchical optimization engine for nanoelectronic systems using emerging device and interconnect technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53931

Chicago Manual of Style (16th Edition):

Pan, Chenyun. “A hierarchical optimization engine for nanoelectronic systems using emerging device and interconnect technologies.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2019. http://hdl.handle.net/1853/53931.

MLA Handbook (7th Edition):

Pan, Chenyun. “A hierarchical optimization engine for nanoelectronic systems using emerging device and interconnect technologies.” 2015. Web. 21 Feb 2019.

Vancouver:

Pan C. A hierarchical optimization engine for nanoelectronic systems using emerging device and interconnect technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 21]. Available from: http://hdl.handle.net/1853/53931.

Council of Science Editors:

Pan C. A hierarchical optimization engine for nanoelectronic systems using emerging device and interconnect technologies. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53931

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