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You searched for +publisher:"Georgia Tech" +contributor:("Mukhopadhyay, Saibal"). Showing records 1 – 30 of 100 total matches.

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Georgia Tech

1. Lee, Minah. Automated I/O library generation for interposer based system-in-package integration of multiple heterogeneous dies.

Degree: MS, Electrical and Computer Engineering, 2019, Georgia Tech

 System-in-Package (SiP) integration of multiple dies in a single package can achieve much higher performance than on-board integration of ICs while reducing the design cost/effort… (more)

Subjects/Keywords: System-in-package (SiP); 2.5D integration; Interface circuits; I/O library; Automated flow

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APA (6th Edition):

Lee, M. (2019). Automated I/O library generation for interposer based system-in-package integration of multiple heterogeneous dies. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62366

Chicago Manual of Style (16th Edition):

Lee, Minah. “Automated I/O library generation for interposer based system-in-package integration of multiple heterogeneous dies.” 2019. Masters Thesis, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/62366.

MLA Handbook (7th Edition):

Lee, Minah. “Automated I/O library generation for interposer based system-in-package integration of multiple heterogeneous dies.” 2019. Web. 06 Aug 2020.

Vancouver:

Lee M. Automated I/O library generation for interposer based system-in-package integration of multiple heterogeneous dies. [Internet] [Masters thesis]. Georgia Tech; 2019. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/62366.

Council of Science Editors:

Lee M. Automated I/O library generation for interposer based system-in-package integration of multiple heterogeneous dies. [Masters Thesis]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62366


Georgia Tech

2. VanDerheyden, Andrew Louis. Characterization of thermal coupling in chip multiprocessors.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 For semiconductor processors temperature increases leakage current, which in turn in- creases the temperature of the processor. This increase in heat is seen by other… (more)

Subjects/Keywords: Thermal management; Thermal characterization; Thermal coupling; High performance processors; Thermal analysis

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APA (6th Edition):

VanDerheyden, A. L. (2014). Characterization of thermal coupling in chip multiprocessors. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51892

Chicago Manual of Style (16th Edition):

VanDerheyden, Andrew Louis. “Characterization of thermal coupling in chip multiprocessors.” 2014. Masters Thesis, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/51892.

MLA Handbook (7th Edition):

VanDerheyden, Andrew Louis. “Characterization of thermal coupling in chip multiprocessors.” 2014. Web. 06 Aug 2020.

Vancouver:

VanDerheyden AL. Characterization of thermal coupling in chip multiprocessors. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/51892.

Council of Science Editors:

VanDerheyden AL. Characterization of thermal coupling in chip multiprocessors. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51892


Georgia Tech

3. Mannan, Parth. Exploring Opportunities and Challenges in Enabling Neuro-Evolutionary Algorithms in Hardware.

Degree: MS, Electrical and Computer Engineering, 2018, Georgia Tech

 Recent advancements in the machine learning algorithms, especially the development of Deep Neural Networks (DNNs) have transformed the landscape of Artificial Intelligence (AI). With every… (more)

Subjects/Keywords: Deep Learning; NeuroEvolution; Architecture; Evolutionary Algorithms; Hardware; Accelerators; Scalability; Distributed System; Collaborative; learning

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APA (6th Edition):

Mannan, P. (2018). Exploring Opportunities and Challenges in Enabling Neuro-Evolutionary Algorithms in Hardware. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62255

Chicago Manual of Style (16th Edition):

Mannan, Parth. “Exploring Opportunities and Challenges in Enabling Neuro-Evolutionary Algorithms in Hardware.” 2018. Masters Thesis, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/62255.

MLA Handbook (7th Edition):

Mannan, Parth. “Exploring Opportunities and Challenges in Enabling Neuro-Evolutionary Algorithms in Hardware.” 2018. Web. 06 Aug 2020.

Vancouver:

Mannan P. Exploring Opportunities and Challenges in Enabling Neuro-Evolutionary Algorithms in Hardware. [Internet] [Masters thesis]. Georgia Tech; 2018. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/62255.

Council of Science Editors:

Mannan P. Exploring Opportunities and Challenges in Enabling Neuro-Evolutionary Algorithms in Hardware. [Masters Thesis]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/62255

4. Bonhomme, Phillip. Circuit modeling of spintronic devices: a SPICE implementation.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 Every engineer that has worked on designing an integrated circuit has to leverage an under- standing of device physics. Understanding device physics is essential when… (more)

Subjects/Keywords: SPICE; Spintronics; Circuit simulation; Magnetization dynamics; Spintronics; Mathematical models

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APA (6th Edition):

Bonhomme, P. (2014). Circuit modeling of spintronic devices: a SPICE implementation. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51818

Chicago Manual of Style (16th Edition):

Bonhomme, Phillip. “Circuit modeling of spintronic devices: a SPICE implementation.” 2014. Masters Thesis, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/51818.

MLA Handbook (7th Edition):

Bonhomme, Phillip. “Circuit modeling of spintronic devices: a SPICE implementation.” 2014. Web. 06 Aug 2020.

Vancouver:

Bonhomme P. Circuit modeling of spintronic devices: a SPICE implementation. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/51818.

Council of Science Editors:

Bonhomme P. Circuit modeling of spintronic devices: a SPICE implementation. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51818

5. Ku, Bon Woong Woong. Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node.

Degree: MS, Electrical and Computer Engineering, 2017, Georgia Tech

 The nature of device scaling in the 7nm era is changing from the traditional scheme driven by Moore’s law because of the physical and economic… (more)

Subjects/Keywords: Gate-level; Monolithic 3D IC; PPC tradeoff; 7nm technology node

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APA (6th Edition):

Ku, B. W. W. (2017). Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58257

Chicago Manual of Style (16th Edition):

Ku, Bon Woong Woong. “Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node.” 2017. Masters Thesis, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/58257.

MLA Handbook (7th Edition):

Ku, Bon Woong Woong. “Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node.” 2017. Web. 06 Aug 2020.

Vancouver:

Ku BWW. Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/58257.

Council of Science Editors:

Ku BWW. Power, performance, and cost impact of gate-level monolithic 3D IC in the 7nm technology node. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58257


Georgia Tech

6. Shim, Da Eun. 3D Flash Memory Cube Design Utilizing COTS for Space.

Degree: MS, Electrical and Computer Engineering, 2019, Georgia Tech

 With the rapid growth in scope for space missions, the computing capabilities of on-board spacecraft is becoming a major limiting factor for future missions. This… (more)

Subjects/Keywords: NAND Flash; memory cube; COTS; electronics for space

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APA (6th Edition):

Shim, D. E. (2019). 3D Flash Memory Cube Design Utilizing COTS for Space. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62704

Chicago Manual of Style (16th Edition):

Shim, Da Eun. “3D Flash Memory Cube Design Utilizing COTS for Space.” 2019. Masters Thesis, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/62704.

MLA Handbook (7th Edition):

Shim, Da Eun. “3D Flash Memory Cube Design Utilizing COTS for Space.” 2019. Web. 06 Aug 2020.

Vancouver:

Shim DE. 3D Flash Memory Cube Design Utilizing COTS for Space. [Internet] [Masters thesis]. Georgia Tech; 2019. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/62704.

Council of Science Editors:

Shim DE. 3D Flash Memory Cube Design Utilizing COTS for Space. [Masters Thesis]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62704


Georgia Tech

7. Chintaluri, Ashwin K. Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays.

Degree: MS, Electrical and Computer Engineering, 2016, Georgia Tech

 Spin transfer torque magnetic random access memory (STT-MRAM) is a competitive, future memory technology that has gained immense interest in recent years due to its… (more)

Subjects/Keywords: STT-MRAM; Variation; Faults

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APA (6th Edition):

Chintaluri, A. K. (2016). Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55060

Chicago Manual of Style (16th Edition):

Chintaluri, Ashwin K. “Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays.” 2016. Masters Thesis, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/55060.

MLA Handbook (7th Edition):

Chintaluri, Ashwin K. “Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays.” 2016. Web. 06 Aug 2020.

Vancouver:

Chintaluri AK. Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/55060.

Council of Science Editors:

Chintaluri AK. Analysis of defects and fault models in embedded spin transfer torque (STT) MRAM arrays. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55060


Georgia Tech

8. Yueh, Wen. Modeling, characterization, and control of the electrical-thermal interactions in advanced packages.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The multi-chip integration in an advanced packaging has made the multi-physics interactions increasingly important. The objective of this research is to address the thermal coupling… (more)

Subjects/Keywords: Cooling; VLSI; SRAM; EDRAM; 3D IC; Packaging

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APA (6th Edition):

Yueh, W. (2015). Modeling, characterization, and control of the electrical-thermal interactions in advanced packages. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56171

Chicago Manual of Style (16th Edition):

Yueh, Wen. “Modeling, characterization, and control of the electrical-thermal interactions in advanced packages.” 2015. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/56171.

MLA Handbook (7th Edition):

Yueh, Wen. “Modeling, characterization, and control of the electrical-thermal interactions in advanced packages.” 2015. Web. 06 Aug 2020.

Vancouver:

Yueh W. Modeling, characterization, and control of the electrical-thermal interactions in advanced packages. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/56171.

Council of Science Editors:

Yueh W. Modeling, characterization, and control of the electrical-thermal interactions in advanced packages. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56171


Georgia Tech

9. Carlo, Sergio. Load-Aware Power Conversion and Integration for Heterogeneous Systems.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 In this thesis we develop a holistic co-design approach to optimize the conversion systems in order to perform relevant trade-offs taking into account system-level converter,… (more)

Subjects/Keywords: Power conversion 3D single inductor multiple output SIMO control design power management

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APA (6th Edition):

Carlo, S. (2015). Load-Aware Power Conversion and Integration for Heterogeneous Systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56182

Chicago Manual of Style (16th Edition):

Carlo, Sergio. “Load-Aware Power Conversion and Integration for Heterogeneous Systems.” 2015. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/56182.

MLA Handbook (7th Edition):

Carlo, Sergio. “Load-Aware Power Conversion and Integration for Heterogeneous Systems.” 2015. Web. 06 Aug 2020.

Vancouver:

Carlo S. Load-Aware Power Conversion and Integration for Heterogeneous Systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/56182.

Council of Science Editors:

Carlo S. Load-Aware Power Conversion and Integration for Heterogeneous Systems. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56182


Georgia Tech

10. Long, Yun. Energy efficient processing in memory architecture for deep learning computing acceleration.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 The major objective of this research is to make the processing-in-memory (PIM) based deep learning accelerator more practical and more computing efficient. This research particularly… (more)

Subjects/Keywords: Processing-in-memory; Deep learning; Resistive ram; Ferroelectric FET; Machine learning computing acceleration

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APA (6th Edition):

Long, Y. (2019). Energy efficient processing in memory architecture for deep learning computing acceleration. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62311

Chicago Manual of Style (16th Edition):

Long, Yun. “Energy efficient processing in memory architecture for deep learning computing acceleration.” 2019. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/62311.

MLA Handbook (7th Edition):

Long, Yun. “Energy efficient processing in memory architecture for deep learning computing acceleration.” 2019. Web. 06 Aug 2020.

Vancouver:

Long Y. Energy efficient processing in memory architecture for deep learning computing acceleration. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/62311.

Council of Science Editors:

Long Y. Energy efficient processing in memory architecture for deep learning computing acceleration. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62311


Georgia Tech

11. Chang, Kyungwook. Design and Tool Solutions for Energy-Efficient Reliable Monolithic 3D ICs.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 The objective of this dissertation is to analyze and identify the benefits and challenges of energy-efficient and reliable monolithic 3D (M3D) ICs, and to develop… (more)

Subjects/Keywords: Monolithic 3D IC; CAD; Physical Design; Low Power Design; High Performance Design; Power Supply Integrity; Deep Neural Network

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APA (6th Edition):

Chang, K. (2019). Design and Tool Solutions for Energy-Efficient Reliable Monolithic 3D ICs. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62672

Chicago Manual of Style (16th Edition):

Chang, Kyungwook. “Design and Tool Solutions for Energy-Efficient Reliable Monolithic 3D ICs.” 2019. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/62672.

MLA Handbook (7th Edition):

Chang, Kyungwook. “Design and Tool Solutions for Energy-Efficient Reliable Monolithic 3D ICs.” 2019. Web. 06 Aug 2020.

Vancouver:

Chang K. Design and Tool Solutions for Energy-Efficient Reliable Monolithic 3D ICs. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/62672.

Council of Science Editors:

Chang K. Design and Tool Solutions for Energy-Efficient Reliable Monolithic 3D ICs. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62672


Georgia Tech

12. Parihar, Abhinav. Utilizing switched linear dynamics of interconnected state transition devices for approximating certain global functions.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 The objective of the proposed research is to create alternative computing models and architectures, unlike (discrete) sequential Turing machine/Von Neumann style models, which utilize the… (more)

Subjects/Keywords: coupled oscillators; switched linear dynamics; eigenvector; graph coloring

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APA (6th Edition):

Parihar, A. (2019). Utilizing switched linear dynamics of interconnected state transition devices for approximating certain global functions. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62725

Chicago Manual of Style (16th Edition):

Parihar, Abhinav. “Utilizing switched linear dynamics of interconnected state transition devices for approximating certain global functions.” 2019. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/62725.

MLA Handbook (7th Edition):

Parihar, Abhinav. “Utilizing switched linear dynamics of interconnected state transition devices for approximating certain global functions.” 2019. Web. 06 Aug 2020.

Vancouver:

Parihar A. Utilizing switched linear dynamics of interconnected state transition devices for approximating certain global functions. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/62725.

Council of Science Editors:

Parihar A. Utilizing switched linear dynamics of interconnected state transition devices for approximating certain global functions. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62725


Georgia Tech

13. Onyewuchi, Urenna. Managing environmentally stressed aging assets in electric power utilities.

Degree: PhD, Electrical and Computer Engineering, 2012, Georgia Tech

 A model for optimizing the differential cost between a preventive maintenance program and a traditional run-to-failure program on managing assets under uncertainty is developed to… (more)

Subjects/Keywords: Asset management; Environmental stress; Decision making; Electric utility; Aging infrastructure

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APA (6th Edition):

Onyewuchi, U. (2012). Managing environmentally stressed aging assets in electric power utilities. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53150

Chicago Manual of Style (16th Edition):

Onyewuchi, Urenna. “Managing environmentally stressed aging assets in electric power utilities.” 2012. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/53150.

MLA Handbook (7th Edition):

Onyewuchi, Urenna. “Managing environmentally stressed aging assets in electric power utilities.” 2012. Web. 06 Aug 2020.

Vancouver:

Onyewuchi U. Managing environmentally stressed aging assets in electric power utilities. [Internet] [Doctoral dissertation]. Georgia Tech; 2012. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/53150.

Council of Science Editors:

Onyewuchi U. Managing environmentally stressed aging assets in electric power utilities. [Doctoral Dissertation]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/53150


Georgia Tech

14. Chakraborty, Partha Sarathi. Design, scaling and reliability of devices for high-performance mixed-signal applications.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 This research investigates and gains new understanding on how silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device design couples with both performance scaling and reliability for… (more)

Subjects/Keywords: Silicon-germanium; Heterojunction bipolar transistor; TCAD; Scaling; Reliability; Device design; Mixed-signal; Simulation; High-frequency; Cryogenic temperature; Characterization

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APA (6th Edition):

Chakraborty, P. S. (2015). Design, scaling and reliability of devices for high-performance mixed-signal applications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58137

Chicago Manual of Style (16th Edition):

Chakraborty, Partha Sarathi. “Design, scaling and reliability of devices for high-performance mixed-signal applications.” 2015. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/58137.

MLA Handbook (7th Edition):

Chakraborty, Partha Sarathi. “Design, scaling and reliability of devices for high-performance mixed-signal applications.” 2015. Web. 06 Aug 2020.

Vancouver:

Chakraborty PS. Design, scaling and reliability of devices for high-performance mixed-signal applications. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/58137.

Council of Science Editors:

Chakraborty PS. Design, scaling and reliability of devices for high-performance mixed-signal applications. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/58137


Georgia Tech

15. Kim, Hyungwook. CMOS radio-frequency power amplifiers for multi-standard wireless communications.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 The development of multi-standard wireless communication systems with low cost and high integration is continuously requested and accompanied by the explosive growth of the wireless… (more)

Subjects/Keywords: CMOS; Power amplifier; RF PA; Multi-standard wireless communications; Wireless communication systems; Power amplifiers; Metal oxide semiconductors, Complementary; Radio Transmitter-receivers

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APA (6th Edition):

Kim, H. (2011). CMOS radio-frequency power amplifiers for multi-standard wireless communications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/44786

Chicago Manual of Style (16th Edition):

Kim, Hyungwook. “CMOS radio-frequency power amplifiers for multi-standard wireless communications.” 2011. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/44786.

MLA Handbook (7th Edition):

Kim, Hyungwook. “CMOS radio-frequency power amplifiers for multi-standard wireless communications.” 2011. Web. 06 Aug 2020.

Vancouver:

Kim H. CMOS radio-frequency power amplifiers for multi-standard wireless communications. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/44786.

Council of Science Editors:

Kim H. CMOS radio-frequency power amplifiers for multi-standard wireless communications. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/44786


Georgia Tech

16. Wunderlich, Richard Bryan. Floating-gate-programmable and reconfigurable, digital and mixed-signal systems.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 This body of work as whole has the theme of using floating-gates and reconfigurable systems to explore and implement non-traditional computing solutions to difficult problems.… (more)

Subjects/Keywords: Floating-gate; Reconfigurable; Digital; Analog processing; Field programmable gate arrays

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APA (6th Edition):

Wunderlich, R. B. (2014). Floating-gate-programmable and reconfigurable, digital and mixed-signal systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51815

Chicago Manual of Style (16th Edition):

Wunderlich, Richard Bryan. “Floating-gate-programmable and reconfigurable, digital and mixed-signal systems.” 2014. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/51815.

MLA Handbook (7th Edition):

Wunderlich, Richard Bryan. “Floating-gate-programmable and reconfigurable, digital and mixed-signal systems.” 2014. Web. 06 Aug 2020.

Vancouver:

Wunderlich RB. Floating-gate-programmable and reconfigurable, digital and mixed-signal systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/51815.

Council of Science Editors:

Wunderlich RB. Floating-gate-programmable and reconfigurable, digital and mixed-signal systems. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51815


Georgia Tech

17. Chae, Kwanyeob. Design methodologies for robust low-power digital systems under static and dynamic variations.

Degree: PhD, Electrical and Computer Engineering, 2013, Georgia Tech

 Variability affects the performance and power of a circuit. Along with static variations, dynamic variations, which occur during chip operation, necessitate a safety margin. The… (more)

Subjects/Keywords: Adaptive circuit; Resilient design; Static variation; Dynamic variation; Error prevention

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APA (6th Edition):

Chae, K. (2013). Design methodologies for robust low-power digital systems under static and dynamic variations. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52174

Chicago Manual of Style (16th Edition):

Chae, Kwanyeob. “Design methodologies for robust low-power digital systems under static and dynamic variations.” 2013. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/52174.

MLA Handbook (7th Edition):

Chae, Kwanyeob. “Design methodologies for robust low-power digital systems under static and dynamic variations.” 2013. Web. 06 Aug 2020.

Vancouver:

Chae K. Design methodologies for robust low-power digital systems under static and dynamic variations. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/52174.

Council of Science Editors:

Chae K. Design methodologies for robust low-power digital systems under static and dynamic variations. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/52174


Georgia Tech

18. Saha, Prabir K. SiGe BiCMOS RF front-ends for adaptive wideband receivers.

Degree: PhD, Electrical and Computer Engineering, 2013, Georgia Tech

 The pursuit of dense monolithic integration and higher operating speed continues to push the integrated circuit (IC) fabrication technologies to their limits. The increasing process… (more)

Subjects/Keywords: Self-healing; Adaptive; Mixer; Image-rejection; RF; LNA; SPDT

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APA (6th Edition):

Saha, P. K. (2013). SiGe BiCMOS RF front-ends for adaptive wideband receivers. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52184

Chicago Manual of Style (16th Edition):

Saha, Prabir K. “SiGe BiCMOS RF front-ends for adaptive wideband receivers.” 2013. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/52184.

MLA Handbook (7th Edition):

Saha, Prabir K. “SiGe BiCMOS RF front-ends for adaptive wideband receivers.” 2013. Web. 06 Aug 2020.

Vancouver:

Saha PK. SiGe BiCMOS RF front-ends for adaptive wideband receivers. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/52184.

Council of Science Editors:

Saha PK. SiGe BiCMOS RF front-ends for adaptive wideband receivers. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/52184


Georgia Tech

19. Wang, Cheng-Yin. Organic field-effect transistors on novel renewable substrates.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 With the increasing awareness of environmental impact from electronic waste and increasing demand for flexible electronic devices, novel substrates with both biodegradability and flexibility have… (more)

Subjects/Keywords: Organic field-effect transistors; Novel renewable substrates; Top-gate geometry; CNC; Reliability; Stability; Nanolaminate; Flexible; Paper

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APA (6th Edition):

Wang, C. (2016). Organic field-effect transistors on novel renewable substrates. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59137

Chicago Manual of Style (16th Edition):

Wang, Cheng-Yin. “Organic field-effect transistors on novel renewable substrates.” 2016. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/59137.

MLA Handbook (7th Edition):

Wang, Cheng-Yin. “Organic field-effect transistors on novel renewable substrates.” 2016. Web. 06 Aug 2020.

Vancouver:

Wang C. Organic field-effect transistors on novel renewable substrates. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/59137.

Council of Science Editors:

Wang C. Organic field-effect transistors on novel renewable substrates. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/59137


Georgia Tech

20. Xiao, He. A Multi-physics approach to the co-design of 3D multi-core processors.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The three-dimensional integrated circuit (3D IC) is a promising solution for processors in the post-Moore era. The 3D integration stacks multiple dies vertically in a… (more)

Subjects/Keywords: Performance; Energy efficiency; 3D IC; Multi-core systems; Multi-physics analysis; Microarchitecture co-design

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APA (6th Edition):

Xiao, H. (2018). A Multi-physics approach to the co-design of 3D multi-core processors. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59810

Chicago Manual of Style (16th Edition):

Xiao, He. “A Multi-physics approach to the co-design of 3D multi-core processors.” 2018. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/59810.

MLA Handbook (7th Edition):

Xiao, He. “A Multi-physics approach to the co-design of 3D multi-core processors.” 2018. Web. 06 Aug 2020.

Vancouver:

Xiao H. A Multi-physics approach to the co-design of 3D multi-core processors. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/59810.

Council of Science Editors:

Xiao H. A Multi-physics approach to the co-design of 3D multi-core processors. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59810


Georgia Tech

21. Kim, Sihwan. Low power mixed signal system design environment using floating-gate FPAAs.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The objective of this research is to create a low-power mixed-signal system design environment using FG FPAAs. To achieve this, my research focused on implementing… (more)

Subjects/Keywords: Floating-gate; FG; Field programmable analog array (FPAA)

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APA (6th Edition):

Kim, S. (2018). Low power mixed signal system design environment using floating-gate FPAAs. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59923

Chicago Manual of Style (16th Edition):

Kim, Sihwan. “Low power mixed signal system design environment using floating-gate FPAAs.” 2018. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/59923.

MLA Handbook (7th Edition):

Kim, Sihwan. “Low power mixed signal system design environment using floating-gate FPAAs.” 2018. Web. 06 Aug 2020.

Vancouver:

Kim S. Low power mixed signal system design environment using floating-gate FPAAs. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/59923.

Council of Science Editors:

Kim S. Low power mixed signal system design environment using floating-gate FPAAs. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59923


Georgia Tech

22. Pardue, Colin Andrew. Wireless power transfer using integrated and emerging technologies.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 To support the next generation of compact low power devices, a wireless power transfer solution needs to have an improved combination of receiver coil area… (more)

Subjects/Keywords: Wireless power transfer; Internet of things; Integrated inductor; Packaging; Rf near field coupling; Power integrity

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APA (6th Edition):

Pardue, C. A. (2018). Wireless power transfer using integrated and emerging technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60216

Chicago Manual of Style (16th Edition):

Pardue, Colin Andrew. “Wireless power transfer using integrated and emerging technologies.” 2018. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/60216.

MLA Handbook (7th Edition):

Pardue, Colin Andrew. “Wireless power transfer using integrated and emerging technologies.” 2018. Web. 06 Aug 2020.

Vancouver:

Pardue CA. Wireless power transfer using integrated and emerging technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/60216.

Council of Science Editors:

Pardue CA. Wireless power transfer using integrated and emerging technologies. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60216


Georgia Tech

23. Amir, Mohammad Faisal. Design methodology for 3d-stacked imaging systems with integrated deep learning.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The Internet of Things (IoT) revolution has brought along with it billions of always on, always connected devices and sensors, associated with which are huge… (more)

Subjects/Keywords: Neural networks; Image sensor; Energy harvesting; Deep learning; 3D integration

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APA (6th Edition):

Amir, M. F. (2018). Design methodology for 3d-stacked imaging systems with integrated deep learning. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61609

Chicago Manual of Style (16th Edition):

Amir, Mohammad Faisal. “Design methodology for 3d-stacked imaging systems with integrated deep learning.” 2018. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/61609.

MLA Handbook (7th Edition):

Amir, Mohammad Faisal. “Design methodology for 3d-stacked imaging systems with integrated deep learning.” 2018. Web. 06 Aug 2020.

Vancouver:

Amir MF. Design methodology for 3d-stacked imaging systems with integrated deep learning. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/61609.

Council of Science Editors:

Amir MF. Design methodology for 3d-stacked imaging systems with integrated deep learning. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/61609


Georgia Tech

24. Kersey, Chad Daniel. A multi-paradigm C++-based hardware description language.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 A generative hardware description library for C++, the CHDL Hardware Design Library or CHDL, along with a body of supporting libraries and a description of… (more)

Subjects/Keywords: Hardware description language; HDL; Domain-specific language; High-level synthesis

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APA (6th Edition):

Kersey, C. D. (2019). A multi-paradigm C++-based hardware description language. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62342

Chicago Manual of Style (16th Edition):

Kersey, Chad Daniel. “A multi-paradigm C++-based hardware description language.” 2019. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/62342.

MLA Handbook (7th Edition):

Kersey, Chad Daniel. “A multi-paradigm C++-based hardware description language.” 2019. Web. 06 Aug 2020.

Vancouver:

Kersey CD. A multi-paradigm C++-based hardware description language. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/62342.

Council of Science Editors:

Kersey CD. A multi-paradigm C++-based hardware description language. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62342


Georgia Tech

25. Wu, Jiadong. Improving the throughput of novel cluster computing systems.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 Traditional cluster computing systems such as the supercomputers are equipped with specially designed high-performance hardware, which escalates the manufacturing cost and the energy cost of… (more)

Subjects/Keywords: GPU; Hadoop; Computer cluster; Parallel computing

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APA (6th Edition):

Wu, J. (2015). Improving the throughput of novel cluster computing systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53890

Chicago Manual of Style (16th Edition):

Wu, Jiadong. “Improving the throughput of novel cluster computing systems.” 2015. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/53890.

MLA Handbook (7th Edition):

Wu, Jiadong. “Improving the throughput of novel cluster computing systems.” 2015. Web. 06 Aug 2020.

Vancouver:

Wu J. Improving the throughput of novel cluster computing systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/53890.

Council of Science Editors:

Wu J. Improving the throughput of novel cluster computing systems. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53890


Georgia Tech

26. Adil, Farhan. Applications of floating-gate based programmable mixed-signal reconfigurable systems.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 A mixed-signal reconfigurable platform gives the designer the choice of implementing systems using the benefits of both analog and digital circuits. The subject of this… (more)

Subjects/Keywords: FPAA; Mixed-signal IC; Reconfigurable systems

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APA (6th Edition):

Adil, F. (2014). Applications of floating-gate based programmable mixed-signal reconfigurable systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54272

Chicago Manual of Style (16th Edition):

Adil, Farhan. “Applications of floating-gate based programmable mixed-signal reconfigurable systems.” 2014. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/54272.

MLA Handbook (7th Edition):

Adil, Farhan. “Applications of floating-gate based programmable mixed-signal reconfigurable systems.” 2014. Web. 06 Aug 2020.

Vancouver:

Adil F. Applications of floating-gate based programmable mixed-signal reconfigurable systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/54272.

Council of Science Editors:

Adil F. Applications of floating-gate based programmable mixed-signal reconfigurable systems. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/54272


Georgia Tech

27. Kumar, Vachan. Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 Modeling approaches are developed to optimize emerging on-chip and off-chip electrical interconnect technologies and benchmark them against conventional technologies. While transistor scaling results in an… (more)

Subjects/Keywords: Interconnect modeling; Graphene nanoribbons; Through silicon via, airgap interconnects

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APA (6th Edition):

Kumar, V. (2014). Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54280

Chicago Manual of Style (16th Edition):

Kumar, Vachan. “Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies.” 2014. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/54280.

MLA Handbook (7th Edition):

Kumar, Vachan. “Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies.” 2014. Web. 06 Aug 2020.

Vancouver:

Kumar V. Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/54280.

Council of Science Editors:

Kumar V. Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/54280


Georgia Tech

28. Wan, Zhimin. Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling.

Degree: PhD, Mechanical Engineering, 2016, Georgia Tech

 Microfluidic convection cooling is a promising technique for future high power microprocessors, radio-frequency (RF) transceivers, solid-state lasers, and light emitting diodes (LED). Three-dimensional (3D) stacking… (more)

Subjects/Keywords: Microfluidic cooling; Pin fin; 3D ICs; Microfabrication; Flow boiling

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APA (6th Edition):

Wan, Z. (2016). Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55480

Chicago Manual of Style (16th Edition):

Wan, Zhimin. “Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling.” 2016. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/55480.

MLA Handbook (7th Edition):

Wan, Zhimin. “Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling.” 2016. Web. 06 Aug 2020.

Vancouver:

Wan Z. Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/55480.

Council of Science Editors:

Wan Z. Transport Characteristics of Pin Fin Enhanced Microgaps under Single and Two Phase Cooling. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55480


Georgia Tech

29. Natarajan, Jayaram. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 One of the challenges faced today in the design of microprocessors is to obtain power, performance scalability and reliability at the same time with technology… (more)

Subjects/Keywords: Microprocessor; Low power; Process variation; Timing variation tolerant; Timing margins; Better than worse-case design; Error resilient pipeline; Reliability

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APA (6th Edition):

Natarajan, J. (2016). Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55577

Chicago Manual of Style (16th Edition):

Natarajan, Jayaram. “Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.” 2016. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/55577.

MLA Handbook (7th Edition):

Natarajan, Jayaram. “Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.” 2016. Web. 06 Aug 2020.

Vancouver:

Natarajan J. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/55577.

Council of Science Editors:

Natarajan J. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55577


Georgia Tech

30. Song, Taigon. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The objective of this research is to study and develop computer-aided-design (CAD) methodologies for reliability in chip-package co-designed three-dimensional integrated circuit (3D IC) systems. 3D… (more)

Subjects/Keywords: 3D IC; Design Methodologies

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APA (6th Edition):

Song, T. (2015). CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56188

Chicago Manual of Style (16th Edition):

Song, Taigon. “CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.” 2015. Doctoral Dissertation, Georgia Tech. Accessed August 06, 2020. http://hdl.handle.net/1853/56188.

MLA Handbook (7th Edition):

Song, Taigon. “CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS.” 2015. Web. 06 Aug 2020.

Vancouver:

Song T. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1853/56188.

Council of Science Editors:

Song T. CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56188

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