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You searched for +publisher:"Georgia Tech" +contributor:("Milor, Linda"). Showing records 1 – 30 of 32 total matches.

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Georgia Tech

1. Kim, Woongrae. Memory BIST with Statistical Failure Analysis for Diagnosis of Resistive-Open Defects due to Electromigration and Stress-Induced Voiding in an SRAM.

Degree: MS, Electrical and Computer Engineering, 2016, Georgia Tech

 The object of the research has been to develop built-in self-test and statistical failure analysis methodologies for electrical detection and diagnosis of backend wearout mechanisms… (more)

Subjects/Keywords: BIST; statistical failure analysis; EM; SIV; SRAM

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APA (6th Edition):

Kim, W. (2016). Memory BIST with Statistical Failure Analysis for Diagnosis of Resistive-Open Defects due to Electromigration and Stress-Induced Voiding in an SRAM. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56191

Chicago Manual of Style (16th Edition):

Kim, Woongrae. “Memory BIST with Statistical Failure Analysis for Diagnosis of Resistive-Open Defects due to Electromigration and Stress-Induced Voiding in an SRAM.” 2016. Masters Thesis, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/56191.

MLA Handbook (7th Edition):

Kim, Woongrae. “Memory BIST with Statistical Failure Analysis for Diagnosis of Resistive-Open Defects due to Electromigration and Stress-Induced Voiding in an SRAM.” 2016. Web. 25 Jun 2019.

Vancouver:

Kim W. Memory BIST with Statistical Failure Analysis for Diagnosis of Resistive-Open Defects due to Electromigration and Stress-Induced Voiding in an SRAM. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/56191.

Council of Science Editors:

Kim W. Memory BIST with Statistical Failure Analysis for Diagnosis of Resistive-Open Defects due to Electromigration and Stress-Induced Voiding in an SRAM. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56191


Georgia Tech

2. Gassel, Kyle Andrew. Analog public PUF for hardware security.

Degree: MS, Electrical and Computer Engineering, 2018, Georgia Tech

In this thesis I improve a current analog PUF design, primarily in uniqueness and reliability, and further analyze it to show fitness for use as a PPUF. Advisors/Committee Members: Chatterjee, Abhijit (advisor), Milor, Linda S (committee member), Keezer, David C (committee member).

Subjects/Keywords: PUF; PPUF; Cryptography; Security

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APA (6th Edition):

Gassel, K. A. (2018). Analog public PUF for hardware security. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59961

Chicago Manual of Style (16th Edition):

Gassel, Kyle Andrew. “Analog public PUF for hardware security.” 2018. Masters Thesis, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/59961.

MLA Handbook (7th Edition):

Gassel, Kyle Andrew. “Analog public PUF for hardware security.” 2018. Web. 25 Jun 2019.

Vancouver:

Gassel KA. Analog public PUF for hardware security. [Internet] [Masters thesis]. Georgia Tech; 2018. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/59961.

Council of Science Editors:

Gassel KA. Analog public PUF for hardware security. [Masters Thesis]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59961


Georgia Tech

3. Zhang, David Chong. Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 A power distribution network (PDN) is designed to provide clean power and facilitate high signal integrity in modern electronic systems. However, the design of a… (more)

Subjects/Keywords: Power delivery network; Power transmission line; Signal integrity; Power integrity; Return path discontinuity

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APA (6th Edition):

Zhang, D. C. (2016). Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56282

Chicago Manual of Style (16th Edition):

Zhang, David Chong. “Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems.” 2016. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/56282.

MLA Handbook (7th Edition):

Zhang, David Chong. “Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems.” 2016. Web. 25 Jun 2019.

Vancouver:

Zhang DC. Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/56282.

Council of Science Editors:

Zhang DC. Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56282


Georgia Tech

4. Khan, Talha Mansur. Organic semiconductor bulk heterojunction diodes with low dark current for photovoltaic, photodetection, and scintillator-free ionizing radiation detection applications.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 Solid-state organic semiconductor-based photovoltaics (OPV) are an emerging technology being developed to generate clean and sustainable electricity in light weight, flexible and shatter-proof form factors.… (more)

Subjects/Keywords: Organic solar cells; Organic photodetectors; High detectivity

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APA (6th Edition):

Khan, T. M. (2016). Organic semiconductor bulk heterojunction diodes with low dark current for photovoltaic, photodetection, and scintillator-free ionizing radiation detection applications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58182

Chicago Manual of Style (16th Edition):

Khan, Talha Mansur. “Organic semiconductor bulk heterojunction diodes with low dark current for photovoltaic, photodetection, and scintillator-free ionizing radiation detection applications.” 2016. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/58182.

MLA Handbook (7th Edition):

Khan, Talha Mansur. “Organic semiconductor bulk heterojunction diodes with low dark current for photovoltaic, photodetection, and scintillator-free ionizing radiation detection applications.” 2016. Web. 25 Jun 2019.

Vancouver:

Khan TM. Organic semiconductor bulk heterojunction diodes with low dark current for photovoltaic, photodetection, and scintillator-free ionizing radiation detection applications. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/58182.

Council of Science Editors:

Khan TM. Organic semiconductor bulk heterojunction diodes with low dark current for photovoltaic, photodetection, and scintillator-free ionizing radiation detection applications. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/58182


Georgia Tech

5. Gallé, William Preston. MEMS-based fabrication of power electronics components for advanced power converters.

Degree: PhD, Electrical and Computer Engineering, 2012, Georgia Tech

 Fabrication technology, based on MEMS processes, for constructing components for use in switched-mode power supplies are developed and presented. Capacitors, magnetic cores, and inductors based… (more)

Subjects/Keywords: Power converters; Capacitors; Inductors; Electroplating; MEMS; Microelectromechanical systems; DC-to-DC converters; Switching power supplies; Electric inductors

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APA (6th Edition):

Gallé, W. P. (2012). MEMS-based fabrication of power electronics components for advanced power converters. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/45821

Chicago Manual of Style (16th Edition):

Gallé, William Preston. “MEMS-based fabrication of power electronics components for advanced power converters.” 2012. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/45821.

MLA Handbook (7th Edition):

Gallé, William Preston. “MEMS-based fabrication of power electronics components for advanced power converters.” 2012. Web. 25 Jun 2019.

Vancouver:

Gallé WP. MEMS-based fabrication of power electronics components for advanced power converters. [Internet] [Doctoral dissertation]. Georgia Tech; 2012. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/45821.

Council of Science Editors:

Gallé WP. MEMS-based fabrication of power electronics components for advanced power converters. [Doctoral Dissertation]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/45821


Georgia Tech

6. Banerjee, Debashis. Intelligent real-time environment and process adaptive radio frequency front-ends for ultra low power applications.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 In the thesis the design of process tolerant, use-aware radio-frequency front-ends were explored. First, the design of fuzzy logic and equation based controllers, which can… (more)

Subjects/Keywords: Radio frequency; Adaptation; Low noise amplifier; LNA; Front-end; Fuzzy logic; Learning; Energy-per-bit; Mixer; Clustering; Process Variation; Channel

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APA (6th Edition):

Banerjee, D. (2015). Intelligent real-time environment and process adaptive radio frequency front-ends for ultra low power applications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53882

Chicago Manual of Style (16th Edition):

Banerjee, Debashis. “Intelligent real-time environment and process adaptive radio frequency front-ends for ultra low power applications.” 2015. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/53882.

MLA Handbook (7th Edition):

Banerjee, Debashis. “Intelligent real-time environment and process adaptive radio frequency front-ends for ultra low power applications.” 2015. Web. 25 Jun 2019.

Vancouver:

Banerjee D. Intelligent real-time environment and process adaptive radio frequency front-ends for ultra low power applications. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/53882.

Council of Science Editors:

Banerjee D. Intelligent real-time environment and process adaptive radio frequency front-ends for ultra low power applications. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53882


Georgia Tech

7. Bhatta, Debesh. Algorithms and methodology for incoherent undersampling based acquisition of high speed signal waveforms using low cost test instrumentation.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 The objective of this research is to develop and demonstrate low-complexity, robust, frequency-scalable, wide-band waveform acquisition techniques for testing high speed com- munication systems. High… (more)

Subjects/Keywords: Incoherent undersampling; Low cost testing; Waveform acquisition; High-speed testing

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APA (6th Edition):

Bhatta, D. (2014). Algorithms and methodology for incoherent undersampling based acquisition of high speed signal waveforms using low cost test instrumentation. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54262

Chicago Manual of Style (16th Edition):

Bhatta, Debesh. “Algorithms and methodology for incoherent undersampling based acquisition of high speed signal waveforms using low cost test instrumentation.” 2014. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/54262.

MLA Handbook (7th Edition):

Bhatta, Debesh. “Algorithms and methodology for incoherent undersampling based acquisition of high speed signal waveforms using low cost test instrumentation.” 2014. Web. 25 Jun 2019.

Vancouver:

Bhatta D. Algorithms and methodology for incoherent undersampling based acquisition of high speed signal waveforms using low cost test instrumentation. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/54262.

Council of Science Editors:

Bhatta D. Algorithms and methodology for incoherent undersampling based acquisition of high speed signal waveforms using low cost test instrumentation. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/54262


Georgia Tech

8. Akbay, Selim Sermet. Constraint-driven RF test stimulus generation and built-in test.

Degree: PhD, Electrical and Computer Engineering, 2009, Georgia Tech

 With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has… (more)

Subjects/Keywords: SVM; MARS; BIST; DfT; BOT; Built-off test; BOST; LNA; Mixer; Transmitter; Receiver; TX; RX; Loopback; Loadboard; Supervised learner; Radio frequency integrated circuits; Testing

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APA (6th Edition):

Akbay, S. S. (2009). Constraint-driven RF test stimulus generation and built-in test. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/33913

Chicago Manual of Style (16th Edition):

Akbay, Selim Sermet. “Constraint-driven RF test stimulus generation and built-in test.” 2009. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/33913.

MLA Handbook (7th Edition):

Akbay, Selim Sermet. “Constraint-driven RF test stimulus generation and built-in test.” 2009. Web. 25 Jun 2019.

Vancouver:

Akbay SS. Constraint-driven RF test stimulus generation and built-in test. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/33913.

Council of Science Editors:

Akbay SS. Constraint-driven RF test stimulus generation and built-in test. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/33913


Georgia Tech

9. Cheng, Peng. Reliability of SiGe HBTs for extreme environment and RF applications.

Degree: PhD, Electrical and Computer Engineering, 2010, Georgia Tech

 The objective of the proposed research is to characterize the safe-operating-area of silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) under radiofrequency (RF) operation and extreme environments.… (more)

Subjects/Keywords: Extreme environment; SiGe HBTs; RF; Power amplifier; Bipolar transistors; Heterojunctions; Semiconductors; Silicones; Germanium; Transistors

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APA (6th Edition):

Cheng, P. (2010). Reliability of SiGe HBTs for extreme environment and RF applications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/42836

Chicago Manual of Style (16th Edition):

Cheng, Peng. “Reliability of SiGe HBTs for extreme environment and RF applications.” 2010. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/42836.

MLA Handbook (7th Edition):

Cheng, Peng. “Reliability of SiGe HBTs for extreme environment and RF applications.” 2010. Web. 25 Jun 2019.

Vancouver:

Cheng P. Reliability of SiGe HBTs for extreme environment and RF applications. [Internet] [Doctoral dissertation]. Georgia Tech; 2010. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/42836.

Council of Science Editors:

Cheng P. Reliability of SiGe HBTs for extreme environment and RF applications. [Doctoral Dissertation]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/42836


Georgia Tech

10. Kim, Woongrae. Design and test methodologies with statistical analysis for reliable memory and processor implementations.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The object of the proposed research is to develop comprehensive methodologies, including circuit design, new test methodologies, and statistical failure analysis, to implement reliable microprocessor… (more)

Subjects/Keywords: Reliability; SRAM; DRAM; Processor

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APA (6th Edition):

Kim, W. (2016). Design and test methodologies with statistical analysis for reliable memory and processor implementations. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59737

Chicago Manual of Style (16th Edition):

Kim, Woongrae. “Design and test methodologies with statistical analysis for reliable memory and processor implementations.” 2016. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/59737.

MLA Handbook (7th Edition):

Kim, Woongrae. “Design and test methodologies with statistical analysis for reliable memory and processor implementations.” 2016. Web. 25 Jun 2019.

Vancouver:

Kim W. Design and test methodologies with statistical analysis for reliable memory and processor implementations. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/59737.

Council of Science Editors:

Kim W. Design and test methodologies with statistical analysis for reliable memory and processor implementations. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/59737


Georgia Tech

11. Cha, Soonyoung. Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 The objective of this research is to extract NBTI and GOBD model parameters to enable the estimation of the degradation and the remaining life of… (more)

Subjects/Keywords: Design for reliability and yield enhancement; Device-level and system-level reliability modeling

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APA (6th Edition):

Cha, S. (2017). Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59748

Chicago Manual of Style (16th Edition):

Cha, Soonyoung. “Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system.” 2017. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/59748.

MLA Handbook (7th Edition):

Cha, Soonyoung. “Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system.” 2017. Web. 25 Jun 2019.

Vancouver:

Cha S. Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/59748.

Council of Science Editors:

Cha S. Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59748


Georgia Tech

12. Chen, Te-Hui. High-speed, low cost test platform using FPGA technology.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The object of this research is to develop a low-cost, adaptable testing platform for multi-GHz digital applications, with concentration on the test requirement of advanced… (more)

Subjects/Keywords: FPGA; High-speed testing

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APA (6th Edition):

Chen, T. (2016). High-speed, low cost test platform using FPGA technology. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56246

Chicago Manual of Style (16th Edition):

Chen, Te-Hui. “High-speed, low cost test platform using FPGA technology.” 2016. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/56246.

MLA Handbook (7th Edition):

Chen, Te-Hui. “High-speed, low cost test platform using FPGA technology.” 2016. Web. 25 Jun 2019.

Vancouver:

Chen T. High-speed, low cost test platform using FPGA technology. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/56246.

Council of Science Editors:

Chen T. High-speed, low cost test platform using FPGA technology. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56246

13. Kim, Dae Hyun. Design methodologies for scalable and reliable memory systems.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 The objective of this research is to develop design methodologies for scalable and reliable memory systems in the presence of scalability and reliability issues exacerbated… (more)

Subjects/Keywords: Memory; Scaling; Reliability; System; Circuit; Test; Repair; Design; Error-correcting codes

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APA (6th Edition):

Kim, D. H. (2017). Design methodologies for scalable and reliable memory systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58654

Chicago Manual of Style (16th Edition):

Kim, Dae Hyun. “Design methodologies for scalable and reliable memory systems.” 2017. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/58654.

MLA Handbook (7th Edition):

Kim, Dae Hyun. “Design methodologies for scalable and reliable memory systems.” 2017. Web. 25 Jun 2019.

Vancouver:

Kim DH. Design methodologies for scalable and reliable memory systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/58654.

Council of Science Editors:

Kim DH. Design methodologies for scalable and reliable memory systems. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58654

14. Chen, Chang-Chih. System-level modeling and reliability analysis of microprocessor systems.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 Frontend and backend wearout mechanisms are major reliability concerns for modern microprocessors. In this research, a framework which contains modules for negative bias temperature instability… (more)

Subjects/Keywords: Microprocessor; Reliability; Modeling; Negative bias temperature instability; Positive bias temperature instability; Hot carrier injection; Timing analysis; Aging; SRAM; Cache; Gate oxide breakdown; Wearout; Electromigration; Stress-induced voiding; Stress migration; Time-dependent backend dielectric breakdown

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APA (6th Edition):

Chen, C. (2014). System-level modeling and reliability analysis of microprocessor systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53033

Chicago Manual of Style (16th Edition):

Chen, Chang-Chih. “System-level modeling and reliability analysis of microprocessor systems.” 2014. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/53033.

MLA Handbook (7th Edition):

Chen, Chang-Chih. “System-level modeling and reliability analysis of microprocessor systems.” 2014. Web. 25 Jun 2019.

Vancouver:

Chen C. System-level modeling and reliability analysis of microprocessor systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/53033.

Council of Science Editors:

Chen C. System-level modeling and reliability analysis of microprocessor systems. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/53033

15. Majid, Ashraf Muhammad. Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 Methods for Extending High-Performance Automated Test Equipment (ATE) using Multi-Gigahertz FPGA Technologies Ashraf M. Majid 264 Pages Directed by Dr. David Keezer This thesis presents… (more)

Subjects/Keywords: FPGA based testing; Test enhancement; High-speed digital test; Automated test equipment; Test module; Multi-GHz testing; Field programmable gate arrays; Integrated circuits; Semiconductors

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APA (6th Edition):

Majid, A. M. (2011). Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/39562

Chicago Manual of Style (16th Edition):

Majid, Ashraf Muhammad. “Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies.” 2011. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/39562.

MLA Handbook (7th Edition):

Majid, Ashraf Muhammad. “Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies.” 2011. Web. 25 Jun 2019.

Vancouver:

Majid AM. Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/39562.

Council of Science Editors:

Majid AM. Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/39562

16. Kook, Se Hun. Low-cost testing of high-precision analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 The advent of deep submicron technology has resulted in a new generation of highly integrated mixed-signal system-on-chips (SoCs) and system-on-packages (SoPs). As a result, the… (more)

Subjects/Keywords: Sigma Delta ADC; Incremental ADC; High-resolution ADC testing; Analog-to-digital converters; Test; Data converters; Analog-to-digital converters; Testing

…research work and enjoying fun time with me for the duration of my stay at Georgia Tech. Most of… …love and confidence, I would not have been able to achieve my goals while studying at Georgia… …Tech. At last, I would like to give my special thanks to my fiancé, Joung Min Leah Choi, who… 

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APA (6th Edition):

Kook, S. H. (2011). Low-cost testing of high-precision analog-to-digital converters. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/41170

Chicago Manual of Style (16th Edition):

Kook, Se Hun. “Low-cost testing of high-precision analog-to-digital converters.” 2011. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/41170.

MLA Handbook (7th Edition):

Kook, Se Hun. “Low-cost testing of high-precision analog-to-digital converters.” 2011. Web. 25 Jun 2019.

Vancouver:

Kook SH. Low-cost testing of high-precision analog-to-digital converters. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/41170.

Council of Science Editors:

Kook SH. Low-cost testing of high-precision analog-to-digital converters. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/41170

17. Gray, Carl Edward. An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices.

Degree: PhD, Electrical and Computer Engineering, 2012, Georgia Tech

 This thesis presents methods for developing FPGA-based test solutions that solve the challenges of evaluating source-synchronous and protocol-laden systems and devices at multi-gigabit per second… (more)

Subjects/Keywords: Test architecture; Digital systems; High-speed; Field programmable gate arrays; Gigabit communications; Digital communications Testing; Computer networks Testing

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APA (6th Edition):

Gray, C. E. (2012). An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/44858

Chicago Manual of Style (16th Edition):

Gray, Carl Edward. “An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices.” 2012. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/44858.

MLA Handbook (7th Edition):

Gray, Carl Edward. “An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices.” 2012. Web. 25 Jun 2019.

Vancouver:

Gray CE. An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices. [Internet] [Doctoral dissertation]. Georgia Tech; 2012. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/44858.

Council of Science Editors:

Gray CE. An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices. [Doctoral Dissertation]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/44858

18. Devarakond , Shyam Kumar. Signature driven low cost test, diagnosis and tuning of wireless systems.

Degree: PhD, Electrical and Computer Engineering, 2013, Georgia Tech

 With increased and varied performance demands, it is essential that complex multi-standard radio/systems coexist on a same chip. To have cost and performance benefits, these… (more)

Subjects/Keywords: Analog/RF self-tuning; Spice-level diagnosis; Analog/RF test; Wireless communication systems; Radio; Radio frequency; Mixed signal circuits

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APA (6th Edition):

Devarakond , S. K. (2013). Signature driven low cost test, diagnosis and tuning of wireless systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/47594

Chicago Manual of Style (16th Edition):

Devarakond , Shyam Kumar. “Signature driven low cost test, diagnosis and tuning of wireless systems.” 2013. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/47594.

MLA Handbook (7th Edition):

Devarakond , Shyam Kumar. “Signature driven low cost test, diagnosis and tuning of wireless systems.” 2013. Web. 25 Jun 2019.

Vancouver:

Devarakond SK. Signature driven low cost test, diagnosis and tuning of wireless systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/47594.

Council of Science Editors:

Devarakond SK. Signature driven low cost test, diagnosis and tuning of wireless systems. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/47594

19. Liu, Taizhi. Comprehensive variation-aware aging simulator for logic timing and SRAM stability.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 This research developed a framework which analyzes circuit-level reliability and evaluates the lifetimes of complex systems like state-of-art microprocessors. The novelty of the proposed work… (more)

Subjects/Keywords: Microelectronics; Statistical timing analysis; SRAM stability; Data cache; Circuit aging; BTI; HCI; GOBD

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APA (6th Edition):

Liu, T. (2017). Comprehensive variation-aware aging simulator for logic timing and SRAM stability. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58287

Chicago Manual of Style (16th Edition):

Liu, Taizhi. “Comprehensive variation-aware aging simulator for logic timing and SRAM stability.” 2017. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/58287.

MLA Handbook (7th Edition):

Liu, Taizhi. “Comprehensive variation-aware aging simulator for logic timing and SRAM stability.” 2017. Web. 25 Jun 2019.

Vancouver:

Liu T. Comprehensive variation-aware aging simulator for logic timing and SRAM stability. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/58287.

Council of Science Editors:

Liu T. Comprehensive variation-aware aging simulator for logic timing and SRAM stability. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58287

20. Yang, Kexin. Variation-aware and process-sensitive reliability simulator and its application for analog and digital circuits.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 A reliability simulator for traditional gate oxide time dependent dielectric breakdown (TDDB) and the newly emerged middle-of-line (MOL) TDDB in both digital and analog circuits’… (more)

Subjects/Keywords: Time-dependent dielectric breakdown; Lifetime simulator; Wearout; Frontend-of-line dielectric breakdown; Gate oxide breakdown; Middle-of-line breakdown; Digital circuit; Microprocessor; Reliability

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APA (6th Edition):

Yang, K. (2018). Variation-aware and process-sensitive reliability simulator and its application for analog and digital circuits. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60762

Chicago Manual of Style (16th Edition):

Yang, Kexin. “Variation-aware and process-sensitive reliability simulator and its application for analog and digital circuits.” 2018. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/60762.

MLA Handbook (7th Edition):

Yang, Kexin. “Variation-aware and process-sensitive reliability simulator and its application for analog and digital circuits.” 2018. Web. 25 Jun 2019.

Vancouver:

Yang K. Variation-aware and process-sensitive reliability simulator and its application for analog and digital circuits. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/60762.

Council of Science Editors:

Yang K. Variation-aware and process-sensitive reliability simulator and its application for analog and digital circuits. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60762

21. Aftabjahani, Seyed-Abdollah. Compact variation-aware standard cells for statistical static timing analysis.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 This dissertation reports on a new methodology to characterize and simulate a standard cell library to be used for statistical static timing analysis. A compact… (more)

Subjects/Keywords: Variation-aware standard cell modeling; Process and environmental variation; Variation-aware waveform modeling; Statistical static timing analysis; Static timing analysis; Integrated circuits; Microelectronics; Standard cells

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APA (6th Edition):

Aftabjahani, S. (2011). Compact variation-aware standard cells for statistical static timing analysis. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/41129

Chicago Manual of Style (16th Edition):

Aftabjahani, Seyed-Abdollah. “Compact variation-aware standard cells for statistical static timing analysis.” 2011. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/41129.

MLA Handbook (7th Edition):

Aftabjahani, Seyed-Abdollah. “Compact variation-aware standard cells for statistical static timing analysis.” 2011. Web. 25 Jun 2019.

Vancouver:

Aftabjahani S. Compact variation-aware standard cells for statistical static timing analysis. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/41129.

Council of Science Editors:

Aftabjahani S. Compact variation-aware standard cells for statistical static timing analysis. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/41129

22. Ahmed, Fahad. Invasive and non-invasive detection of bias temperature instability.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 Invasive and non-invasive methods of BTI monitoring and wearout preemption have been proposed. We propose a novel, simple to use, test structure for NBTI /PBTI… (more)

Subjects/Keywords: Wearout; BTI; NBTI; PBTI; Compiler; Monitor; Sensor

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APA (6th Edition):

Ahmed, F. (2014). Invasive and non-invasive detection of bias temperature instability. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52227

Chicago Manual of Style (16th Edition):

Ahmed, Fahad. “Invasive and non-invasive detection of bias temperature instability.” 2014. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/52227.

MLA Handbook (7th Edition):

Ahmed, Fahad. “Invasive and non-invasive detection of bias temperature instability.” 2014. Web. 25 Jun 2019.

Vancouver:

Ahmed F. Invasive and non-invasive detection of bias temperature instability. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/52227.

Council of Science Editors:

Ahmed F. Invasive and non-invasive detection of bias temperature instability. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/52227

23. Mevawalla, Zubin. Process modeling and optimization using industrial semiconductor fabrication data.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 Manufacturers address the distinct operational objectives of product innovation and manufacturing efficiency by having separate fabrication facilities (“fabs”) for development and manufacturing. Additionally, the industrial… (more)

Subjects/Keywords:

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APA (6th Edition):

Mevawalla, Z. (2015). Process modeling and optimization using industrial semiconductor fabrication data. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53382

Chicago Manual of Style (16th Edition):

Mevawalla, Zubin. “Process modeling and optimization using industrial semiconductor fabrication data.” 2015. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/53382.

MLA Handbook (7th Edition):

Mevawalla, Zubin. “Process modeling and optimization using industrial semiconductor fabrication data.” 2015. Web. 25 Jun 2019.

Vancouver:

Mevawalla Z. Process modeling and optimization using industrial semiconductor fabrication data. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/53382.

Council of Science Editors:

Mevawalla Z. Process modeling and optimization using industrial semiconductor fabrication data. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53382

24. Cho, Minki. Design methodology to characterize and compensate for process and temperature variation in digital systems.

Degree: PhD, Electrical and Computer Engineering, 2012, Georgia Tech

 The main objective of this dissertation is to investigate a design methodology that can characterize and compensate for process and temperature variation. First, a design… (more)

Subjects/Keywords: VLSI; Temperature; Process; Variation; Digital system; Three-dimensional integrated circuits; Interconnects (Integrated circuit technology)

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APA (6th Edition):

Cho, M. (2012). Design methodology to characterize and compensate for process and temperature variation in digital systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/50148

Chicago Manual of Style (16th Edition):

Cho, Minki. “Design methodology to characterize and compensate for process and temperature variation in digital systems.” 2012. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/50148.

MLA Handbook (7th Edition):

Cho, Minki. “Design methodology to characterize and compensate for process and temperature variation in digital systems.” 2012. Web. 25 Jun 2019.

Vancouver:

Cho M. Design methodology to characterize and compensate for process and temperature variation in digital systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2012. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/50148.

Council of Science Editors:

Cho M. Design methodology to characterize and compensate for process and temperature variation in digital systems. [Doctoral Dissertation]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/50148


Georgia Tech

25. Douglas, Dale Scott. Flicker noise in cmos lc oscillators.

Degree: MS, Electrical and Computer Engineering, 2008, Georgia Tech

 Sources of flicker noise generation in the cross-coupled negative resistance oscillator (NMOS, PMOS, and CMOS) are explored. Also, prior and current work in the area… (more)

Subjects/Keywords: Adaptive systems; Oscillators; Voltage controlled oscillators; Phase noise; Mixed analog-digital integrated circuits; Oscillators, Electric; Oscillators, Audio-frequency; Wireless communication systems

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APA (6th Edition):

Douglas, D. S. (2008). Flicker noise in cmos lc oscillators. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/26550

Chicago Manual of Style (16th Edition):

Douglas, Dale Scott. “Flicker noise in cmos lc oscillators.” 2008. Masters Thesis, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/26550.

MLA Handbook (7th Edition):

Douglas, Dale Scott. “Flicker noise in cmos lc oscillators.” 2008. Web. 25 Jun 2019.

Vancouver:

Douglas DS. Flicker noise in cmos lc oscillators. [Internet] [Masters thesis]. Georgia Tech; 2008. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/26550.

Council of Science Editors:

Douglas DS. Flicker noise in cmos lc oscillators. [Masters Thesis]. Georgia Tech; 2008. Available from: http://hdl.handle.net/1853/26550


Georgia Tech

26. Lu, Yuan. Design of High-Speed SiGe HBT Circuits for Wideband Transceivers.

Degree: PhD, Electrical and Computer Engineering, 2007, Georgia Tech

 The objective of this work was to design high-speed circuits using silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) and complementary SiGe (C-SiGe) HBTs, as well as… (more)

Subjects/Keywords: High-speed circuits; HBT; SiGe; Silicon-germanium

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APA (6th Edition):

Lu, Y. (2007). Design of High-Speed SiGe HBT Circuits for Wideband Transceivers. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/14533

Chicago Manual of Style (16th Edition):

Lu, Yuan. “Design of High-Speed SiGe HBT Circuits for Wideband Transceivers.” 2007. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/14533.

MLA Handbook (7th Edition):

Lu, Yuan. “Design of High-Speed SiGe HBT Circuits for Wideband Transceivers.” 2007. Web. 25 Jun 2019.

Vancouver:

Lu Y. Design of High-Speed SiGe HBT Circuits for Wideband Transceivers. [Internet] [Doctoral dissertation]. Georgia Tech; 2007. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/14533.

Council of Science Editors:

Lu Y. Design of High-Speed SiGe HBT Circuits for Wideband Transceivers. [Doctoral Dissertation]. Georgia Tech; 2007. Available from: http://hdl.handle.net/1853/14533


Georgia Tech

27. Ashouei, Maryam. Algorithms and Methodology for Post-Manufacture Adaptation to Process Variations and Induced Noise in Deeply Scaled CMOS Technologies.

Degree: PhD, Electrical and Computer Engineering, 2007, Georgia Tech

 In the last two decades, VLSI technology scaling has spurred a rapid growth in the semiconductor industry. With CMOS device dimensions falling below 100 nm,… (more)

Subjects/Keywords: Probablistic compensation; Transient error; CMOS; Process variation; Metal oxide semiconductors, Complementary; Manufacturing processes

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APA (6th Edition):

Ashouei, M. (2007). Algorithms and Methodology for Post-Manufacture Adaptation to Process Variations and Induced Noise in Deeply Scaled CMOS Technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/19859

Chicago Manual of Style (16th Edition):

Ashouei, Maryam. “Algorithms and Methodology for Post-Manufacture Adaptation to Process Variations and Induced Noise in Deeply Scaled CMOS Technologies.” 2007. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/19859.

MLA Handbook (7th Edition):

Ashouei, Maryam. “Algorithms and Methodology for Post-Manufacture Adaptation to Process Variations and Induced Noise in Deeply Scaled CMOS Technologies.” 2007. Web. 25 Jun 2019.

Vancouver:

Ashouei M. Algorithms and Methodology for Post-Manufacture Adaptation to Process Variations and Induced Noise in Deeply Scaled CMOS Technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2007. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/19859.

Council of Science Editors:

Ashouei M. Algorithms and Methodology for Post-Manufacture Adaptation to Process Variations and Induced Noise in Deeply Scaled CMOS Technologies. [Doctoral Dissertation]. Georgia Tech; 2007. Available from: http://hdl.handle.net/1853/19859


Georgia Tech

28. Mukhopadhyay, Rajarshi. Broadband and Low-Power Signal Generation Techniques for Multi-Band Reconfigurable Radios in Silicon-based Technologies.

Degree: PhD, Electrical and Computer Engineering, 2006, Georgia Tech

 Wireless communication is witnessing tremendous growth with the proliferation of various standards covering wide, local, and personal area networks, which operate at different frequency bands.… (more)

Subjects/Keywords: Switched resonators; Active inductors; Voltage-controlled oscillator; VCO; Oscillators; Phase noise; Low-power; Broadband; Wireless communication systems Design and construction; Oscillators, Electric Design and construction

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APA (6th Edition):

Mukhopadhyay, R. (2006). Broadband and Low-Power Signal Generation Techniques for Multi-Band Reconfigurable Radios in Silicon-based Technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/14097

Chicago Manual of Style (16th Edition):

Mukhopadhyay, Rajarshi. “Broadband and Low-Power Signal Generation Techniques for Multi-Band Reconfigurable Radios in Silicon-based Technologies.” 2006. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/14097.

MLA Handbook (7th Edition):

Mukhopadhyay, Rajarshi. “Broadband and Low-Power Signal Generation Techniques for Multi-Band Reconfigurable Radios in Silicon-based Technologies.” 2006. Web. 25 Jun 2019.

Vancouver:

Mukhopadhyay R. Broadband and Low-Power Signal Generation Techniques for Multi-Band Reconfigurable Radios in Silicon-based Technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2006. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/14097.

Council of Science Editors:

Mukhopadhyay R. Broadband and Low-Power Signal Generation Techniques for Multi-Band Reconfigurable Radios in Silicon-based Technologies. [Doctoral Dissertation]. Georgia Tech; 2006. Available from: http://hdl.handle.net/1853/14097


Georgia Tech

29. Han, Dong-Hoon. Built-In Self Test and Calibration of RF Systems for Parametric Failures.

Degree: PhD, Engineering, 2007, Georgia Tech

 This thesis proposes a multifaceted production test and post-silicon yield enhancement framework for RF systems. The three main components of the proposed framework are the… (more)

Subjects/Keywords: Test; BIST; Calibration; RF circuits; Yield; Radio frequency integrated circuits Testing; Radio frequency integrated circuits Design and construction

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APA (6th Edition):

Han, D. (2007). Built-In Self Test and Calibration of RF Systems for Parametric Failures. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/14507

Chicago Manual of Style (16th Edition):

Han, Dong-Hoon. “Built-In Self Test and Calibration of RF Systems for Parametric Failures.” 2007. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/14507.

MLA Handbook (7th Edition):

Han, Dong-Hoon. “Built-In Self Test and Calibration of RF Systems for Parametric Failures.” 2007. Web. 25 Jun 2019.

Vancouver:

Han D. Built-In Self Test and Calibration of RF Systems for Parametric Failures. [Internet] [Doctoral dissertation]. Georgia Tech; 2007. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/14507.

Council of Science Editors:

Han D. Built-In Self Test and Calibration of RF Systems for Parametric Failures. [Doctoral Dissertation]. Georgia Tech; 2007. Available from: http://hdl.handle.net/1853/14507


Georgia Tech

30. Joshi, Ajay Jayant. Wave-Pipelined Multiplexed (WPM) Routing for Gigascale Integration (GSI).

Degree: PhD, Electrical and Computer Engineering, 2006, Georgia Tech

 The main objective of this research is to develop a pervasive wire sharing technique that can be easily applied across the entire range of on-chip… (more)

Subjects/Keywords: Wave-pipelining; Wire sharing; System simulator; Low power; On-chip interconnects

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APA (6th Edition):

Joshi, A. J. (2006). Wave-Pipelined Multiplexed (WPM) Routing for Gigascale Integration (GSI). (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/10549

Chicago Manual of Style (16th Edition):

Joshi, Ajay Jayant. “Wave-Pipelined Multiplexed (WPM) Routing for Gigascale Integration (GSI).” 2006. Doctoral Dissertation, Georgia Tech. Accessed June 25, 2019. http://hdl.handle.net/1853/10549.

MLA Handbook (7th Edition):

Joshi, Ajay Jayant. “Wave-Pipelined Multiplexed (WPM) Routing for Gigascale Integration (GSI).” 2006. Web. 25 Jun 2019.

Vancouver:

Joshi AJ. Wave-Pipelined Multiplexed (WPM) Routing for Gigascale Integration (GSI). [Internet] [Doctoral dissertation]. Georgia Tech; 2006. [cited 2019 Jun 25]. Available from: http://hdl.handle.net/1853/10549.

Council of Science Editors:

Joshi AJ. Wave-Pipelined Multiplexed (WPM) Routing for Gigascale Integration (GSI). [Doctoral Dissertation]. Georgia Tech; 2006. Available from: http://hdl.handle.net/1853/10549

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