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You searched for +publisher:"Georgia Tech" +contributor:("Krishna, Tushar"). Showing records 1 – 30 of 37 total matches.

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Georgia Tech

1. Mannan, Parth. Exploring opportunities and challenges in enabling neuro-evolutionary algorithms in hardware.

Degree: MS, Electrical and Computer Engineering, 2018, Georgia Tech

 Recent advancements in the machine learning algorithms, especially the development of Deep Neural Networks (DNNs) have transformed the landscape of Artificial Intelligence (AI). With every… (more)

Subjects/Keywords: Deep Learning; NeuroEvolution; Architecture; Evolutionary Algorithms; Hardware; Accelerators; Scalability; Distributed System; Collaborative; learning

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APA (6th Edition):

Mannan, P. (2018). Exploring opportunities and challenges in enabling neuro-evolutionary algorithms in hardware. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62255

Chicago Manual of Style (16th Edition):

Mannan, Parth. “Exploring opportunities and challenges in enabling neuro-evolutionary algorithms in hardware.” 2018. Masters Thesis, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/62255.

MLA Handbook (7th Edition):

Mannan, Parth. “Exploring opportunities and challenges in enabling neuro-evolutionary algorithms in hardware.” 2018. Web. 13 Apr 2021.

Vancouver:

Mannan P. Exploring opportunities and challenges in enabling neuro-evolutionary algorithms in hardware. [Internet] [Masters thesis]. Georgia Tech; 2018. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/62255.

Council of Science Editors:

Mannan P. Exploring opportunities and challenges in enabling neuro-evolutionary algorithms in hardware. [Masters Thesis]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/62255


Georgia Tech

2. Ko, Sho. Efficient Pipelined ReRAM-Based Processing-In-Memory Architecture for Convolutional Neural Network Inference.

Degree: MS, Electrical and Computer Engineering, 2020, Georgia Tech

 This research work presents a design of an analog ReRAM-based PIM (processing-in-memory) architecture for fast and efficient CNN (convolutional neural network) inference. For the overall… (more)

Subjects/Keywords: hardware accelerator; ReRAM (resistive random access memory); PIM (processing-in-memory); CNN (convolutional neural network); NoC (network-on-chip); SMART flow control

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APA (6th Edition):

Ko, S. (2020). Efficient Pipelined ReRAM-Based Processing-In-Memory Architecture for Convolutional Neural Network Inference. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62806

Chicago Manual of Style (16th Edition):

Ko, Sho. “Efficient Pipelined ReRAM-Based Processing-In-Memory Architecture for Convolutional Neural Network Inference.” 2020. Masters Thesis, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/62806.

MLA Handbook (7th Edition):

Ko, Sho. “Efficient Pipelined ReRAM-Based Processing-In-Memory Architecture for Convolutional Neural Network Inference.” 2020. Web. 13 Apr 2021.

Vancouver:

Ko S. Efficient Pipelined ReRAM-Based Processing-In-Memory Architecture for Convolutional Neural Network Inference. [Internet] [Masters thesis]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/62806.

Council of Science Editors:

Ko S. Efficient Pipelined ReRAM-Based Processing-In-Memory Architecture for Convolutional Neural Network Inference. [Masters Thesis]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/62806


Georgia Tech

3. Bharadwaj, Vedula Venkata. Scaling address translation in multi-core architectures using low-latency interconnects.

Degree: MS, Electrical and Computer Engineering, 2017, Georgia Tech

 Modern systems employ structures known as Translation Lookaside Buffers(TLB) to accelerate the address translation mechanism. As workloads use ever-increasing memory footprints, TLBs are becoming critical… (more)

Subjects/Keywords: TLB; NUTRA; SMART; Interconnect; Distributed; NUCA

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APA (6th Edition):

Bharadwaj, V. V. (2017). Scaling address translation in multi-core architectures using low-latency interconnects. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59300

Chicago Manual of Style (16th Edition):

Bharadwaj, Vedula Venkata. “Scaling address translation in multi-core architectures using low-latency interconnects.” 2017. Masters Thesis, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/59300.

MLA Handbook (7th Edition):

Bharadwaj, Vedula Venkata. “Scaling address translation in multi-core architectures using low-latency interconnects.” 2017. Web. 13 Apr 2021.

Vancouver:

Bharadwaj VV. Scaling address translation in multi-core architectures using low-latency interconnects. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/59300.

Council of Science Editors:

Bharadwaj VV. Scaling address translation in multi-core architectures using low-latency interconnects. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59300


Georgia Tech

4. She, Xueyuan. Fast and low-precision learning in GPU-accelerated spiking neural network.

Degree: MS, Electrical and Computer Engineering, 2020, Georgia Tech

 Spiking neural network (SNN) uses biologically inspired neuron model coupled with Spike-timing-dependent-plasticity (STDP) to enable unsupervised continuous learning in artificial intelligence (AI) platform. However, current… (more)

Subjects/Keywords: Spiking neural network; GPU acceleration; Computer vision

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APA (6th Edition):

She, X. (2020). Fast and low-precision learning in GPU-accelerated spiking neural network. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/63679

Chicago Manual of Style (16th Edition):

She, Xueyuan. “Fast and low-precision learning in GPU-accelerated spiking neural network.” 2020. Masters Thesis, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/63679.

MLA Handbook (7th Edition):

She, Xueyuan. “Fast and low-precision learning in GPU-accelerated spiking neural network.” 2020. Web. 13 Apr 2021.

Vancouver:

She X. Fast and low-precision learning in GPU-accelerated spiking neural network. [Internet] [Masters thesis]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/63679.

Council of Science Editors:

She X. Fast and low-precision learning in GPU-accelerated spiking neural network. [Masters Thesis]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/63679


Georgia Tech

5. Dasari, Nihar. Modeling of Integrated Voltage Regulator Power delivery systems.

Degree: MS, Electrical and Computer Engineering, 2020, Georgia Tech

 Distributed power delivery poses new power design challenges in modern ICs, requiring circuit level techniques to convert and regulate power at points-of-load (POL), methodological solutions… (more)

Subjects/Keywords: IVR; LDO; Power Delivery

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APA (6th Edition):

Dasari, N. (2020). Modeling of Integrated Voltage Regulator Power delivery systems. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/64139

Chicago Manual of Style (16th Edition):

Dasari, Nihar. “Modeling of Integrated Voltage Regulator Power delivery systems.” 2020. Masters Thesis, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/64139.

MLA Handbook (7th Edition):

Dasari, Nihar. “Modeling of Integrated Voltage Regulator Power delivery systems.” 2020. Web. 13 Apr 2021.

Vancouver:

Dasari N. Modeling of Integrated Voltage Regulator Power delivery systems. [Internet] [Masters thesis]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/64139.

Council of Science Editors:

Dasari N. Modeling of Integrated Voltage Regulator Power delivery systems. [Masters Thesis]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/64139


Georgia Tech

6. Immanuel, Yehowshua U. PLUG-AND-PLAY FOSS ML ACCELERATOR : FROM CONCEPT TO CONCEPTION.

Degree: MS, Electrical and Computer Engineering, 2020, Georgia Tech

 ML accelerators are a fairly new research area and it is important that the archi- tecture community is able to iterate quickly on architectural exploration.… (more)

Subjects/Keywords: DNN Accelerator; AI

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APA (6th Edition):

Immanuel, Y. U. (2020). PLUG-AND-PLAY FOSS ML ACCELERATOR : FROM CONCEPT TO CONCEPTION. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/64210

Chicago Manual of Style (16th Edition):

Immanuel, Yehowshua U. “PLUG-AND-PLAY FOSS ML ACCELERATOR : FROM CONCEPT TO CONCEPTION.” 2020. Masters Thesis, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/64210.

MLA Handbook (7th Edition):

Immanuel, Yehowshua U. “PLUG-AND-PLAY FOSS ML ACCELERATOR : FROM CONCEPT TO CONCEPTION.” 2020. Web. 13 Apr 2021.

Vancouver:

Immanuel YU. PLUG-AND-PLAY FOSS ML ACCELERATOR : FROM CONCEPT TO CONCEPTION. [Internet] [Masters thesis]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/64210.

Council of Science Editors:

Immanuel YU. PLUG-AND-PLAY FOSS ML ACCELERATOR : FROM CONCEPT TO CONCEPTION. [Masters Thesis]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/64210


Georgia Tech

7. Hill, Brennan. Malware capability reverse engineering via coordination with symbolic analysis.

Degree: MS, Electrical and Computer Engineering, 2018, Georgia Tech

 A key feature of cyber attack investigations is to quickly understand the capabilities and payloads of malware so proper countermeasures can be adopted. Unfortunately, due… (more)

Subjects/Keywords: Malware analysis; Symbolic execution; Memory forensics

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APA (6th Edition):

Hill, B. (2018). Malware capability reverse engineering via coordination with symbolic analysis. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62254

Chicago Manual of Style (16th Edition):

Hill, Brennan. “Malware capability reverse engineering via coordination with symbolic analysis.” 2018. Masters Thesis, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/62254.

MLA Handbook (7th Edition):

Hill, Brennan. “Malware capability reverse engineering via coordination with symbolic analysis.” 2018. Web. 13 Apr 2021.

Vancouver:

Hill B. Malware capability reverse engineering via coordination with symbolic analysis. [Internet] [Masters thesis]. Georgia Tech; 2018. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/62254.

Council of Science Editors:

Hill B. Malware capability reverse engineering via coordination with symbolic analysis. [Masters Thesis]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/62254


Georgia Tech

8. Na, Taesik. Energy efficient, secure and noise robust deep learning for the internet of things.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The objective of this research is to design an energy efficient, secure and noise robust deep learning system for the Internet of Things (IoTs). The… (more)

Subjects/Keywords: Deep learning; Adversarial machine learning; Energy efficient training; Noise robust machine learning; IoT

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APA (6th Edition):

Na, T. (2018). Energy efficient, secure and noise robust deep learning for the internet of things. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60293

Chicago Manual of Style (16th Edition):

Na, Taesik. “Energy efficient, secure and noise robust deep learning for the internet of things.” 2018. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/60293.

MLA Handbook (7th Edition):

Na, Taesik. “Energy efficient, secure and noise robust deep learning for the internet of things.” 2018. Web. 13 Apr 2021.

Vancouver:

Na T. Energy efficient, secure and noise robust deep learning for the internet of things. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/60293.

Council of Science Editors:

Na T. Energy efficient, secure and noise robust deep learning for the internet of things. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60293


Georgia Tech

9. Sharma, Hardik. Accelerated deep learning for the edge-to-cloud continuum: A specialized full stack derived from algorithms.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 Advances in high-performance computer architecture design have been a major driver for the rapid evolution of Deep Neural Networks (DNN). Due to their insatiable demand… (more)

Subjects/Keywords: Bit level composability; Dynamic composability; Deep neural networks; Accelerators; DNN; Convolutional neural networks; CNN; Long short-term memory; LSTM; Recurrent neural networks; RNN; Quantization; Bit fusion; DnnWeaver; FPGA; ASIC

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APA (6th Edition):

Sharma, H. (2019). Accelerated deep learning for the edge-to-cloud continuum: A specialized full stack derived from algorithms. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61267

Chicago Manual of Style (16th Edition):

Sharma, Hardik. “Accelerated deep learning for the edge-to-cloud continuum: A specialized full stack derived from algorithms.” 2019. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/61267.

MLA Handbook (7th Edition):

Sharma, Hardik. “Accelerated deep learning for the edge-to-cloud continuum: A specialized full stack derived from algorithms.” 2019. Web. 13 Apr 2021.

Vancouver:

Sharma H. Accelerated deep learning for the edge-to-cloud continuum: A specialized full stack derived from algorithms. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/61267.

Council of Science Editors:

Sharma H. Accelerated deep learning for the edge-to-cloud continuum: A specialized full stack derived from algorithms. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/61267


Georgia Tech

10. Jo, Paul K. Polylithic integration of heterogeneous multi-die enabled by compressible microinterconnects.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 This research proposes and demonstrate 1) a new compliant interconnect that can provide cost-effective and simple fabrication process and allow high-degree of freedom in design… (more)

Subjects/Keywords: Compliant interconnect; Heterogeneous integration; Package; 2.5D; 3D; System-level integration; System-in-package

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APA (6th Edition):

Jo, P. K. (2019). Polylithic integration of heterogeneous multi-die enabled by compressible microinterconnects. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62301

Chicago Manual of Style (16th Edition):

Jo, Paul K. “Polylithic integration of heterogeneous multi-die enabled by compressible microinterconnects.” 2019. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/62301.

MLA Handbook (7th Edition):

Jo, Paul K. “Polylithic integration of heterogeneous multi-die enabled by compressible microinterconnects.” 2019. Web. 13 Apr 2021.

Vancouver:

Jo PK. Polylithic integration of heterogeneous multi-die enabled by compressible microinterconnects. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/62301.

Council of Science Editors:

Jo PK. Polylithic integration of heterogeneous multi-die enabled by compressible microinterconnects. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62301


Georgia Tech

11. Nazari, Alireza. Software profiling via electromagnetic side-channel signal.

Degree: PhD, Computer Science, 2020, Georgia Tech

 This thesis develops general methods to exploit information leaked in Electromagnetic (EM) emanations for profiling software applications. A broad range of computing devices and software… (more)

Subjects/Keywords: Electromagnetic side-channel; Profiling; Memory profiler; Blind source separation; Malware detection

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APA (6th Edition):

Nazari, A. (2020). Software profiling via electromagnetic side-channel signal. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62720

Chicago Manual of Style (16th Edition):

Nazari, Alireza. “Software profiling via electromagnetic side-channel signal.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/62720.

MLA Handbook (7th Edition):

Nazari, Alireza. “Software profiling via electromagnetic side-channel signal.” 2020. Web. 13 Apr 2021.

Vancouver:

Nazari A. Software profiling via electromagnetic side-channel signal. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/62720.

Council of Science Editors:

Nazari A. Software profiling via electromagnetic side-channel signal. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/62720


Georgia Tech

12. Srikanth, Sriseshan. Energy efficient architectures for irregular data streams.

Degree: PhD, Computer Science, 2020, Georgia Tech

 An increasing prevalence of data-irregularity is being seen in applications today, particularly in machine learning, graph analytics, high-performance computing and cybersecurity. Faced with fundamental technology… (more)

Subjects/Keywords: Computer architecture; Sparse; Near data processing; Post-Moore computing; Cache; Memory

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APA (6th Edition):

Srikanth, S. (2020). Energy efficient architectures for irregular data streams. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62757

Chicago Manual of Style (16th Edition):

Srikanth, Sriseshan. “Energy efficient architectures for irregular data streams.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/62757.

MLA Handbook (7th Edition):

Srikanth, Sriseshan. “Energy efficient architectures for irregular data streams.” 2020. Web. 13 Apr 2021.

Vancouver:

Srikanth S. Energy efficient architectures for irregular data streams. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/62757.

Council of Science Editors:

Srikanth S. Energy efficient architectures for irregular data streams. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/62757


Georgia Tech

13. Long, Yun. Energy efficient processing in memory architecture for deep learning computing acceleration.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 The major objective of this research is to make the processing-in-memory (PIM) based deep learning accelerator more practical and more computing efficient. This research particularly… (more)

Subjects/Keywords: Processing-in-memory; Deep learning; Resistive ram; Ferroelectric FET; Machine learning computing acceleration

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APA (6th Edition):

Long, Y. (2019). Energy efficient processing in memory architecture for deep learning computing acceleration. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62311

Chicago Manual of Style (16th Edition):

Long, Yun. “Energy efficient processing in memory architecture for deep learning computing acceleration.” 2019. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/62311.

MLA Handbook (7th Edition):

Long, Yun. “Energy efficient processing in memory architecture for deep learning computing acceleration.” 2019. Web. 13 Apr 2021.

Vancouver:

Long Y. Energy efficient processing in memory architecture for deep learning computing acceleration. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/62311.

Council of Science Editors:

Long Y. Energy efficient processing in memory architecture for deep learning computing acceleration. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62311


Georgia Tech

14. Kang, Suk Chan. Optimizing high locality memory references in cache coherent shared memory multi-core processors.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 Optimizing memory references has been a primary research area of computer systems ever since the advent of the stored program computers. The objective of this… (more)

Subjects/Keywords: Shared memory system; Cache coherence; Memory consistency; Synchronization

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APA (6th Edition):

Kang, S. C. (2019). Optimizing high locality memory references in cache coherent shared memory multi-core processors. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62641

Chicago Manual of Style (16th Edition):

Kang, Suk Chan. “Optimizing high locality memory references in cache coherent shared memory multi-core processors.” 2019. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/62641.

MLA Handbook (7th Edition):

Kang, Suk Chan. “Optimizing high locality memory references in cache coherent shared memory multi-core processors.” 2019. Web. 13 Apr 2021.

Vancouver:

Kang SC. Optimizing high locality memory references in cache coherent shared memory multi-core processors. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/62641.

Council of Science Editors:

Kang SC. Optimizing high locality memory references in cache coherent shared memory multi-core processors. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62641


Georgia Tech

15. Amir, Mohammad Faisal. Design methodology for 3d-stacked imaging systems with integrated deep learning.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The Internet of Things (IoT) revolution has brought along with it billions of always on, always connected devices and sensors, associated with which are huge… (more)

Subjects/Keywords: Neural networks; Image sensor; Energy harvesting; Deep learning; 3D integration

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APA (6th Edition):

Amir, M. F. (2018). Design methodology for 3d-stacked imaging systems with integrated deep learning. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61609

Chicago Manual of Style (16th Edition):

Amir, Mohammad Faisal. “Design methodology for 3d-stacked imaging systems with integrated deep learning.” 2018. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/61609.

MLA Handbook (7th Edition):

Amir, Mohammad Faisal. “Design methodology for 3d-stacked imaging systems with integrated deep learning.” 2018. Web. 13 Apr 2021.

Vancouver:

Amir MF. Design methodology for 3d-stacked imaging systems with integrated deep learning. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/61609.

Council of Science Editors:

Amir MF. Design methodology for 3d-stacked imaging systems with integrated deep learning. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/61609


Georgia Tech

16. Maass, Steffen Alexander. Systems abstractions for big data processing on a single machine.

Degree: PhD, Computer Science, 2019, Georgia Tech

 Large-scale internet services, such as Facebook or Google, are using clusters of many servers for problems such as search, machine learning, and social networks. However,… (more)

Subjects/Keywords: Runtime system; Big data; Graph analytics; Performance optimization; Incremental processing; Heterogeneous computing

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APA (6th Edition):

Maass, S. A. (2019). Systems abstractions for big data processing on a single machine. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61679

Chicago Manual of Style (16th Edition):

Maass, Steffen Alexander. “Systems abstractions for big data processing on a single machine.” 2019. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/61679.

MLA Handbook (7th Edition):

Maass, Steffen Alexander. “Systems abstractions for big data processing on a single machine.” 2019. Web. 13 Apr 2021.

Vancouver:

Maass SA. Systems abstractions for big data processing on a single machine. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/61679.

Council of Science Editors:

Maass SA. Systems abstractions for big data processing on a single machine. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/61679


Georgia Tech

17. Kersey, Chad Daniel. A multi-paradigm C++-based hardware description language.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 A generative hardware description library for C++, the CHDL Hardware Design Library or CHDL, along with a body of supporting libraries and a description of… (more)

Subjects/Keywords: Hardware description language; HDL; Domain-specific language; High-level synthesis

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APA (6th Edition):

Kersey, C. D. (2019). A multi-paradigm C++-based hardware description language. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62342

Chicago Manual of Style (16th Edition):

Kersey, Chad Daniel. “A multi-paradigm C++-based hardware description language.” 2019. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/62342.

MLA Handbook (7th Edition):

Kersey, Chad Daniel. “A multi-paradigm C++-based hardware description language.” 2019. Web. 13 Apr 2021.

Vancouver:

Kersey CD. A multi-paradigm C++-based hardware description language. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/62342.

Council of Science Editors:

Kersey CD. A multi-paradigm C++-based hardware description language. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62342


Georgia Tech

18. Hossen, Md Obaidul. Power delivery and thermal considerations for 2.5-D and 3-D integration technologies.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 Owing to advanced technologies, the total power density in a high-performance computing system is expected to increase beyond 100 W/cm2; power delivery becomes a critical… (more)

Subjects/Keywords: Power delivery network; Heterogeneous Integration

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APA (6th Edition):

Hossen, M. O. (2019). Power delivery and thermal considerations for 2.5-D and 3-D integration technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62346

Chicago Manual of Style (16th Edition):

Hossen, Md Obaidul. “Power delivery and thermal considerations for 2.5-D and 3-D integration technologies.” 2019. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/62346.

MLA Handbook (7th Edition):

Hossen, Md Obaidul. “Power delivery and thermal considerations for 2.5-D and 3-D integration technologies.” 2019. Web. 13 Apr 2021.

Vancouver:

Hossen MO. Power delivery and thermal considerations for 2.5-D and 3-D integration technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/62346.

Council of Science Editors:

Hossen MO. Power delivery and thermal considerations for 2.5-D and 3-D integration technologies. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62346


Georgia Tech

19. Hassan, Syed Minhaj. Exploiting on-chip memory concurrency in 3d manycore architectures.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The objective of this thesis is to optimize the uncore of 3D many-core architectures. More specifically, we note that technology trends point to large increases… (more)

Subjects/Keywords: 3D memory systems; Network-on-chip; 3D system thermal analysis; Memory-level parallelism; DRAM

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APA (6th Edition):

Hassan, S. M. (2016). Exploiting on-chip memory concurrency in 3d manycore architectures. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56251

Chicago Manual of Style (16th Edition):

Hassan, Syed Minhaj. “Exploiting on-chip memory concurrency in 3d manycore architectures.” 2016. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/56251.

MLA Handbook (7th Edition):

Hassan, Syed Minhaj. “Exploiting on-chip memory concurrency in 3d manycore architectures.” 2016. Web. 13 Apr 2021.

Vancouver:

Hassan SM. Exploiting on-chip memory concurrency in 3d manycore architectures. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/56251.

Council of Science Editors:

Hassan SM. Exploiting on-chip memory concurrency in 3d manycore architectures. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56251


Georgia Tech

20. Wang, Jin. Acceleration and optimization of dynamic parallelism for irregular applications on GPUs.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The objective of this thesis is the development, implementation and optimization of a GPU execution model extension that efficiently supports time-varying, nested, fine-grained dynamic parallelism… (more)

Subjects/Keywords: General-purpose GPU; Dynamic parallelism; Irregular applications

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APA (6th Edition):

Wang, J. (2016). Acceleration and optimization of dynamic parallelism for irregular applications on GPUs. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56294

Chicago Manual of Style (16th Edition):

Wang, Jin. “Acceleration and optimization of dynamic parallelism for irregular applications on GPUs.” 2016. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/56294.

MLA Handbook (7th Edition):

Wang, Jin. “Acceleration and optimization of dynamic parallelism for irregular applications on GPUs.” 2016. Web. 13 Apr 2021.

Vancouver:

Wang J. Acceleration and optimization of dynamic parallelism for irregular applications on GPUs. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/56294.

Council of Science Editors:

Wang J. Acceleration and optimization of dynamic parallelism for irregular applications on GPUs. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56294


Georgia Tech

21. Wahby, William. Theoretical and experimental investigations of connectivity in three-dimensional integrated circuits.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 Three-dimensional integration, in which integrated circuits (ICs) are stacked directly atop one another to reduce interconnect length, is an attractive method for achieving continued performance… (more)

Subjects/Keywords: 3DIC; Interconnect; Thermal

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APA (6th Edition):

Wahby, W. (2018). Theoretical and experimental investigations of connectivity in three-dimensional integrated circuits. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61184

Chicago Manual of Style (16th Edition):

Wahby, William. “Theoretical and experimental investigations of connectivity in three-dimensional integrated circuits.” 2018. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/61184.

MLA Handbook (7th Edition):

Wahby, William. “Theoretical and experimental investigations of connectivity in three-dimensional integrated circuits.” 2018. Web. 13 Apr 2021.

Vancouver:

Wahby W. Theoretical and experimental investigations of connectivity in three-dimensional integrated circuits. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/61184.

Council of Science Editors:

Wahby W. Theoretical and experimental investigations of connectivity in three-dimensional integrated circuits. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/61184


Georgia Tech

22. Parasar, Mayank. Subactive techniques for guaranteeing routing and protocol deadlock freedom in interconnection networks.

Degree: PhD, Electrical and Computer Engineering, 2020, Georgia Tech

 Interconnection networks are the communication backbone for any system. They occur at various scales: from on-chip networks between processing cores, to supercomputers between compute nodes,… (more)

Subjects/Keywords: Interconnection network; Routing deadlock; Protocol deadlock; Proactive; Reactive; Subactive; Network on chip; Computer architecture

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APA (6th Edition):

Parasar, M. (2020). Subactive techniques for guaranteeing routing and protocol deadlock freedom in interconnection networks. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/63654

Chicago Manual of Style (16th Edition):

Parasar, Mayank. “Subactive techniques for guaranteeing routing and protocol deadlock freedom in interconnection networks.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/63654.

MLA Handbook (7th Edition):

Parasar, Mayank. “Subactive techniques for guaranteeing routing and protocol deadlock freedom in interconnection networks.” 2020. Web. 13 Apr 2021.

Vancouver:

Parasar M. Subactive techniques for guaranteeing routing and protocol deadlock freedom in interconnection networks. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/63654.

Council of Science Editors:

Parasar M. Subactive techniques for guaranteeing routing and protocol deadlock freedom in interconnection networks. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/63654


Georgia Tech

23. Kwon, Hyouk Jun. Data- and communication-centric approaches to model and design flexible deep neural network accelerators.

Degree: PhD, Computer Science, 2020, Georgia Tech

 Deep neural network (DNN) accelerators, which are specialized hardware for DNN inferences, enabled energy-efficient and low-latency DNN inferences. To maximize the efficiency (energy efficiency, latency,… (more)

Subjects/Keywords: DNN accelerator; DNN dataflow; DNN mapping; Flexible mapping accelerator

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APA (6th Edition):

Kwon, H. J. (2020). Data- and communication-centric approaches to model and design flexible deep neural network accelerators. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/63663

Chicago Manual of Style (16th Edition):

Kwon, Hyouk Jun. “Data- and communication-centric approaches to model and design flexible deep neural network accelerators.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/63663.

MLA Handbook (7th Edition):

Kwon, Hyouk Jun. “Data- and communication-centric approaches to model and design flexible deep neural network accelerators.” 2020. Web. 13 Apr 2021.

Vancouver:

Kwon HJ. Data- and communication-centric approaches to model and design flexible deep neural network accelerators. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/63663.

Council of Science Editors:

Kwon HJ. Data- and communication-centric approaches to model and design flexible deep neural network accelerators. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/63663


Georgia Tech

24. Mururu, Girish. Compiler Guided Scheduling : A Cross-Stack Approach For Performance Elicitation.

Degree: PhD, Computer Science, 2020, Georgia Tech

 Modern software executes on multi-core systems that share resources like several levels of memory hierarchy (caches, main memory, secondary storage), I/O devices, and network interfaces.… (more)

Subjects/Keywords: Compilers; Scheduling; Co-location

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APA (6th Edition):

Mururu, G. (2020). Compiler Guided Scheduling : A Cross-Stack Approach For Performance Elicitation. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/64096

Chicago Manual of Style (16th Edition):

Mururu, Girish. “Compiler Guided Scheduling : A Cross-Stack Approach For Performance Elicitation.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/64096.

MLA Handbook (7th Edition):

Mururu, Girish. “Compiler Guided Scheduling : A Cross-Stack Approach For Performance Elicitation.” 2020. Web. 13 Apr 2021.

Vancouver:

Mururu G. Compiler Guided Scheduling : A Cross-Stack Approach For Performance Elicitation. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/64096.

Council of Science Editors:

Mururu G. Compiler Guided Scheduling : A Cross-Stack Approach For Performance Elicitation. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/64096


Georgia Tech

25. Chatarasi, Prasanth. ADVANCING COMPILER OPTIMIZATIONS FOR GENERAL-PURPOSE & DOMAIN-SPECIFIC PARALLEL ARCHITECTURES.

Degree: PhD, Computer Science, 2020, Georgia Tech

 Computer hardware is undergoing a major disruption as we approach the end of Moore’s law, in the form of new advancements to general-purpose and domain-specific… (more)

Subjects/Keywords: Compiler Optimizations; General-Purpose Architectures; Domain-Specific Architectures; Deep Learning; Graph Analytics; Accelerators; Polyhedral Model

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APA (6th Edition):

Chatarasi, P. (2020). ADVANCING COMPILER OPTIMIZATIONS FOR GENERAL-PURPOSE & DOMAIN-SPECIFIC PARALLEL ARCHITECTURES. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/64099

Chicago Manual of Style (16th Edition):

Chatarasi, Prasanth. “ADVANCING COMPILER OPTIMIZATIONS FOR GENERAL-PURPOSE & DOMAIN-SPECIFIC PARALLEL ARCHITECTURES.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/64099.

MLA Handbook (7th Edition):

Chatarasi, Prasanth. “ADVANCING COMPILER OPTIMIZATIONS FOR GENERAL-PURPOSE & DOMAIN-SPECIFIC PARALLEL ARCHITECTURES.” 2020. Web. 13 Apr 2021.

Vancouver:

Chatarasi P. ADVANCING COMPILER OPTIMIZATIONS FOR GENERAL-PURPOSE & DOMAIN-SPECIFIC PARALLEL ARCHITECTURES. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/64099.

Council of Science Editors:

Chatarasi P. ADVANCING COMPILER OPTIMIZATIONS FOR GENERAL-PURPOSE & DOMAIN-SPECIFIC PARALLEL ARCHITECTURES. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/64099


Georgia Tech

26. Tannu, Swamit. Software Techniques to Mitigate Errors on Noisy Quantum Computers.

Degree: PhD, Electrical and Computer Engineering, 2020, Georgia Tech

 Quantum computers are domain-specific accelerators that can provide a large speedup for important problems. Quantum computers with few tens of qubits have already been demonstrated,… (more)

Subjects/Keywords: Quantum Computing; Quantum Software; Quantum Compilation; Noisy Intermediate Scale Quantum Computers

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APA (6th Edition):

Tannu, S. (2020). Software Techniques to Mitigate Errors on Noisy Quantum Computers. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/64123

Chicago Manual of Style (16th Edition):

Tannu, Swamit. “Software Techniques to Mitigate Errors on Noisy Quantum Computers.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/64123.

MLA Handbook (7th Edition):

Tannu, Swamit. “Software Techniques to Mitigate Errors on Noisy Quantum Computers.” 2020. Web. 13 Apr 2021.

Vancouver:

Tannu S. Software Techniques to Mitigate Errors on Noisy Quantum Computers. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/64123.

Council of Science Editors:

Tannu S. Software Techniques to Mitigate Errors on Noisy Quantum Computers. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/64123


Georgia Tech

27. Bak, Seonmyeong. Runtime Approaches to Improve the Efficiency of Hybrid and Irregular Applications.

Degree: PhD, Computer Science, 2020, Georgia Tech

 On-node parallelism has increased significantly in high-performance computing systems. This huge amount of parallelism can be used to speed up regular paral- lel applications relatively… (more)

Subjects/Keywords: High Performance Computing; Runtime Systems; Load Balancing; Task-based programming models

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APA (6th Edition):

Bak, S. (2020). Runtime Approaches to Improve the Efficiency of Hybrid and Irregular Applications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/64198

Chicago Manual of Style (16th Edition):

Bak, Seonmyeong. “Runtime Approaches to Improve the Efficiency of Hybrid and Irregular Applications.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/64198.

MLA Handbook (7th Edition):

Bak, Seonmyeong. “Runtime Approaches to Improve the Efficiency of Hybrid and Irregular Applications.” 2020. Web. 13 Apr 2021.

Vancouver:

Bak S. Runtime Approaches to Improve the Efficiency of Hybrid and Irregular Applications. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/64198.

Council of Science Editors:

Bak S. Runtime Approaches to Improve the Efficiency of Hybrid and Irregular Applications. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/64198

28. Ko, Jong Hwan. Resource-aware and robust image processing for intelligent sensor systems.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The objective of this research is to design resource-aware and robust image processing algorithms, system architecture, and hardware implementation for intelligent image sensor systems in… (more)

Subjects/Keywords: Image processing; Deep learning; Sensor systems

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APA (6th Edition):

Ko, J. H. (2018). Resource-aware and robust image processing for intelligent sensor systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60198

Chicago Manual of Style (16th Edition):

Ko, Jong Hwan. “Resource-aware and robust image processing for intelligent sensor systems.” 2018. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/60198.

MLA Handbook (7th Edition):

Ko, Jong Hwan. “Resource-aware and robust image processing for intelligent sensor systems.” 2018. Web. 13 Apr 2021.

Vancouver:

Ko JH. Resource-aware and robust image processing for intelligent sensor systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/60198.

Council of Science Editors:

Ko JH. Resource-aware and robust image processing for intelligent sensor systems. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/60198

29. Garg, Kartikay. Near-memory primitive support and infratructure for sparse algorithm.

Degree: MS, Electrical and Computer Engineering, 2017, Georgia Tech

 This thesis introduces an approach to solving the problem of memory latency performance penalties with traditional accelerators. By introducing simple near-data-processing (NDP) accelerators for primitives… (more)

Subjects/Keywords: Processing in memory (PIM); Near data processing (NDP); 3D-stacked memory; HMC; FPGA; SuperLU

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APA (6th Edition):

Garg, K. (2017). Near-memory primitive support and infratructure for sparse algorithm. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58343

Chicago Manual of Style (16th Edition):

Garg, Kartikay. “Near-memory primitive support and infratructure for sparse algorithm.” 2017. Masters Thesis, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/58343.

MLA Handbook (7th Edition):

Garg, Kartikay. “Near-memory primitive support and infratructure for sparse algorithm.” 2017. Web. 13 Apr 2021.

Vancouver:

Garg K. Near-memory primitive support and infratructure for sparse algorithm. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/58343.

Council of Science Editors:

Garg K. Near-memory primitive support and infratructure for sparse algorithm. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58343

30. Ramrakhyani, Aniruddh. Aniruddh Ramrakhyani Thesis.

Degree: MS, Electrical and Computer Engineering, 2017, Georgia Tech

 The demise of Dennard Scaling and the continuance of Moore’s law has provided us with shrinking chip dimensions and higher on-chip transistor density at the… (more)

Subjects/Keywords: Deadlocks; NoC; Routing; Computer architecture; Dark Silicon; Power Gating; Resiliency; Topology

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APA (6th Edition):

Ramrakhyani, A. (2017). Aniruddh Ramrakhyani Thesis. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58331

Chicago Manual of Style (16th Edition):

Ramrakhyani, Aniruddh. “Aniruddh Ramrakhyani Thesis.” 2017. Masters Thesis, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/58331.

MLA Handbook (7th Edition):

Ramrakhyani, Aniruddh. “Aniruddh Ramrakhyani Thesis.” 2017. Web. 13 Apr 2021.

Vancouver:

Ramrakhyani A. Aniruddh Ramrakhyani Thesis. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/58331.

Council of Science Editors:

Ramrakhyani A. Aniruddh Ramrakhyani Thesis. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58331

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