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You searched for +publisher:"Georgia Tech" +contributor:("Kim, Hyesoon"). Showing records 1 – 30 of 79 total matches.

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Georgia Tech

1. Mannan, Parth. Exploring opportunities and challenges in enabling neuro-evolutionary algorithms in hardware.

Degree: MS, Electrical and Computer Engineering, 2018, Georgia Tech

 Recent advancements in the machine learning algorithms, especially the development of Deep Neural Networks (DNNs) have transformed the landscape of Artificial Intelligence (AI). With every… (more)

Subjects/Keywords: Deep Learning; NeuroEvolution; Architecture; Evolutionary Algorithms; Hardware; Accelerators; Scalability; Distributed System; Collaborative; learning

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APA (6th Edition):

Mannan, P. (2018). Exploring opportunities and challenges in enabling neuro-evolutionary algorithms in hardware. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62255

Chicago Manual of Style (16th Edition):

Mannan, Parth. “Exploring opportunities and challenges in enabling neuro-evolutionary algorithms in hardware.” 2018. Masters Thesis, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/62255.

MLA Handbook (7th Edition):

Mannan, Parth. “Exploring opportunities and challenges in enabling neuro-evolutionary algorithms in hardware.” 2018. Web. 13 Apr 2021.

Vancouver:

Mannan P. Exploring opportunities and challenges in enabling neuro-evolutionary algorithms in hardware. [Internet] [Masters thesis]. Georgia Tech; 2018. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/62255.

Council of Science Editors:

Mannan P. Exploring opportunities and challenges in enabling neuro-evolutionary algorithms in hardware. [Masters Thesis]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/62255


Georgia Tech

2. Bharadwaj, Vedula Venkata. Scaling address translation in multi-core architectures using low-latency interconnects.

Degree: MS, Electrical and Computer Engineering, 2017, Georgia Tech

 Modern systems employ structures known as Translation Lookaside Buffers(TLB) to accelerate the address translation mechanism. As workloads use ever-increasing memory footprints, TLBs are becoming critical… (more)

Subjects/Keywords: TLB; NUTRA; SMART; Interconnect; Distributed; NUCA

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APA (6th Edition):

Bharadwaj, V. V. (2017). Scaling address translation in multi-core architectures using low-latency interconnects. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59300

Chicago Manual of Style (16th Edition):

Bharadwaj, Vedula Venkata. “Scaling address translation in multi-core architectures using low-latency interconnects.” 2017. Masters Thesis, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/59300.

MLA Handbook (7th Edition):

Bharadwaj, Vedula Venkata. “Scaling address translation in multi-core architectures using low-latency interconnects.” 2017. Web. 13 Apr 2021.

Vancouver:

Bharadwaj VV. Scaling address translation in multi-core architectures using low-latency interconnects. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/59300.

Council of Science Editors:

Bharadwaj VV. Scaling address translation in multi-core architectures using low-latency interconnects. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59300


Georgia Tech

3. Gupta, Meghana. Code generation and adaptive control divergence management for light weight SIMT processors.

Degree: MS, Computer Science, 2016, Georgia Tech

 The energy costs of data movement are limiting the performance scaling of future generations of high performance computing architectures targeted to data intensive applications. The… (more)

Subjects/Keywords: Compiler; SIMT; Control divergence

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APA (6th Edition):

Gupta, M. (2016). Code generation and adaptive control divergence management for light weight SIMT processors. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55044

Chicago Manual of Style (16th Edition):

Gupta, Meghana. “Code generation and adaptive control divergence management for light weight SIMT processors.” 2016. Masters Thesis, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/55044.

MLA Handbook (7th Edition):

Gupta, Meghana. “Code generation and adaptive control divergence management for light weight SIMT processors.” 2016. Web. 13 Apr 2021.

Vancouver:

Gupta M. Code generation and adaptive control divergence management for light weight SIMT processors. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/55044.

Council of Science Editors:

Gupta M. Code generation and adaptive control divergence management for light weight SIMT processors. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55044


Georgia Tech

4. She, Xueyuan. Fast and low-precision learning in GPU-accelerated spiking neural network.

Degree: MS, Electrical and Computer Engineering, 2020, Georgia Tech

 Spiking neural network (SNN) uses biologically inspired neuron model coupled with Spike-timing-dependent-plasticity (STDP) to enable unsupervised continuous learning in artificial intelligence (AI) platform. However, current… (more)

Subjects/Keywords: Spiking neural network; GPU acceleration; Computer vision

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APA (6th Edition):

She, X. (2020). Fast and low-precision learning in GPU-accelerated spiking neural network. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/63679

Chicago Manual of Style (16th Edition):

She, Xueyuan. “Fast and low-precision learning in GPU-accelerated spiking neural network.” 2020. Masters Thesis, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/63679.

MLA Handbook (7th Edition):

She, Xueyuan. “Fast and low-precision learning in GPU-accelerated spiking neural network.” 2020. Web. 13 Apr 2021.

Vancouver:

She X. Fast and low-precision learning in GPU-accelerated spiking neural network. [Internet] [Masters thesis]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/63679.

Council of Science Editors:

She X. Fast and low-precision learning in GPU-accelerated spiking neural network. [Masters Thesis]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/63679


Georgia Tech

5. Dasari, Nihar. Modeling of Integrated Voltage Regulator Power delivery systems.

Degree: MS, Electrical and Computer Engineering, 2020, Georgia Tech

 Distributed power delivery poses new power design challenges in modern ICs, requiring circuit level techniques to convert and regulate power at points-of-load (POL), methodological solutions… (more)

Subjects/Keywords: IVR; LDO; Power Delivery

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APA (6th Edition):

Dasari, N. (2020). Modeling of Integrated Voltage Regulator Power delivery systems. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/64139

Chicago Manual of Style (16th Edition):

Dasari, Nihar. “Modeling of Integrated Voltage Regulator Power delivery systems.” 2020. Masters Thesis, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/64139.

MLA Handbook (7th Edition):

Dasari, Nihar. “Modeling of Integrated Voltage Regulator Power delivery systems.” 2020. Web. 13 Apr 2021.

Vancouver:

Dasari N. Modeling of Integrated Voltage Regulator Power delivery systems. [Internet] [Masters thesis]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/64139.

Council of Science Editors:

Dasari N. Modeling of Integrated Voltage Regulator Power delivery systems. [Masters Thesis]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/64139


Georgia Tech

6. Immanuel, Yehowshua U. PLUG-AND-PLAY FOSS ML ACCELERATOR : FROM CONCEPT TO CONCEPTION.

Degree: MS, Electrical and Computer Engineering, 2020, Georgia Tech

 ML accelerators are a fairly new research area and it is important that the archi- tecture community is able to iterate quickly on architectural exploration.… (more)

Subjects/Keywords: DNN Accelerator; AI

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APA (6th Edition):

Immanuel, Y. U. (2020). PLUG-AND-PLAY FOSS ML ACCELERATOR : FROM CONCEPT TO CONCEPTION. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/64210

Chicago Manual of Style (16th Edition):

Immanuel, Yehowshua U. “PLUG-AND-PLAY FOSS ML ACCELERATOR : FROM CONCEPT TO CONCEPTION.” 2020. Masters Thesis, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/64210.

MLA Handbook (7th Edition):

Immanuel, Yehowshua U. “PLUG-AND-PLAY FOSS ML ACCELERATOR : FROM CONCEPT TO CONCEPTION.” 2020. Web. 13 Apr 2021.

Vancouver:

Immanuel YU. PLUG-AND-PLAY FOSS ML ACCELERATOR : FROM CONCEPT TO CONCEPTION. [Internet] [Masters thesis]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/64210.

Council of Science Editors:

Immanuel YU. PLUG-AND-PLAY FOSS ML ACCELERATOR : FROM CONCEPT TO CONCEPTION. [Masters Thesis]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/64210


Georgia Tech

7. Saeed, Ifrah. A portable relational algebra library for high performance data-intensive query processing.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 A growing number of industries are turning to data warehousing applications such as forecasting and risk assessment to process large volumes of data. These data… (more)

Subjects/Keywords: Data-intensive query processing; RA operators; OpenCL; GPUs; CPUs; Graphics processing units; Data warehousing; Big data; Relation algebras

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APA (6th Edition):

Saeed, I. (2014). A portable relational algebra library for high performance data-intensive query processing. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51967

Chicago Manual of Style (16th Edition):

Saeed, Ifrah. “A portable relational algebra library for high performance data-intensive query processing.” 2014. Masters Thesis, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/51967.

MLA Handbook (7th Edition):

Saeed, Ifrah. “A portable relational algebra library for high performance data-intensive query processing.” 2014. Web. 13 Apr 2021.

Vancouver:

Saeed I. A portable relational algebra library for high performance data-intensive query processing. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/51967.

Council of Science Editors:

Saeed I. A portable relational algebra library for high performance data-intensive query processing. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51967


Georgia Tech

8. Sharma, Hardik. Accelerated deep learning for the edge-to-cloud continuum: A specialized full stack derived from algorithms.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 Advances in high-performance computer architecture design have been a major driver for the rapid evolution of Deep Neural Networks (DNN). Due to their insatiable demand… (more)

Subjects/Keywords: Bit level composability; Dynamic composability; Deep neural networks; Accelerators; DNN; Convolutional neural networks; CNN; Long short-term memory; LSTM; Recurrent neural networks; RNN; Quantization; Bit fusion; DnnWeaver; FPGA; ASIC

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APA (6th Edition):

Sharma, H. (2019). Accelerated deep learning for the edge-to-cloud continuum: A specialized full stack derived from algorithms. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61267

Chicago Manual of Style (16th Edition):

Sharma, Hardik. “Accelerated deep learning for the edge-to-cloud continuum: A specialized full stack derived from algorithms.” 2019. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/61267.

MLA Handbook (7th Edition):

Sharma, Hardik. “Accelerated deep learning for the edge-to-cloud continuum: A specialized full stack derived from algorithms.” 2019. Web. 13 Apr 2021.

Vancouver:

Sharma H. Accelerated deep learning for the edge-to-cloud continuum: A specialized full stack derived from algorithms. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/61267.

Council of Science Editors:

Sharma H. Accelerated deep learning for the edge-to-cloud continuum: A specialized full stack derived from algorithms. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/61267


Georgia Tech

9. Chang, Kyungwook. Design and tool solutions for energy-efficient reliable monolithic 3D ICs.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 The objective of this dissertation is to analyze and identify the benefits and challenges of energy-efficient and reliable monolithic 3D (M3D) ICs, and to develop… (more)

Subjects/Keywords: Monolithic 3D IC; CAD; Physical design; Low power design; High performance design; Power supply integrity; Deep neural network

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APA (6th Edition):

Chang, K. (2019). Design and tool solutions for energy-efficient reliable monolithic 3D ICs. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62672

Chicago Manual of Style (16th Edition):

Chang, Kyungwook. “Design and tool solutions for energy-efficient reliable monolithic 3D ICs.” 2019. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/62672.

MLA Handbook (7th Edition):

Chang, Kyungwook. “Design and tool solutions for energy-efficient reliable monolithic 3D ICs.” 2019. Web. 13 Apr 2021.

Vancouver:

Chang K. Design and tool solutions for energy-efficient reliable monolithic 3D ICs. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/62672.

Council of Science Editors:

Chang K. Design and tool solutions for energy-efficient reliable monolithic 3D ICs. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62672


Georgia Tech

10. Kim, Hyojong. Techniques to mitigate performance impact of off-chip data migrations in modern GPU computing.

Degree: PhD, Computer Science, 2020, Georgia Tech

 In response to growing compute and memory capacity requirements, modern systems are equipped to distribute the work over multiple GPUs and pool the memory from… (more)

Subjects/Keywords: GPUs; Data migrations; Unified memory; Multi-GPUs

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APA (6th Edition):

Kim, H. (2020). Techniques to mitigate performance impact of off-chip data migrations in modern GPU computing. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62741

Chicago Manual of Style (16th Edition):

Kim, Hyojong. “Techniques to mitigate performance impact of off-chip data migrations in modern GPU computing.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/62741.

MLA Handbook (7th Edition):

Kim, Hyojong. “Techniques to mitigate performance impact of off-chip data migrations in modern GPU computing.” 2020. Web. 13 Apr 2021.

Vancouver:

Kim H. Techniques to mitigate performance impact of off-chip data migrations in modern GPU computing. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/62741.

Council of Science Editors:

Kim H. Techniques to mitigate performance impact of off-chip data migrations in modern GPU computing. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/62741


Georgia Tech

11. Srikanth, Sriseshan. Energy efficient architectures for irregular data streams.

Degree: PhD, Computer Science, 2020, Georgia Tech

 An increasing prevalence of data-irregularity is being seen in applications today, particularly in machine learning, graph analytics, high-performance computing and cybersecurity. Faced with fundamental technology… (more)

Subjects/Keywords: Computer architecture; Sparse; Near data processing; Post-Moore computing; Cache; Memory

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APA (6th Edition):

Srikanth, S. (2020). Energy efficient architectures for irregular data streams. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62757

Chicago Manual of Style (16th Edition):

Srikanth, Sriseshan. “Energy efficient architectures for irregular data streams.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/62757.

MLA Handbook (7th Edition):

Srikanth, Sriseshan. “Energy efficient architectures for irregular data streams.” 2020. Web. 13 Apr 2021.

Vancouver:

Srikanth S. Energy efficient architectures for irregular data streams. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/62757.

Council of Science Editors:

Srikanth S. Energy efficient architectures for irregular data streams. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/62757


Georgia Tech

12. Park, Sunjae Young. Bridging the gap for hardware transactional memory.

Degree: PhD, Computer Science, 2018, Georgia Tech

 Transactional memory (TM) is a promising new tool for shared memory application development. Unlike mutual exclusion locks, TM allows atomic sections to execute concurrently, optimistically… (more)

Subjects/Keywords: Transactional memory; Multithread; Multicore

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APA (6th Edition):

Park, S. Y. (2018). Bridging the gap for hardware transactional memory. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62218

Chicago Manual of Style (16th Edition):

Park, Sunjae Young. “Bridging the gap for hardware transactional memory.” 2018. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/62218.

MLA Handbook (7th Edition):

Park, Sunjae Young. “Bridging the gap for hardware transactional memory.” 2018. Web. 13 Apr 2021.

Vancouver:

Park SY. Bridging the gap for hardware transactional memory. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/62218.

Council of Science Editors:

Park SY. Bridging the gap for hardware transactional memory. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/62218


Georgia Tech

13. Amaravati, Anvesha. Energy-efficient circuits and system architectures to enable intelligence at the edge of the cloud.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 Internet of Things (IoT) devices are collecting a large amount of data for video processing, monitoring health, etc. Transmitting the data from the sensor to… (more)

Subjects/Keywords: Compressive sensing; Reinforcement learning

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APA (6th Edition):

Amaravati, A. (2018). Energy-efficient circuits and system architectures to enable intelligence at the edge of the cloud. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62240

Chicago Manual of Style (16th Edition):

Amaravati, Anvesha. “Energy-efficient circuits and system architectures to enable intelligence at the edge of the cloud.” 2018. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/62240.

MLA Handbook (7th Edition):

Amaravati, Anvesha. “Energy-efficient circuits and system architectures to enable intelligence at the edge of the cloud.” 2018. Web. 13 Apr 2021.

Vancouver:

Amaravati A. Energy-efficient circuits and system architectures to enable intelligence at the edge of the cloud. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/62240.

Council of Science Editors:

Amaravati A. Energy-efficient circuits and system architectures to enable intelligence at the edge of the cloud. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/62240


Georgia Tech

14. Long, Yun. Energy efficient processing in memory architecture for deep learning computing acceleration.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 The major objective of this research is to make the processing-in-memory (PIM) based deep learning accelerator more practical and more computing efficient. This research particularly… (more)

Subjects/Keywords: Processing-in-memory; Deep learning; Resistive ram; Ferroelectric FET; Machine learning computing acceleration

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APA (6th Edition):

Long, Y. (2019). Energy efficient processing in memory architecture for deep learning computing acceleration. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62311

Chicago Manual of Style (16th Edition):

Long, Yun. “Energy efficient processing in memory architecture for deep learning computing acceleration.” 2019. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/62311.

MLA Handbook (7th Edition):

Long, Yun. “Energy efficient processing in memory architecture for deep learning computing acceleration.” 2019. Web. 13 Apr 2021.

Vancouver:

Long Y. Energy efficient processing in memory architecture for deep learning computing acceleration. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/62311.

Council of Science Editors:

Long Y. Energy efficient processing in memory architecture for deep learning computing acceleration. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62311


Georgia Tech

15. Sehatbakhsh, Nader. Leveraging side-channel signals for security and trust.

Degree: PhD, Computer Science, 2020, Georgia Tech

 This decade has already seen a significant surge in the number of cyber attacks. With the exponential growth of computers in numbers, due to the… (more)

Subjects/Keywords: Security; Computer architecture; Side-channels; Embedded systems; IoT; CPS

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APA (6th Edition):

Sehatbakhsh, N. (2020). Leveraging side-channel signals for security and trust. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/63575

Chicago Manual of Style (16th Edition):

Sehatbakhsh, Nader. “Leveraging side-channel signals for security and trust.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/63575.

MLA Handbook (7th Edition):

Sehatbakhsh, Nader. “Leveraging side-channel signals for security and trust.” 2020. Web. 13 Apr 2021.

Vancouver:

Sehatbakhsh N. Leveraging side-channel signals for security and trust. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/63575.

Council of Science Editors:

Sehatbakhsh N. Leveraging side-channel signals for security and trust. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/63575


Georgia Tech

16. Ravichandran, Kaushik. Programming frameworks for performance driven speculative parallelization.

Degree: PhD, Computer Science, 2014, Georgia Tech

 Effectively utilizing available parallelism is becoming harder and harder as systems evolve to many-core processors with many tens of cores per chip. Automatically extracting parallelism… (more)

Subjects/Keywords: Speculation; Transactional memory

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APA (6th Edition):

Ravichandran, K. (2014). Programming frameworks for performance driven speculative parallelization. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52985

Chicago Manual of Style (16th Edition):

Ravichandran, Kaushik. “Programming frameworks for performance driven speculative parallelization.” 2014. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/52985.

MLA Handbook (7th Edition):

Ravichandran, Kaushik. “Programming frameworks for performance driven speculative parallelization.” 2014. Web. 13 Apr 2021.

Vancouver:

Ravichandran K. Programming frameworks for performance driven speculative parallelization. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/52985.

Council of Science Editors:

Ravichandran K. Programming frameworks for performance driven speculative parallelization. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/52985


Georgia Tech

17. Yusuf, Lateef. Improving quality of experience for mobile video streaming.

Degree: PhD, Computer Science, 2014, Georgia Tech

 Thanks to their increasing sophistication and popularity, mobile devices, in the form of smartphones and tablets, have become the fastest growing contributors to Internet traffic.… (more)

Subjects/Keywords: Video; HTTP; DASH; Mobile; Smartphones; P2P; Social networks; Opportunistic networks; Adaptive streaming

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APA (6th Edition):

Yusuf, L. (2014). Improving quality of experience for mobile video streaming. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53423

Chicago Manual of Style (16th Edition):

Yusuf, Lateef. “Improving quality of experience for mobile video streaming.” 2014. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/53423.

MLA Handbook (7th Edition):

Yusuf, Lateef. “Improving quality of experience for mobile video streaming.” 2014. Web. 13 Apr 2021.

Vancouver:

Yusuf L. Improving quality of experience for mobile video streaming. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/53423.

Council of Science Editors:

Yusuf L. Improving quality of experience for mobile video streaming. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/53423


Georgia Tech

18. Chae, Kwanyeob. Design methodologies for robust low-power digital systems under static and dynamic variations.

Degree: PhD, Electrical and Computer Engineering, 2013, Georgia Tech

 Variability affects the performance and power of a circuit. Along with static variations, dynamic variations, which occur during chip operation, necessitate a safety margin. The… (more)

Subjects/Keywords: Adaptive circuit; Resilient design; Static variation; Dynamic variation; Error prevention

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APA (6th Edition):

Chae, K. (2013). Design methodologies for robust low-power digital systems under static and dynamic variations. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52174

Chicago Manual of Style (16th Edition):

Chae, Kwanyeob. “Design methodologies for robust low-power digital systems under static and dynamic variations.” 2013. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/52174.

MLA Handbook (7th Edition):

Chae, Kwanyeob. “Design methodologies for robust low-power digital systems under static and dynamic variations.” 2013. Web. 13 Apr 2021.

Vancouver:

Chae K. Design methodologies for robust low-power digital systems under static and dynamic variations. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/52174.

Council of Science Editors:

Chae K. Design methodologies for robust low-power digital systems under static and dynamic variations. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/52174


Georgia Tech

19. Xiao, He. A Multi-physics approach to the co-design of 3D multi-core processors.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The three-dimensional integrated circuit (3D IC) is a promising solution for processors in the post-Moore era. The 3D integration stacks multiple dies vertically in a… (more)

Subjects/Keywords: Performance; Energy efficiency; 3D IC; Multi-core systems; Multi-physics analysis; Microarchitecture co-design

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APA (6th Edition):

Xiao, H. (2018). A Multi-physics approach to the co-design of 3D multi-core processors. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59810

Chicago Manual of Style (16th Edition):

Xiao, He. “A Multi-physics approach to the co-design of 3D multi-core processors.” 2018. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/59810.

MLA Handbook (7th Edition):

Xiao, He. “A Multi-physics approach to the co-design of 3D multi-core processors.” 2018. Web. 13 Apr 2021.

Vancouver:

Xiao H. A Multi-physics approach to the co-design of 3D multi-core processors. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/59810.

Council of Science Editors:

Xiao H. A Multi-physics approach to the co-design of 3D multi-core processors. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59810


Georgia Tech

20. Czechowski, Kenneth. Diagnosing performance bottlenecks in HPC applications.

Degree: PhD, Computational Science and Engineering, 2019, Georgia Tech

 The software performance optimizations process is one of the most challenging aspects of developing highly performant code because underlying performance limitations are hard to diagnose.… (more)

Subjects/Keywords: HPC

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APA (6th Edition):

Czechowski, K. (2019). Diagnosing performance bottlenecks in HPC applications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61261

Chicago Manual of Style (16th Edition):

Czechowski, Kenneth. “Diagnosing performance bottlenecks in HPC applications.” 2019. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/61261.

MLA Handbook (7th Edition):

Czechowski, Kenneth. “Diagnosing performance bottlenecks in HPC applications.” 2019. Web. 13 Apr 2021.

Vancouver:

Czechowski K. Diagnosing performance bottlenecks in HPC applications. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/61261.

Council of Science Editors:

Czechowski K. Diagnosing performance bottlenecks in HPC applications. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/61261


Georgia Tech

21. Liang, Ching-Kai. Model, predict, and mitigate scalability bottlenecks for parallel application on many-core processors.

Degree: PhD, Computer Science, 2018, Georgia Tech

 Ensuring the continuous scaling of parallel applications is challenging on many-core processors, due to the complex relationship of available parallelism in application and the limited… (more)

Subjects/Keywords: Parallel Applications Many-core processor; Performance modeling; Lock contention; Synchronization; Synchronization Accelerator; Application Scaling

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APA (6th Edition):

Liang, C. (2018). Model, predict, and mitigate scalability bottlenecks for parallel application on many-core processors. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61667

Chicago Manual of Style (16th Edition):

Liang, Ching-Kai. “Model, predict, and mitigate scalability bottlenecks for parallel application on many-core processors.” 2018. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/61667.

MLA Handbook (7th Edition):

Liang, Ching-Kai. “Model, predict, and mitigate scalability bottlenecks for parallel application on many-core processors.” 2018. Web. 13 Apr 2021.

Vancouver:

Liang C. Model, predict, and mitigate scalability bottlenecks for parallel application on many-core processors. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/61667.

Council of Science Editors:

Liang C. Model, predict, and mitigate scalability bottlenecks for parallel application on many-core processors. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/61667


Georgia Tech

22. Kersey, Chad Daniel. A multi-paradigm C++-based hardware description language.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 A generative hardware description library for C++, the CHDL Hardware Design Library or CHDL, along with a body of supporting libraries and a description of… (more)

Subjects/Keywords: Hardware description language; HDL; Domain-specific language; High-level synthesis

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APA (6th Edition):

Kersey, C. D. (2019). A multi-paradigm C++-based hardware description language. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62342

Chicago Manual of Style (16th Edition):

Kersey, Chad Daniel. “A multi-paradigm C++-based hardware description language.” 2019. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/62342.

MLA Handbook (7th Edition):

Kersey, Chad Daniel. “A multi-paradigm C++-based hardware description language.” 2019. Web. 13 Apr 2021.

Vancouver:

Kersey CD. A multi-paradigm C++-based hardware description language. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/62342.

Council of Science Editors:

Kersey CD. A multi-paradigm C++-based hardware description language. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62342


Georgia Tech

23. Lee, Sangho. Mitigating the performance impact of memory bloat.

Degree: PhD, Computer Science, 2015, Georgia Tech

 Memory bloat is loosely defined as an excessive memory usage by an application during its execution. Due to the complexity of efficient memory management that… (more)

Subjects/Keywords: Memory bloat; optimization

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APA (6th Edition):

Lee, S. (2015). Mitigating the performance impact of memory bloat. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56174

Chicago Manual of Style (16th Edition):

Lee, Sangho. “Mitigating the performance impact of memory bloat.” 2015. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/56174.

MLA Handbook (7th Edition):

Lee, Sangho. “Mitigating the performance impact of memory bloat.” 2015. Web. 13 Apr 2021.

Vancouver:

Lee S. Mitigating the performance impact of memory bloat. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/56174.

Council of Science Editors:

Lee S. Mitigating the performance impact of memory bloat. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/56174


Georgia Tech

24. Hassan, Syed Minhaj. Exploiting on-chip memory concurrency in 3d manycore architectures.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The objective of this thesis is to optimize the uncore of 3D many-core architectures. More specifically, we note that technology trends point to large increases… (more)

Subjects/Keywords: 3D memory systems; Network-on-chip; 3D system thermal analysis; Memory-level parallelism; DRAM

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APA (6th Edition):

Hassan, S. M. (2016). Exploiting on-chip memory concurrency in 3d manycore architectures. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56251

Chicago Manual of Style (16th Edition):

Hassan, Syed Minhaj. “Exploiting on-chip memory concurrency in 3d manycore architectures.” 2016. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/56251.

MLA Handbook (7th Edition):

Hassan, Syed Minhaj. “Exploiting on-chip memory concurrency in 3d manycore architectures.” 2016. Web. 13 Apr 2021.

Vancouver:

Hassan SM. Exploiting on-chip memory concurrency in 3d manycore architectures. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/56251.

Council of Science Editors:

Hassan SM. Exploiting on-chip memory concurrency in 3d manycore architectures. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56251


Georgia Tech

25. Wang, Jin. Acceleration and optimization of dynamic parallelism for irregular applications on GPUs.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The objective of this thesis is the development, implementation and optimization of a GPU execution model extension that efficiently supports time-varying, nested, fine-grained dynamic parallelism… (more)

Subjects/Keywords: General-purpose GPU; Dynamic parallelism; Irregular applications

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APA (6th Edition):

Wang, J. (2016). Acceleration and optimization of dynamic parallelism for irregular applications on GPUs. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56294

Chicago Manual of Style (16th Edition):

Wang, Jin. “Acceleration and optimization of dynamic parallelism for irregular applications on GPUs.” 2016. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/56294.

MLA Handbook (7th Edition):

Wang, Jin. “Acceleration and optimization of dynamic parallelism for irregular applications on GPUs.” 2016. Web. 13 Apr 2021.

Vancouver:

Wang J. Acceleration and optimization of dynamic parallelism for irregular applications on GPUs. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/56294.

Council of Science Editors:

Wang J. Acceleration and optimization of dynamic parallelism for irregular applications on GPUs. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56294


Georgia Tech

26. Peng, Yarui. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 As one of more-than-Moore technologies, 3D ICs enable next-generation systems with much higher device density without needs for technology scaling. However, designing reliable 3D IC… (more)

Subjects/Keywords: 3D IC; CAD; Methodology; Reliable; Power integrity; Signal integrity

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APA (6th Edition):

Peng, Y. (2016). CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56330

Chicago Manual of Style (16th Edition):

Peng, Yarui. “CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.” 2016. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/56330.

MLA Handbook (7th Edition):

Peng, Yarui. “CAD tools and methodologies for reliable 3D IC design, analysis, and optimization.” 2016. Web. 13 Apr 2021.

Vancouver:

Peng Y. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/56330.

Council of Science Editors:

Peng Y. CAD tools and methodologies for reliable 3D IC design, analysis, and optimization. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56330


Georgia Tech

27. Mahajan, Divya. Balancing generality and specialization for machine learning in the post-ISA era.

Degree: PhD, Computer Science, 2019, Georgia Tech

 A growing number of commercial and enterprise systems are increasingly relying on compute-intensive machine learning algorithms. While the demand for these apaplications is growing, the… (more)

Subjects/Keywords: Computer architecture; Hardware acceleration; Machine learning; Database management system; Full compute stack; Domain specific language; Hardware software abstraction; Template based architecture; Reconfigurable architecture; FPGA; In database analytics; Stochastic gradient descent; Approximate computing; Hardware software co-design; Instruction set architecture

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APA (6th Edition):

Mahajan, D. (2019). Balancing generality and specialization for machine learning in the post-ISA era. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61075

Chicago Manual of Style (16th Edition):

Mahajan, Divya. “Balancing generality and specialization for machine learning in the post-ISA era.” 2019. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/61075.

MLA Handbook (7th Edition):

Mahajan, Divya. “Balancing generality and specialization for machine learning in the post-ISA era.” 2019. Web. 13 Apr 2021.

Vancouver:

Mahajan D. Balancing generality and specialization for machine learning in the post-ISA era. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/61075.

Council of Science Editors:

Mahajan D. Balancing generality and specialization for machine learning in the post-ISA era. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/61075


Georgia Tech

28. Mandal, Ankush. Enabling parallelism and optimizations in data mining algorithms for power-law data.

Degree: PhD, Computer Science, 2020, Georgia Tech

 Today's data mining tasks aim to extract meaningful information from a large amount of data in a reasonable time mainly via means of  – a)… (more)

Subjects/Keywords: Data mining; Performance optimization; Parallel approximate algorithms; Power-law data; Sketches; Word embedding; Multi-core; GPU

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APA (6th Edition):

Mandal, A. (2020). Enabling parallelism and optimizations in data mining algorithms for power-law data. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/63692

Chicago Manual of Style (16th Edition):

Mandal, Ankush. “Enabling parallelism and optimizations in data mining algorithms for power-law data.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/63692.

MLA Handbook (7th Edition):

Mandal, Ankush. “Enabling parallelism and optimizations in data mining algorithms for power-law data.” 2020. Web. 13 Apr 2021.

Vancouver:

Mandal A. Enabling parallelism and optimizations in data mining algorithms for power-law data. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/63692.

Council of Science Editors:

Mandal A. Enabling parallelism and optimizations in data mining algorithms for power-law data. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/63692


Georgia Tech

29. Parasar, Mayank. Subactive techniques for guaranteeing routing and protocol deadlock freedom in interconnection networks.

Degree: PhD, Electrical and Computer Engineering, 2020, Georgia Tech

 Interconnection networks are the communication backbone for any system. They occur at various scales: from on-chip networks between processing cores, to supercomputers between compute nodes,… (more)

Subjects/Keywords: Interconnection network; Routing deadlock; Protocol deadlock; Proactive; Reactive; Subactive; Network on chip; Computer architecture

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APA (6th Edition):

Parasar, M. (2020). Subactive techniques for guaranteeing routing and protocol deadlock freedom in interconnection networks. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/63654

Chicago Manual of Style (16th Edition):

Parasar, Mayank. “Subactive techniques for guaranteeing routing and protocol deadlock freedom in interconnection networks.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/63654.

MLA Handbook (7th Edition):

Parasar, Mayank. “Subactive techniques for guaranteeing routing and protocol deadlock freedom in interconnection networks.” 2020. Web. 13 Apr 2021.

Vancouver:

Parasar M. Subactive techniques for guaranteeing routing and protocol deadlock freedom in interconnection networks. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/63654.

Council of Science Editors:

Parasar M. Subactive techniques for guaranteeing routing and protocol deadlock freedom in interconnection networks. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/63654


Georgia Tech

30. Kwon, Hyouk Jun. Data- and communication-centric approaches to model and design flexible deep neural network accelerators.

Degree: PhD, Computer Science, 2020, Georgia Tech

 Deep neural network (DNN) accelerators, which are specialized hardware for DNN inferences, enabled energy-efficient and low-latency DNN inferences. To maximize the efficiency (energy efficiency, latency,… (more)

Subjects/Keywords: DNN accelerator; DNN dataflow; DNN mapping; Flexible mapping accelerator

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APA (6th Edition):

Kwon, H. J. (2020). Data- and communication-centric approaches to model and design flexible deep neural network accelerators. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/63663

Chicago Manual of Style (16th Edition):

Kwon, Hyouk Jun. “Data- and communication-centric approaches to model and design flexible deep neural network accelerators.” 2020. Doctoral Dissertation, Georgia Tech. Accessed April 13, 2021. http://hdl.handle.net/1853/63663.

MLA Handbook (7th Edition):

Kwon, Hyouk Jun. “Data- and communication-centric approaches to model and design flexible deep neural network accelerators.” 2020. Web. 13 Apr 2021.

Vancouver:

Kwon HJ. Data- and communication-centric approaches to model and design flexible deep neural network accelerators. [Internet] [Doctoral dissertation]. Georgia Tech; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1853/63663.

Council of Science Editors:

Kwon HJ. Data- and communication-centric approaches to model and design flexible deep neural network accelerators. [Doctoral Dissertation]. Georgia Tech; 2020. Available from: http://hdl.handle.net/1853/63663

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