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You searched for +publisher:"Georgia Tech" +contributor:("Keezer, David"). Showing records 1 – 30 of 36 total matches.

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Georgia Tech

1. Natu, Nitish Umesh. Design and prototyping of temperature resilient clock distribution networks.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 Clock Distribution Networks play a vital role in performance and reliability of a system. However, temperature gradients observed in 3D ICs hamper the functionality of… (more)

Subjects/Keywords: 3D IC; Through silicon via; Clock distribution network (CDN); Skew; Propagation delay; Adaptive voltage; Controllable delay; FPGA; Test vehicle; ASIC buffer design; Three-dimensional integrated circuits; Integrated circuits

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APA (6th Edition):

Natu, N. U. (2014). Design and prototyping of temperature resilient clock distribution networks. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51812

Chicago Manual of Style (16th Edition):

Natu, Nitish Umesh. “Design and prototyping of temperature resilient clock distribution networks.” 2014. Masters Thesis, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/51812.

MLA Handbook (7th Edition):

Natu, Nitish Umesh. “Design and prototyping of temperature resilient clock distribution networks.” 2014. Web. 20 Mar 2019.

Vancouver:

Natu NU. Design and prototyping of temperature resilient clock distribution networks. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/51812.

Council of Science Editors:

Natu NU. Design and prototyping of temperature resilient clock distribution networks. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51812


Georgia Tech

2. Mutnuri, Keertana. Channel adaptive process resilient ultra low-power transmitter design with simulated-annealing based self-discovery.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 Modern day wireless communication systems are constantly facing increasing bandwidth demands due to a growing consumer base. To cope up with it, they are required… (more)

Subjects/Keywords: Ofdm; Papr; Companding; Simulated-annealing; Power-amplifier

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APA (6th Edition):

Mutnuri, K. (2014). Channel adaptive process resilient ultra low-power transmitter design with simulated-annealing based self-discovery. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53402

Chicago Manual of Style (16th Edition):

Mutnuri, Keertana. “Channel adaptive process resilient ultra low-power transmitter design with simulated-annealing based self-discovery.” 2014. Masters Thesis, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/53402.

MLA Handbook (7th Edition):

Mutnuri, Keertana. “Channel adaptive process resilient ultra low-power transmitter design with simulated-annealing based self-discovery.” 2014. Web. 20 Mar 2019.

Vancouver:

Mutnuri K. Channel adaptive process resilient ultra low-power transmitter design with simulated-annealing based self-discovery. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/53402.

Council of Science Editors:

Mutnuri K. Channel adaptive process resilient ultra low-power transmitter design with simulated-annealing based self-discovery. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/53402


Georgia Tech

3. Gassel, Kyle Andrew. Analog public PUF for hardware security.

Degree: MS, Electrical and Computer Engineering, 2018, Georgia Tech

In this thesis I improve a current analog PUF design, primarily in uniqueness and reliability, and further analyze it to show fitness for use as a PPUF. Advisors/Committee Members: Chatterjee, Abhijit (advisor), Milor, Linda S (committee member), Keezer, David C (committee member).

Subjects/Keywords: PUF; PPUF; Cryptography; Security

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APA (6th Edition):

Gassel, K. A. (2018). Analog public PUF for hardware security. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59961

Chicago Manual of Style (16th Edition):

Gassel, Kyle Andrew. “Analog public PUF for hardware security.” 2018. Masters Thesis, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/59961.

MLA Handbook (7th Edition):

Gassel, Kyle Andrew. “Analog public PUF for hardware security.” 2018. Web. 20 Mar 2019.

Vancouver:

Gassel KA. Analog public PUF for hardware security. [Internet] [Masters thesis]. Georgia Tech; 2018. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/59961.

Council of Science Editors:

Gassel KA. Analog public PUF for hardware security. [Masters Thesis]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59961


Georgia Tech

4. Park, Sung Joo. Managing signal, power, and thermal integrity for three-dimensional integrated circuits.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 A full thermal-electrical model of a 3-D system consisting of a PCB, an interposer, TSVs, and stacked dies was built and simulated. From the results… (more)

Subjects/Keywords: 3-D integration; TSV; Electrical-thermal

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APA (6th Edition):

Park, S. J. (2016). Managing signal, power, and thermal integrity for three-dimensional integrated circuits. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58604

Chicago Manual of Style (16th Edition):

Park, Sung Joo. “Managing signal, power, and thermal integrity for three-dimensional integrated circuits.” 2016. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/58604.

MLA Handbook (7th Edition):

Park, Sung Joo. “Managing signal, power, and thermal integrity for three-dimensional integrated circuits.” 2016. Web. 20 Mar 2019.

Vancouver:

Park SJ. Managing signal, power, and thermal integrity for three-dimensional integrated circuits. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/58604.

Council of Science Editors:

Park SJ. Managing signal, power, and thermal integrity for three-dimensional integrated circuits. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/58604


Georgia Tech

5. Zhang, David Chong. Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 A power distribution network (PDN) is designed to provide clean power and facilitate high signal integrity in modern electronic systems. However, the design of a… (more)

Subjects/Keywords: Power delivery network; Power transmission line; Signal integrity; Power integrity; Return path discontinuity

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APA (6th Edition):

Zhang, D. C. (2016). Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56282

Chicago Manual of Style (16th Edition):

Zhang, David Chong. “Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems.” 2016. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/56282.

MLA Handbook (7th Edition):

Zhang, David Chong. “Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems.” 2016. Web. 20 Mar 2019.

Vancouver:

Zhang DC. Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/56282.

Council of Science Editors:

Zhang DC. Design of power delivery networks using power transmission lines for high speed I/O signaling in complex electronic systems. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56282


Georgia Tech

6. Banerjee, Aritra. Design of digitally assisted adaptive analog and RF circuits and systems.

Degree: PhD, Electrical and Computer Engineering, 2013, Georgia Tech

 With more and more integration of analog and RF circuits in scaled CMOS technologies, process variation is playing a critical role which makes it difficult… (more)

Subjects/Keywords: Adaptive analog/RF; Digitally assisted analog; Process variation tolerant; Diagnosis; Performance tuning; Power amplifier; Reliability; Carbon nanotube transistor; Testing

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APA (6th Edition):

Banerjee, A. (2013). Design of digitally assisted adaptive analog and RF circuits and systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52919

Chicago Manual of Style (16th Edition):

Banerjee, Aritra. “Design of digitally assisted adaptive analog and RF circuits and systems.” 2013. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/52919.

MLA Handbook (7th Edition):

Banerjee, Aritra. “Design of digitally assisted adaptive analog and RF circuits and systems.” 2013. Web. 20 Mar 2019.

Vancouver:

Banerjee A. Design of digitally assisted adaptive analog and RF circuits and systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/52919.

Council of Science Editors:

Banerjee A. Design of digitally assisted adaptive analog and RF circuits and systems. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/52919


Georgia Tech

7. Bhatta, Debesh. Algorithms and methodology for incoherent undersampling based acquisition of high speed signal waveforms using low cost test instrumentation.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 The objective of this research is to develop and demonstrate low-complexity, robust, frequency-scalable, wide-band waveform acquisition techniques for testing high speed com- munication systems. High… (more)

Subjects/Keywords: Incoherent undersampling; Low cost testing; Waveform acquisition; High-speed testing

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APA (6th Edition):

Bhatta, D. (2014). Algorithms and methodology for incoherent undersampling based acquisition of high speed signal waveforms using low cost test instrumentation. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54262

Chicago Manual of Style (16th Edition):

Bhatta, Debesh. “Algorithms and methodology for incoherent undersampling based acquisition of high speed signal waveforms using low cost test instrumentation.” 2014. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/54262.

MLA Handbook (7th Edition):

Bhatta, Debesh. “Algorithms and methodology for incoherent undersampling based acquisition of high speed signal waveforms using low cost test instrumentation.” 2014. Web. 20 Mar 2019.

Vancouver:

Bhatta D. Algorithms and methodology for incoherent undersampling based acquisition of high speed signal waveforms using low cost test instrumentation. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/54262.

Council of Science Editors:

Bhatta D. Algorithms and methodology for incoherent undersampling based acquisition of high speed signal waveforms using low cost test instrumentation. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/54262


Georgia Tech

8. Chen, Te-Hui. HIGH-SPEED, LOW COST TEST PLATFORM USING FPGA TECHNOLOGY.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The object of this research is to develop a low-cost, adaptable testing platform for multi-GHz digital applications, with concentration on the test requirement of advanced… (more)

Subjects/Keywords: FPGA; High-speed testing

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APA (6th Edition):

Chen, T. (2016). HIGH-SPEED, LOW COST TEST PLATFORM USING FPGA TECHNOLOGY. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56246

Chicago Manual of Style (16th Edition):

Chen, Te-Hui. “HIGH-SPEED, LOW COST TEST PLATFORM USING FPGA TECHNOLOGY.” 2016. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/56246.

MLA Handbook (7th Edition):

Chen, Te-Hui. “HIGH-SPEED, LOW COST TEST PLATFORM USING FPGA TECHNOLOGY.” 2016. Web. 20 Mar 2019.

Vancouver:

Chen T. HIGH-SPEED, LOW COST TEST PLATFORM USING FPGA TECHNOLOGY. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/56246.

Council of Science Editors:

Chen T. HIGH-SPEED, LOW COST TEST PLATFORM USING FPGA TECHNOLOGY. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56246


Georgia Tech

9. Akbay, Selim Sermet. Constraint-driven RF test stimulus generation and built-in test.

Degree: PhD, Electrical and Computer Engineering, 2009, Georgia Tech

 With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has… (more)

Subjects/Keywords: SVM; MARS; BIST; DfT; BOT; Built-off test; BOST; LNA; Mixer; Transmitter; Receiver; TX; RX; Loopback; Loadboard; Supervised learner; Radio frequency integrated circuits; Testing

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APA (6th Edition):

Akbay, S. S. (2009). Constraint-driven RF test stimulus generation and built-in test. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/33913

Chicago Manual of Style (16th Edition):

Akbay, Selim Sermet. “Constraint-driven RF test stimulus generation and built-in test.” 2009. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/33913.

MLA Handbook (7th Edition):

Akbay, Selim Sermet. “Constraint-driven RF test stimulus generation and built-in test.” 2009. Web. 20 Mar 2019.

Vancouver:

Akbay SS. Constraint-driven RF test stimulus generation and built-in test. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/33913.

Council of Science Editors:

Akbay SS. Constraint-driven RF test stimulus generation and built-in test. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/33913


Georgia Tech

10. Cha, Soonyoung. Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 The objective of this research is to extract NBTI and GOBD model parameters to enable the estimation of the degradation and the remaining life of… (more)

Subjects/Keywords: Design for reliability and yield enhancement; Device-level and system-level reliability modeling

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APA (6th Edition):

Cha, S. (2017). Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59748

Chicago Manual of Style (16th Edition):

Cha, Soonyoung. “Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system.” 2017. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/59748.

MLA Handbook (7th Edition):

Cha, Soonyoung. “Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system.” 2017. Web. 20 Mar 2019.

Vancouver:

Cha S. Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/59748.

Council of Science Editors:

Cha S. Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59748


Georgia Tech

11. Sutton, Akil Khamisi. Hardness assurance testing and radiation hardening by design techniques for silicon-germanium heterojunction bipolar transistors and digital logic circuits.

Degree: PhD, Electrical and Computer Engineering, 2009, Georgia Tech

 Hydrocarbon exploration, global navigation satellite systems, computed tomography, and aircraft avionics are just a few examples of applications that require system operation at an ambient… (more)

Subjects/Keywords: Bit error rate testing; Displacement damage; Heterojunction bipolar transistor; Radiation effects; Radiation hardening by design; Silicon germanium; Single event upset; Ionization; Heterojunctions; Bipolar transistors; Logic circuits; Radiation hardening; Hardness; Germanium compounds; Silicon compounds; Extreme environments

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APA (6th Edition):

Sutton, A. K. (2009). Hardness assurance testing and radiation hardening by design techniques for silicon-germanium heterojunction bipolar transistors and digital logic circuits. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/29778

Chicago Manual of Style (16th Edition):

Sutton, Akil Khamisi. “Hardness assurance testing and radiation hardening by design techniques for silicon-germanium heterojunction bipolar transistors and digital logic circuits.” 2009. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/29778.

MLA Handbook (7th Edition):

Sutton, Akil Khamisi. “Hardness assurance testing and radiation hardening by design techniques for silicon-germanium heterojunction bipolar transistors and digital logic circuits.” 2009. Web. 20 Mar 2019.

Vancouver:

Sutton AK. Hardness assurance testing and radiation hardening by design techniques for silicon-germanium heterojunction bipolar transistors and digital logic circuits. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/29778.

Council of Science Editors:

Sutton AK. Hardness assurance testing and radiation hardening by design techniques for silicon-germanium heterojunction bipolar transistors and digital logic circuits. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/29778

12. Laddha, Vishal. Correlation of PDN impedance with jitter and voltage margin in high speed channels.

Degree: MS, Electrical and Computer Engineering, 2008, Georgia Tech

 Jitter and noise on package and printed circuit board interconnects are limiting factors in the performance of high speed digital channels. The simultaneous switching noise… (more)

Subjects/Keywords: PDN impedance; Jitter; Noise margin; Impedance (Electricity); Genetic algorithms

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APA (6th Edition):

Laddha, V. (2008). Correlation of PDN impedance with jitter and voltage margin in high speed channels. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/26521

Chicago Manual of Style (16th Edition):

Laddha, Vishal. “Correlation of PDN impedance with jitter and voltage margin in high speed channels.” 2008. Masters Thesis, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/26521.

MLA Handbook (7th Edition):

Laddha, Vishal. “Correlation of PDN impedance with jitter and voltage margin in high speed channels.” 2008. Web. 20 Mar 2019.

Vancouver:

Laddha V. Correlation of PDN impedance with jitter and voltage margin in high speed channels. [Internet] [Masters thesis]. Georgia Tech; 2008. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/26521.

Council of Science Editors:

Laddha V. Correlation of PDN impedance with jitter and voltage margin in high speed channels. [Masters Thesis]. Georgia Tech; 2008. Available from: http://hdl.handle.net/1853/26521

13. Moon, Thomas. Testing and characterization of high-speed signals using incoherent undersampling driven signal reconstruction algorithms.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The objective of the proposed research is to develop a framework for the signal reconstruction algorithm with sub-Nyquist sampling rate and the low-cost hardware design… (more)

Subjects/Keywords: High-speed signal characterization; Sub-Nyquist rate reconstruction; Direct subsampling; Low-cost test

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APA (6th Edition):

Moon, T. (2015). Testing and characterization of high-speed signals using incoherent undersampling driven signal reconstruction algorithms. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54326

Chicago Manual of Style (16th Edition):

Moon, Thomas. “Testing and characterization of high-speed signals using incoherent undersampling driven signal reconstruction algorithms.” 2015. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/54326.

MLA Handbook (7th Edition):

Moon, Thomas. “Testing and characterization of high-speed signals using incoherent undersampling driven signal reconstruction algorithms.” 2015. Web. 20 Mar 2019.

Vancouver:

Moon T. Testing and characterization of high-speed signals using incoherent undersampling driven signal reconstruction algorithms. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/54326.

Council of Science Editors:

Moon T. Testing and characterization of high-speed signals using incoherent undersampling driven signal reconstruction algorithms. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/54326

14. Wang, Xian. Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 Low-cost test and tuning methods for difficult-to-measure specifications are presented in this research from the following perspectives: 1)"Safe" test and self-tuning for power converters: To… (more)

Subjects/Keywords: Signature test; RF signal generation; Power converter test; Built-in test; DFT; Alternative testing

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APA (6th Edition):

Wang, X. (2015). Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53521

Chicago Manual of Style (16th Edition):

Wang, Xian. “Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices.” 2015. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/53521.

MLA Handbook (7th Edition):

Wang, Xian. “Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices.” 2015. Web. 20 Mar 2019.

Vancouver:

Wang X. Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/53521.

Council of Science Editors:

Wang X. Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53521

15. Chen, Chang-Chih. System-level modeling and reliability analysis of microprocessor systems.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 Frontend and backend wearout mechanisms are major reliability concerns for modern microprocessors. In this research, a framework which contains modules for negative bias temperature instability… (more)

Subjects/Keywords: Microprocessor; Reliability; Modeling; Negative bias temperature instability; Positive bias temperature instability; Hot carrier injection; Timing analysis; Aging; SRAM; Cache; Gate oxide breakdown; Wearout; Electromigration; Stress-induced voiding; Stress migration; Time-dependent backend dielectric breakdown

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APA (6th Edition):

Chen, C. (2014). System-level modeling and reliability analysis of microprocessor systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53033

Chicago Manual of Style (16th Edition):

Chen, Chang-Chih. “System-level modeling and reliability analysis of microprocessor systems.” 2014. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/53033.

MLA Handbook (7th Edition):

Chen, Chang-Chih. “System-level modeling and reliability analysis of microprocessor systems.” 2014. Web. 20 Mar 2019.

Vancouver:

Chen C. System-level modeling and reliability analysis of microprocessor systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/53033.

Council of Science Editors:

Chen C. System-level modeling and reliability analysis of microprocessor systems. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/53033

16. Tzou, Nicholas. Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 Cost reduction has been and will continue to be a primary driving force in the evolution of hardware design and associated technologies. The objective of… (more)

Subjects/Keywords: Low-cost; Sub-Nyquist; Algorithm; Hardware; Measurement; Multi-rate; Band-interleaved; Undersampling; Jitter; Crosstalk separation; Broadband communication systems Equipment and supplies; Algorithms

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APA (6th Edition):

Tzou, N. (2014). Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51876

Chicago Manual of Style (16th Edition):

Tzou, Nicholas. “Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement.” 2014. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/51876.

MLA Handbook (7th Edition):

Tzou, Nicholas. “Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement.” 2014. Web. 20 Mar 2019.

Vancouver:

Tzou N. Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/51876.

Council of Science Editors:

Tzou N. Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51876

17. Majid, Ashraf Muhammad. Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 Methods for Extending High-Performance Automated Test Equipment (ATE) using Multi-Gigahertz FPGA Technologies Ashraf M. Majid 264 Pages Directed by Dr. David Keezer This thesis presents… (more)

Subjects/Keywords: FPGA based testing; Test enhancement; High-speed digital test; Automated test equipment; Test module; Multi-GHz testing; Field programmable gate arrays; Integrated circuits; Semiconductors

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APA (6th Edition):

Majid, A. M. (2011). Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/39562

Chicago Manual of Style (16th Edition):

Majid, Ashraf Muhammad. “Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies.” 2011. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/39562.

MLA Handbook (7th Edition):

Majid, Ashraf Muhammad. “Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies.” 2011. Web. 20 Mar 2019.

Vancouver:

Majid AM. Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/39562.

Council of Science Editors:

Majid AM. Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/39562

18. Natarajan, Vishwanath. Self-healing RF SoCs: low cost built-in test and control driven simultaneous tuning of multiple performance metrics.

Degree: PhD, Electrical and Computer Engineering, 2010, Georgia Tech

 The advent of deep submicron technology coupled with ever increasing demands from the customer for more functionality on a compact silicon real estate has led… (more)

Subjects/Keywords: Embedded sensors; Low-cost testing; Behavioral modeling; Wireless; OFDM; Calibration; Compensation; Tuning; Self-healing; Production testing; RF testing; Loop-back; Black box modeling; Parameter identification; Process variations; Yield; Receiver; Transmitter; Wireless communication systems; Microelectronics

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APA (6th Edition):

Natarajan, V. (2010). Self-healing RF SoCs: low cost built-in test and control driven simultaneous tuning of multiple performance metrics. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/37165

Chicago Manual of Style (16th Edition):

Natarajan, Vishwanath. “Self-healing RF SoCs: low cost built-in test and control driven simultaneous tuning of multiple performance metrics.” 2010. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/37165.

MLA Handbook (7th Edition):

Natarajan, Vishwanath. “Self-healing RF SoCs: low cost built-in test and control driven simultaneous tuning of multiple performance metrics.” 2010. Web. 20 Mar 2019.

Vancouver:

Natarajan V. Self-healing RF SoCs: low cost built-in test and control driven simultaneous tuning of multiple performance metrics. [Internet] [Doctoral dissertation]. Georgia Tech; 2010. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/37165.

Council of Science Editors:

Natarajan V. Self-healing RF SoCs: low cost built-in test and control driven simultaneous tuning of multiple performance metrics. [Doctoral Dissertation]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/37165

19. Tavassolian, Negar. Dielectric charging in capacitive RF MEMS switches with silicon nitride and silicon dioxide.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 Capacitive radio frequency (RF) micro-electromechanical (MEMS) switches are among the most promising applications in MEMS systems. They have been introduced in the last 15-20 years… (more)

Subjects/Keywords: Dielectric charging; Capacitive MEMS switches; Microelectromechanical systems; Dielectrics

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APA (6th Edition):

Tavassolian, N. (2011). Dielectric charging in capacitive RF MEMS switches with silicon nitride and silicon dioxide. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/39504

Chicago Manual of Style (16th Edition):

Tavassolian, Negar. “Dielectric charging in capacitive RF MEMS switches with silicon nitride and silicon dioxide.” 2011. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/39504.

MLA Handbook (7th Edition):

Tavassolian, Negar. “Dielectric charging in capacitive RF MEMS switches with silicon nitride and silicon dioxide.” 2011. Web. 20 Mar 2019.

Vancouver:

Tavassolian N. Dielectric charging in capacitive RF MEMS switches with silicon nitride and silicon dioxide. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/39504.

Council of Science Editors:

Tavassolian N. Dielectric charging in capacitive RF MEMS switches with silicon nitride and silicon dioxide. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/39504

20. Huh, Suzanne Lynn. Design of power delivery networks for noise suppression and isolation using power transmission lines.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 In conventional design of power delivery networks (PDNs), the PDN impedance is required to be less than the target impedance over the frequency range of… (more)

Subjects/Keywords: Power delivery network; Switching noise; Electromagnetic band gap; Power transmission; Semiconductors; Microelectronics; Mixed signal circuits

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APA (6th Edition):

Huh, S. L. (2011). Design of power delivery networks for noise suppression and isolation using power transmission lines. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/42842

Chicago Manual of Style (16th Edition):

Huh, Suzanne Lynn. “Design of power delivery networks for noise suppression and isolation using power transmission lines.” 2011. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/42842.

MLA Handbook (7th Edition):

Huh, Suzanne Lynn. “Design of power delivery networks for noise suppression and isolation using power transmission lines.” 2011. Web. 20 Mar 2019.

Vancouver:

Huh SL. Design of power delivery networks for noise suppression and isolation using power transmission lines. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/42842.

Council of Science Editors:

Huh SL. Design of power delivery networks for noise suppression and isolation using power transmission lines. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/42842

21. Dutton, Marcus. Flexible architecture methods for graphics processing.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 The FPGA GPU architecture proposed in this thesis was motivated by underserved markets for graphics processing that desire flexibility, long-term device availability, scalability, certifiability, and… (more)

Subjects/Keywords: GPU; FPGA; Graphics processing units; Computer graphics; Field programmable gate arrays; Application-specific integrated circuits; Integrated circuits

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APA (6th Edition):

Dutton, M. (2011). Flexible architecture methods for graphics processing. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/43658

Chicago Manual of Style (16th Edition):

Dutton, Marcus. “Flexible architecture methods for graphics processing.” 2011. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/43658.

MLA Handbook (7th Edition):

Dutton, Marcus. “Flexible architecture methods for graphics processing.” 2011. Web. 20 Mar 2019.

Vancouver:

Dutton M. Flexible architecture methods for graphics processing. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/43658.

Council of Science Editors:

Dutton M. Flexible architecture methods for graphics processing. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/43658

22. Gray, Carl Edward. An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices.

Degree: PhD, Electrical and Computer Engineering, 2012, Georgia Tech

 This thesis presents methods for developing FPGA-based test solutions that solve the challenges of evaluating source-synchronous and protocol-laden systems and devices at multi-gigabit per second… (more)

Subjects/Keywords: Test architecture; Digital systems; High-speed; Field programmable gate arrays; Gigabit communications; Digital communications Testing; Computer networks Testing

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APA (6th Edition):

Gray, C. E. (2012). An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/44858

Chicago Manual of Style (16th Edition):

Gray, Carl Edward. “An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices.” 2012. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/44858.

MLA Handbook (7th Edition):

Gray, Carl Edward. “An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices.” 2012. Web. 20 Mar 2019.

Vancouver:

Gray CE. An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices. [Internet] [Doctoral dissertation]. Georgia Tech; 2012. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/44858.

Council of Science Editors:

Gray CE. An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices. [Doctoral Dissertation]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/44858

23. Ramanathan, Saptharishi. Understanding and development of dielectric passivated high efficiency silicon solar cells using spin-on solutions.

Degree: PhD, Electrical and Computer Engineering, 2012, Georgia Tech

 In this work, spin-on processes were used to improve front- and rear-side technologies of solar cells to increase efficiencies to >20 %. A limited source… (more)

Subjects/Keywords: Dielectric; Spin-on solutions; Passivation; High-efficiency; Solar cells; Silicon solar cells; Dielectrics; Passive components

…system (BOS) costs and the module cost. Prior work at Georgia Tech modeled… 

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APA (6th Edition):

Ramanathan, S. (2012). Understanding and development of dielectric passivated high efficiency silicon solar cells using spin-on solutions. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/44771

Chicago Manual of Style (16th Edition):

Ramanathan, Saptharishi. “Understanding and development of dielectric passivated high efficiency silicon solar cells using spin-on solutions.” 2012. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/44771.

MLA Handbook (7th Edition):

Ramanathan, Saptharishi. “Understanding and development of dielectric passivated high efficiency silicon solar cells using spin-on solutions.” 2012. Web. 20 Mar 2019.

Vancouver:

Ramanathan S. Understanding and development of dielectric passivated high efficiency silicon solar cells using spin-on solutions. [Internet] [Doctoral dissertation]. Georgia Tech; 2012. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/44771.

Council of Science Editors:

Ramanathan S. Understanding and development of dielectric passivated high efficiency silicon solar cells using spin-on solutions. [Doctoral Dissertation]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/44771

24. Devarakond , Shyam Kumar. Signature driven low cost test, diagnosis and tuning of wireless systems.

Degree: PhD, Electrical and Computer Engineering, 2013, Georgia Tech

 With increased and varied performance demands, it is essential that complex multi-standard radio/systems coexist on a same chip. To have cost and performance benefits, these… (more)

Subjects/Keywords: Analog/RF self-tuning; Spice-level diagnosis; Analog/RF test; Wireless communication systems; Radio; Radio frequency; Mixed signal circuits

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APA (6th Edition):

Devarakond , S. K. (2013). Signature driven low cost test, diagnosis and tuning of wireless systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/47594

Chicago Manual of Style (16th Edition):

Devarakond , Shyam Kumar. “Signature driven low cost test, diagnosis and tuning of wireless systems.” 2013. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/47594.

MLA Handbook (7th Edition):

Devarakond , Shyam Kumar. “Signature driven low cost test, diagnosis and tuning of wireless systems.” 2013. Web. 20 Mar 2019.

Vancouver:

Devarakond SK. Signature driven low cost test, diagnosis and tuning of wireless systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/47594.

Council of Science Editors:

Devarakond SK. Signature driven low cost test, diagnosis and tuning of wireless systems. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/47594

25. Kumar, Ajay. A wide dynamic range high-q high-frequency bandpass filter with an automatic quality factor tuning scheme.

Degree: PhD, Electrical and Computer Engineering, 2009, Georgia Tech

 An 80 MHz bandpass filter with a tunable quality factor of 16∼44 using an improved transconductor circuit is presented. A noise optimized biquad structure for… (more)

Subjects/Keywords: Tuning; GM-C; Filter; Analog filter; Continuous time; MLL; QLL; Quality factor; Electric filters, Bandpass; Radio Transmitter-receivers; Wireless communication systems

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APA (6th Edition):

Kumar, A. (2009). A wide dynamic range high-q high-frequency bandpass filter with an automatic quality factor tuning scheme. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/28126

Chicago Manual of Style (16th Edition):

Kumar, Ajay. “A wide dynamic range high-q high-frequency bandpass filter with an automatic quality factor tuning scheme.” 2009. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/28126.

MLA Handbook (7th Edition):

Kumar, Ajay. “A wide dynamic range high-q high-frequency bandpass filter with an automatic quality factor tuning scheme.” 2009. Web. 20 Mar 2019.

Vancouver:

Kumar A. A wide dynamic range high-q high-frequency bandpass filter with an automatic quality factor tuning scheme. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/28126.

Council of Science Editors:

Kumar A. A wide dynamic range high-q high-frequency bandpass filter with an automatic quality factor tuning scheme. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/28126

26. Telikepalli, Satyanarayana. Managing signal and power integrity using power transmission lines and alternative signaling schemes.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 In this dissertation, a new signaling scheme known as Constant Voltage Power Transmission Line (CV-PTL) is presented to supply power to a digital I/O circuit.… (more)

Subjects/Keywords: Signal integrity; Power integrity; Simultaneous switching noise; Switching noise; Power transmission lines; Noise isolation

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APA (6th Edition):

Telikepalli, S. (2015). Managing signal and power integrity using power transmission lines and alternative signaling schemes. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53463

Chicago Manual of Style (16th Edition):

Telikepalli, Satyanarayana. “Managing signal and power integrity using power transmission lines and alternative signaling schemes.” 2015. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/53463.

MLA Handbook (7th Edition):

Telikepalli, Satyanarayana. “Managing signal and power integrity using power transmission lines and alternative signaling schemes.” 2015. Web. 20 Mar 2019.

Vancouver:

Telikepalli S. Managing signal and power integrity using power transmission lines and alternative signaling schemes. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/53463.

Council of Science Editors:

Telikepalli S. Managing signal and power integrity using power transmission lines and alternative signaling schemes. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53463

27. Seth, Sachin. Using complementary silicon-germanium transistors for design of high-performance rf front-ends.

Degree: PhD, Electrical and Computer Engineering, 2012, Georgia Tech

 The objective of the research presented in this dissertation is to explore the achievable dynamic range limits in high-performance RF front-ends designed using SiGe HBTs,… (more)

Subjects/Keywords: Distortion; RF circuit design; SiGe HBT; Transistors; Radio Transmitter-receivers; Radio frequency integrated circuits; Bipolar transistors; Silicon alloys; Germanium

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APA (6th Edition):

Seth, S. (2012). Using complementary silicon-germanium transistors for design of high-performance rf front-ends. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/44721

Chicago Manual of Style (16th Edition):

Seth, Sachin. “Using complementary silicon-germanium transistors for design of high-performance rf front-ends.” 2012. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/44721.

MLA Handbook (7th Edition):

Seth, Sachin. “Using complementary silicon-germanium transistors for design of high-performance rf front-ends.” 2012. Web. 20 Mar 2019.

Vancouver:

Seth S. Using complementary silicon-germanium transistors for design of high-performance rf front-ends. [Internet] [Doctoral dissertation]. Georgia Tech; 2012. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/44721.

Council of Science Editors:

Seth S. Using complementary silicon-germanium transistors for design of high-performance rf front-ends. [Doctoral Dissertation]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/44721

28. Wang, Po-Chun. Fabrication, packaging, and application of micromachined hollow polymer needle arrays.

Degree: PhD, Electrical and Computer Engineering, 2013, Georgia Tech

 Micromachined needles have been shown to successfully transport biological molecules into the body with minimal invasiveness and pain, following the insertion of needles into the… (more)

Subjects/Keywords: Microneedle; Microfabrication; Mechanical characterization; Drug delivery systems; Microlithography; Micromachining

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APA (6th Edition):

Wang, P. (2013). Fabrication, packaging, and application of micromachined hollow polymer needle arrays. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/50283

Chicago Manual of Style (16th Edition):

Wang, Po-Chun. “Fabrication, packaging, and application of micromachined hollow polymer needle arrays.” 2013. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/50283.

MLA Handbook (7th Edition):

Wang, Po-Chun. “Fabrication, packaging, and application of micromachined hollow polymer needle arrays.” 2013. Web. 20 Mar 2019.

Vancouver:

Wang P. Fabrication, packaging, and application of micromachined hollow polymer needle arrays. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/50283.

Council of Science Editors:

Wang P. Fabrication, packaging, and application of micromachined hollow polymer needle arrays. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/50283

29. Choi, Jae Young. Modeling and simulation for signal and power integrity of electronic packages.

Degree: PhD, Electrical and Computer Engineering, 2012, Georgia Tech

 The objective of this dissertation is to develop electrical modeling and co-simulation methodologies for signal and power integrity of package and board applications. The dissertation… (more)

Subjects/Keywords: Power delivery network; Power distribution network; Simultaneous switching noise; Signal integrity; Power integrity; Power ground planes; Microelectronic packaging; Surface mount technology; Electronic packaging; Signal integrity (Electronics); Integrated circuits

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APA (6th Edition):

Choi, J. Y. (2012). Modeling and simulation for signal and power integrity of electronic packages. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/45885

Chicago Manual of Style (16th Edition):

Choi, Jae Young. “Modeling and simulation for signal and power integrity of electronic packages.” 2012. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/45885.

MLA Handbook (7th Edition):

Choi, Jae Young. “Modeling and simulation for signal and power integrity of electronic packages.” 2012. Web. 20 Mar 2019.

Vancouver:

Choi JY. Modeling and simulation for signal and power integrity of electronic packages. [Internet] [Doctoral dissertation]. Georgia Tech; 2012. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/45885.

Council of Science Editors:

Choi JY. Modeling and simulation for signal and power integrity of electronic packages. [Doctoral Dissertation]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/45885

30. Hsin, Shih-Chieh. Design and analysis of key components for manufacturable and low-power CMOS millimeter-wave receiver front end.

Degree: PhD, Electrical and Computer Engineering, 2012, Georgia Tech

 The objective of this dissertation is to develop key components of a CMOS heterodyne millimeter-wave receiver front end. Robust designs are necessary to overcome PVT… (more)

Subjects/Keywords: VCO; LNA; Receiver front end; QVCO; LDO; Metal oxide semiconductors, Complementary; Millimeter wave devices; Millimeter waves; Microwave devices; Microwaves

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APA (6th Edition):

Hsin, S. (2012). Design and analysis of key components for manufacturable and low-power CMOS millimeter-wave receiver front end. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/45877

Chicago Manual of Style (16th Edition):

Hsin, Shih-Chieh. “Design and analysis of key components for manufacturable and low-power CMOS millimeter-wave receiver front end.” 2012. Doctoral Dissertation, Georgia Tech. Accessed March 20, 2019. http://hdl.handle.net/1853/45877.

MLA Handbook (7th Edition):

Hsin, Shih-Chieh. “Design and analysis of key components for manufacturable and low-power CMOS millimeter-wave receiver front end.” 2012. Web. 20 Mar 2019.

Vancouver:

Hsin S. Design and analysis of key components for manufacturable and low-power CMOS millimeter-wave receiver front end. [Internet] [Doctoral dissertation]. Georgia Tech; 2012. [cited 2019 Mar 20]. Available from: http://hdl.handle.net/1853/45877.

Council of Science Editors:

Hsin S. Design and analysis of key components for manufacturable and low-power CMOS millimeter-wave receiver front end. [Doctoral Dissertation]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/45877

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