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You searched for +publisher:"Georgia Tech" +contributor:("Jeffrey A. Davis"). Showing records 1 – 6 of 6 total matches.

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1. Huang, Yong. InAlGaAs/InP light emitting transistors and transistor lasers operating near 1.55 μm.

Degree: PhD, Electrical and Computer Engineering, 2010, Georgia Tech

 Light emitting transistors (LETs) and transistor lasers (TLs) are newly-emerging optoelectronic devices capable of emitting spontaneous or stimulated light while performing transistor actions. This dissertation… (more)

Subjects/Keywords: Doping; MOCVD; Transistor lasers; Light emitting transistors; Device physics; InP/InAlGaAs; Optoelectronic devices; Optoelectronics; Semiconductor doping; Electroluminescence

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APA (6th Edition):

Huang, Y. (2010). InAlGaAs/InP light emitting transistors and transistor lasers operating near 1.55 μm. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/37298

Chicago Manual of Style (16th Edition):

Huang, Yong. “InAlGaAs/InP light emitting transistors and transistor lasers operating near 1.55 μm.” 2010. Doctoral Dissertation, Georgia Tech. Accessed November 15, 2019. http://hdl.handle.net/1853/37298.

MLA Handbook (7th Edition):

Huang, Yong. “InAlGaAs/InP light emitting transistors and transistor lasers operating near 1.55 μm.” 2010. Web. 15 Nov 2019.

Vancouver:

Huang Y. InAlGaAs/InP light emitting transistors and transistor lasers operating near 1.55 μm. [Internet] [Doctoral dissertation]. Georgia Tech; 2010. [cited 2019 Nov 15]. Available from: http://hdl.handle.net/1853/37298.

Council of Science Editors:

Huang Y. InAlGaAs/InP light emitting transistors and transistor lasers operating near 1.55 μm. [Doctoral Dissertation]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/37298

2. Rakheja, Shaloo. Interconnects for post-CMOS devices: physical limits and device and circuit implications.

Degree: PhD, Electrical and Computer Engineering, 2012, Georgia Tech

 The objective of this dissertation is to classify the opportunities, advantages, and limits of novel interconnects for post-CMOS logic that can augment or eventually replace… (more)

Subjects/Keywords: Interconnects; Spintronics; Post-CMOS; Graphene; Spin relaxation; Spin torque; Metal oxide semiconductors, Complementary; Integrated circuits; Semiconductors; Interconnects (Integrated circuit technology); Field-effect transistors; Transistors

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APA (6th Edition):

Rakheja, S. (2012). Interconnects for post-CMOS devices: physical limits and device and circuit implications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/45866

Chicago Manual of Style (16th Edition):

Rakheja, Shaloo. “Interconnects for post-CMOS devices: physical limits and device and circuit implications.” 2012. Doctoral Dissertation, Georgia Tech. Accessed November 15, 2019. http://hdl.handle.net/1853/45866.

MLA Handbook (7th Edition):

Rakheja, Shaloo. “Interconnects for post-CMOS devices: physical limits and device and circuit implications.” 2012. Web. 15 Nov 2019.

Vancouver:

Rakheja S. Interconnects for post-CMOS devices: physical limits and device and circuit implications. [Internet] [Doctoral dissertation]. Georgia Tech; 2012. [cited 2019 Nov 15]. Available from: http://hdl.handle.net/1853/45866.

Council of Science Editors:

Rakheja S. Interconnects for post-CMOS devices: physical limits and device and circuit implications. [Doctoral Dissertation]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/45866

3. Lopez, Gerald Gabriel. The impact of interconnect process variations and size effects for gigascale integration.

Degree: PhD, Electrical and Computer Engineering, 2009, Georgia Tech

 The objective of this research is to demonstrate the impact of interconnect process variations, line-edge roughness and size effects on interconnect effective resistivity and ultimately… (more)

Subjects/Keywords: Closed-form model; Process variations; LER; Size effects; Line-edge roughness; Mean free path; Resistivity; Copper; Grain boundary; Sidewall scattering; Reflectivity; Specularity; Model; Interconnect; Copper; Reflectance; Interconnects (Integrated circuit technology)

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APA (6th Edition):

Lopez, G. G. (2009). The impact of interconnect process variations and size effects for gigascale integration. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/31781

Chicago Manual of Style (16th Edition):

Lopez, Gerald Gabriel. “The impact of interconnect process variations and size effects for gigascale integration.” 2009. Doctoral Dissertation, Georgia Tech. Accessed November 15, 2019. http://hdl.handle.net/1853/31781.

MLA Handbook (7th Edition):

Lopez, Gerald Gabriel. “The impact of interconnect process variations and size effects for gigascale integration.” 2009. Web. 15 Nov 2019.

Vancouver:

Lopez GG. The impact of interconnect process variations and size effects for gigascale integration. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2019 Nov 15]. Available from: http://hdl.handle.net/1853/31781.

Council of Science Editors:

Lopez GG. The impact of interconnect process variations and size effects for gigascale integration. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/31781


Georgia Tech

4. Ogunsola, Oluwafemi Olusegun. Prospects for Mirror-Enabled Polymer Pillar I/O Optical Interconnects for Gigascale Integration.

Degree: PhD, Electrical Engineering, 2006, Georgia Tech

 Digital systems have derived performance benefits due to the scaling down of CMOS microprocessor feature sizes towards packing billions of transistors on a chip, or… (more)

Subjects/Keywords: Mirrors; Polymer pillars; Finite-difference time-domain; FDTD; Optical interconnects; Gigascale integration; Silicon; Optical interconnects; Finite differences Data processing; Digital integrated circuits

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APA (6th Edition):

Ogunsola, O. O. (2006). Prospects for Mirror-Enabled Polymer Pillar I/O Optical Interconnects for Gigascale Integration. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/14067

Chicago Manual of Style (16th Edition):

Ogunsola, Oluwafemi Olusegun. “Prospects for Mirror-Enabled Polymer Pillar I/O Optical Interconnects for Gigascale Integration.” 2006. Doctoral Dissertation, Georgia Tech. Accessed November 15, 2019. http://hdl.handle.net/1853/14067.

MLA Handbook (7th Edition):

Ogunsola, Oluwafemi Olusegun. “Prospects for Mirror-Enabled Polymer Pillar I/O Optical Interconnects for Gigascale Integration.” 2006. Web. 15 Nov 2019.

Vancouver:

Ogunsola OO. Prospects for Mirror-Enabled Polymer Pillar I/O Optical Interconnects for Gigascale Integration. [Internet] [Doctoral dissertation]. Georgia Tech; 2006. [cited 2019 Nov 15]. Available from: http://hdl.handle.net/1853/14067.

Council of Science Editors:

Ogunsola OO. Prospects for Mirror-Enabled Polymer Pillar I/O Optical Interconnects for Gigascale Integration. [Doctoral Dissertation]. Georgia Tech; 2006. Available from: http://hdl.handle.net/1853/14067


Georgia Tech

5. Kim, Hongkyu. Architectural enhancements for efficient operand transport in multimedia systems.

Degree: PhD, Electrical and Computer Engineering, 2007, Georgia Tech

 Multimedia applications pose new challenges to computer architecture. Their tremendous communication demands severely burden the interconnect between functional units. This dissertation addresses to efficiently transport… (more)

Subjects/Keywords: Operand; Transport; Multimedia; Architecture

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APA (6th Edition):

Kim, H. (2007). Architectural enhancements for efficient operand transport in multimedia systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/14595

Chicago Manual of Style (16th Edition):

Kim, Hongkyu. “Architectural enhancements for efficient operand transport in multimedia systems.” 2007. Doctoral Dissertation, Georgia Tech. Accessed November 15, 2019. http://hdl.handle.net/1853/14595.

MLA Handbook (7th Edition):

Kim, Hongkyu. “Architectural enhancements for efficient operand transport in multimedia systems.” 2007. Web. 15 Nov 2019.

Vancouver:

Kim H. Architectural enhancements for efficient operand transport in multimedia systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2007. [cited 2019 Nov 15]. Available from: http://hdl.handle.net/1853/14595.

Council of Science Editors:

Kim H. Architectural enhancements for efficient operand transport in multimedia systems. [Doctoral Dissertation]. Georgia Tech; 2007. Available from: http://hdl.handle.net/1853/14595


Georgia Tech

6. Nugent, Steven Paul. A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC).

Degree: PhD, Electrical and Computer Engineering, 2005, Georgia Tech

 Future opportunities for gigascale integration will be governed by a hierarchy of theoretical and practical limits that can be codified as follows: fundamental, material, device,… (more)

Subjects/Keywords: Chip modeling; Performance modeling; Simulator; Gigascale; Chip modeling; GENESYS; Integrated circuits Very large scale integration Design and construction Computer simulation; System design Computer simulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nugent, S. P. (2005). A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC). (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/6885

Chicago Manual of Style (16th Edition):

Nugent, Steven Paul. “A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC).” 2005. Doctoral Dissertation, Georgia Tech. Accessed November 15, 2019. http://hdl.handle.net/1853/6885.

MLA Handbook (7th Edition):

Nugent, Steven Paul. “A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC).” 2005. Web. 15 Nov 2019.

Vancouver:

Nugent SP. A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC). [Internet] [Doctoral dissertation]. Georgia Tech; 2005. [cited 2019 Nov 15]. Available from: http://hdl.handle.net/1853/6885.

Council of Science Editors:

Nugent SP. A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC). [Doctoral Dissertation]. Georgia Tech; 2005. Available from: http://hdl.handle.net/1853/6885

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