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You searched for +publisher:"Georgia Tech" +contributor:("Daniel F. Baldwin"). Showing records 1 – 2 of 2 total matches.

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Georgia Tech

1. Zhang, Jian. In-process stress analysis of flip chip assembly and reliability assessment during environmental and power cycling tests.

Degree: PhD, Mechanical Engineering, 2003, Georgia Tech

Subjects/Keywords: Flip chip technology Testing; Microelectronic packaging Materials Testing; Microelectronic packaging Materials Testing; Flip chip technology Testing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhang, J. (2003). In-process stress analysis of flip chip assembly and reliability assessment during environmental and power cycling tests. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/5442

Chicago Manual of Style (16th Edition):

Zhang, Jian. “In-process stress analysis of flip chip assembly and reliability assessment during environmental and power cycling tests.” 2003. Doctoral Dissertation, Georgia Tech. Accessed April 20, 2021. http://hdl.handle.net/1853/5442.

MLA Handbook (7th Edition):

Zhang, Jian. “In-process stress analysis of flip chip assembly and reliability assessment during environmental and power cycling tests.” 2003. Web. 20 Apr 2021.

Vancouver:

Zhang J. In-process stress analysis of flip chip assembly and reliability assessment during environmental and power cycling tests. [Internet] [Doctoral dissertation]. Georgia Tech; 2003. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1853/5442.

Council of Science Editors:

Zhang J. In-process stress analysis of flip chip assembly and reliability assessment during environmental and power cycling tests. [Doctoral Dissertation]. Georgia Tech; 2003. Available from: http://hdl.handle.net/1853/5442


Georgia Tech

2. Muncy, Jennifer V. Predictive Failure Model for Flip Chip on Board Component Level Assemblies.

Degree: PhD, Mechanical Engineering, 2004, Georgia Tech

Environmental stress tests, or accelerated life tests, apply stresses to electronic packages that exceed the stress levels experienced in the field. In theory, these elevated stress levels are used to generate the same failure mechanisms that are seen in the field, only at an accelerated rate. The methods of assessing reliability of electronic packages can be classified into two categories: a statistical failure based approach and a physics of failure based approach. This research uses a statistical based methodology to identify the critical factors in reliability performance of a flip chip on board component level assembly and a physics of failure based approach to develop a low cycle strain based fatigue equation for flip chip component level assemblies. The critical factors in determining reliability performance were established via experimental investigation and their influence quantified via regression analysis. This methodology differs from other strain based fatigue approaches because it is not an empirical fit to experimental data; it utilizes regression analysis and least squares to obtain correction factors, or correction functions, and constants for a strain based fatigue equation, where the total inelastic strain is determined analytically. The end product is a general flip chip on board equation rather than one that is specific to a certain test vehicle or material set. Advisors/Committee Members: Daniel F. Baldwin (Committee Chair), Anthony Hayter (Committee Member), Jianmin Qu (Committee Member), Laurence J. Jacobs (Committee Member), Suresh K. Sitaraman (Committee Member).

Subjects/Keywords: Electronics; Flip chip; Solder interconnect fatigue; Predictive modeling; Reliability; Solder and soldering Fatigue; Flip chip technology

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Muncy, J. V. (2004). Predictive Failure Model for Flip Chip on Board Component Level Assemblies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/5131

Chicago Manual of Style (16th Edition):

Muncy, Jennifer V. “Predictive Failure Model for Flip Chip on Board Component Level Assemblies.” 2004. Doctoral Dissertation, Georgia Tech. Accessed April 20, 2021. http://hdl.handle.net/1853/5131.

MLA Handbook (7th Edition):

Muncy, Jennifer V. “Predictive Failure Model for Flip Chip on Board Component Level Assemblies.” 2004. Web. 20 Apr 2021.

Vancouver:

Muncy JV. Predictive Failure Model for Flip Chip on Board Component Level Assemblies. [Internet] [Doctoral dissertation]. Georgia Tech; 2004. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1853/5131.

Council of Science Editors:

Muncy JV. Predictive Failure Model for Flip Chip on Board Component Level Assemblies. [Doctoral Dissertation]. Georgia Tech; 2004. Available from: http://hdl.handle.net/1853/5131

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