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You searched for +publisher:"Georgia Tech" +contributor:("Daniel F. Baldwin"). Showing records 1 – 3 of 3 total matches.

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1. Joo, Sung Chul. Adhesion mechanisms of nano-particle silver to electronics packaging materials.

Degree: PhD, Mechanical Engineering, 2009, Georgia Tech

To reduce electronics packaging lead time and potentially to reduce manufacturing cost, an innovative packaging process targeting rapid package prototyping (RPP) has been developed. The developed RPP process, which is based on a data-driven chip-first approach, provides electrical functionality as well as form factors for micro-systems packages. The key component of the RPP process is the nano-particle silver (NPS) interconnect. However, NPS has not yet been adequately proven for use in electronics packaging applications. Moreover, its adhesion to electronics packaging materials such as polyimide, benzocyclobutene (BCB), copper, and aluminum is found to be weak. Thus, improving the adhesion strength of NPS will be a key issue for reliable package prototypes with NPS interconnects. In this research, the adhesion of NPS to substrate materials is found to be attributed to particle adhesion and more specifically, van der Waals forces. An adhesion model based on the van der Waals force is suggested in order to predict NPS adhesion strength to packaging materials. A new adhesion test method that is based on a die shear test and a button shear test is developed to validate the NPS adhesion prediction model. The newly developed adhesion test method is generic in nature and can be extended to other thin films' adhesion tests. The NPS adhesion model provides a general and explicit relation between NPS tensile bond strength and adhesion factors such as substrate hardness, adhesion distance, van der Waals constant, and particle diameter. The NPS adhesion model is verified as a first order adhesion model using experimental data from seventeen packaging materials. Substrate hardness is identified as a primary factor in NPS adhesion. Adhesion distance and van der Waals constant are also significant in organic and inorganic materials. Diffusion or other interfacial reaction between NPS and metal substrates such as copper and silver seems to exist. Finally, guidelines to improve the adhesion strength of NPS are suggested based on the adhesion model and on external adhesion factors such as Silane coupling agents and plasma treatment. Advisors/Committee Members: Daniel F. Baldwin (Committee Chair).

Subjects/Keywords: Adhesion modeling; Adhesion mechanisms; Adhesion; Nano-particle silver; Electronics packaging; Adhesion; Nanoparticles; Silver; Electronic packaging; Rapid prototyping

…Approved by: Dr. Daniel F. Baldwin, Advisor School of Mechanical Engineering Georgia Institute of… …acknowledgements. I wish to thank Dr. Daniel F. Baldwin, my thesis advisor, for his indispensable… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Joo, S. C. (2009). Adhesion mechanisms of nano-particle silver to electronics packaging materials. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/31730

Chicago Manual of Style (16th Edition):

Joo, Sung Chul. “Adhesion mechanisms of nano-particle silver to electronics packaging materials.” 2009. Doctoral Dissertation, Georgia Tech. Accessed February 28, 2021. http://hdl.handle.net/1853/31730.

MLA Handbook (7th Edition):

Joo, Sung Chul. “Adhesion mechanisms of nano-particle silver to electronics packaging materials.” 2009. Web. 28 Feb 2021.

Vancouver:

Joo SC. Adhesion mechanisms of nano-particle silver to electronics packaging materials. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/1853/31730.

Council of Science Editors:

Joo SC. Adhesion mechanisms of nano-particle silver to electronics packaging materials. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/31730


Georgia Tech

2. Zhang, Jian. In-process stress analysis of flip chip assembly and reliability assessment during environmental and power cycling tests.

Degree: PhD, Mechanical Engineering, 2003, Georgia Tech

Subjects/Keywords: Flip chip technology Testing; Microelectronic packaging Materials Testing; Microelectronic packaging Materials Testing; Flip chip technology Testing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhang, J. (2003). In-process stress analysis of flip chip assembly and reliability assessment during environmental and power cycling tests. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/5442

Chicago Manual of Style (16th Edition):

Zhang, Jian. “In-process stress analysis of flip chip assembly and reliability assessment during environmental and power cycling tests.” 2003. Doctoral Dissertation, Georgia Tech. Accessed February 28, 2021. http://hdl.handle.net/1853/5442.

MLA Handbook (7th Edition):

Zhang, Jian. “In-process stress analysis of flip chip assembly and reliability assessment during environmental and power cycling tests.” 2003. Web. 28 Feb 2021.

Vancouver:

Zhang J. In-process stress analysis of flip chip assembly and reliability assessment during environmental and power cycling tests. [Internet] [Doctoral dissertation]. Georgia Tech; 2003. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/1853/5442.

Council of Science Editors:

Zhang J. In-process stress analysis of flip chip assembly and reliability assessment during environmental and power cycling tests. [Doctoral Dissertation]. Georgia Tech; 2003. Available from: http://hdl.handle.net/1853/5442


Georgia Tech

3. Muncy, Jennifer V. Predictive Failure Model for Flip Chip on Board Component Level Assemblies.

Degree: PhD, Mechanical Engineering, 2004, Georgia Tech

Environmental stress tests, or accelerated life tests, apply stresses to electronic packages that exceed the stress levels experienced in the field. In theory, these elevated stress levels are used to generate the same failure mechanisms that are seen in the field, only at an accelerated rate. The methods of assessing reliability of electronic packages can be classified into two categories: a statistical failure based approach and a physics of failure based approach. This research uses a statistical based methodology to identify the critical factors in reliability performance of a flip chip on board component level assembly and a physics of failure based approach to develop a low cycle strain based fatigue equation for flip chip component level assemblies. The critical factors in determining reliability performance were established via experimental investigation and their influence quantified via regression analysis. This methodology differs from other strain based fatigue approaches because it is not an empirical fit to experimental data; it utilizes regression analysis and least squares to obtain correction factors, or correction functions, and constants for a strain based fatigue equation, where the total inelastic strain is determined analytically. The end product is a general flip chip on board equation rather than one that is specific to a certain test vehicle or material set. Advisors/Committee Members: Daniel F. Baldwin (Committee Chair), Anthony Hayter (Committee Member), Jianmin Qu (Committee Member), Laurence J. Jacobs (Committee Member), Suresh K. Sitaraman (Committee Member).

Subjects/Keywords: Electronics; Flip chip; Solder interconnect fatigue; Predictive modeling; Reliability; Solder and soldering Fatigue; Flip chip technology

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Muncy, J. V. (2004). Predictive Failure Model for Flip Chip on Board Component Level Assemblies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/5131

Chicago Manual of Style (16th Edition):

Muncy, Jennifer V. “Predictive Failure Model for Flip Chip on Board Component Level Assemblies.” 2004. Doctoral Dissertation, Georgia Tech. Accessed February 28, 2021. http://hdl.handle.net/1853/5131.

MLA Handbook (7th Edition):

Muncy, Jennifer V. “Predictive Failure Model for Flip Chip on Board Component Level Assemblies.” 2004. Web. 28 Feb 2021.

Vancouver:

Muncy JV. Predictive Failure Model for Flip Chip on Board Component Level Assemblies. [Internet] [Doctoral dissertation]. Georgia Tech; 2004. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/1853/5131.

Council of Science Editors:

Muncy JV. Predictive Failure Model for Flip Chip on Board Component Level Assemblies. [Doctoral Dissertation]. Georgia Tech; 2004. Available from: http://hdl.handle.net/1853/5131

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