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You searched for +publisher:"Georgia Tech" +contributor:("Chatterjee, Abhijit"). Showing records 1 – 30 of 48 total matches.

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Georgia Tech

1. Banerjee, Suvadeep. State-space encoding driven error resilience in control systems and circuits.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The objective of the proposed research is to develop methodologies, support algorithms and software-hardware infrastructure for detection and diagnosis of parametric failures, transient soft errors… (more)

Subjects/Keywords: Cyber-physical systems; Control systems; Error resilience

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APA (6th Edition):

Banerjee, S. (2018). State-space encoding driven error resilience in control systems and circuits. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59838

Chicago Manual of Style (16th Edition):

Banerjee, Suvadeep. “State-space encoding driven error resilience in control systems and circuits.” 2018. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/59838.

MLA Handbook (7th Edition):

Banerjee, Suvadeep. “State-space encoding driven error resilience in control systems and circuits.” 2018. Web. 16 Feb 2019.

Vancouver:

Banerjee S. State-space encoding driven error resilience in control systems and circuits. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/59838.

Council of Science Editors:

Banerjee S. State-space encoding driven error resilience in control systems and circuits. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59838


Georgia Tech

2. Natu, Nitish Umesh. Design and prototyping of temperature resilient clock distribution networks.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 Clock Distribution Networks play a vital role in performance and reliability of a system. However, temperature gradients observed in 3D ICs hamper the functionality of… (more)

Subjects/Keywords: 3D IC; Through silicon via; Clock distribution network (CDN); Skew; Propagation delay; Adaptive voltage; Controllable delay; FPGA; Test vehicle; ASIC buffer design; Three-dimensional integrated circuits; Integrated circuits

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APA (6th Edition):

Natu, N. U. (2014). Design and prototyping of temperature resilient clock distribution networks. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51812

Chicago Manual of Style (16th Edition):

Natu, Nitish Umesh. “Design and prototyping of temperature resilient clock distribution networks.” 2014. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/51812.

MLA Handbook (7th Edition):

Natu, Nitish Umesh. “Design and prototyping of temperature resilient clock distribution networks.” 2014. Web. 16 Feb 2019.

Vancouver:

Natu NU. Design and prototyping of temperature resilient clock distribution networks. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/51812.

Council of Science Editors:

Natu NU. Design and prototyping of temperature resilient clock distribution networks. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51812


Georgia Tech

3. Mutnuri, Keertana. Channel adaptive process resilient ultra low-power transmitter design with simulated-annealing based self-discovery.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 Modern day wireless communication systems are constantly facing increasing bandwidth demands due to a growing consumer base. To cope up with it, they are required… (more)

Subjects/Keywords: Ofdm; Papr; Companding; Simulated-annealing; Power-amplifier

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APA (6th Edition):

Mutnuri, K. (2014). Channel adaptive process resilient ultra low-power transmitter design with simulated-annealing based self-discovery. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53402

Chicago Manual of Style (16th Edition):

Mutnuri, Keertana. “Channel adaptive process resilient ultra low-power transmitter design with simulated-annealing based self-discovery.” 2014. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/53402.

MLA Handbook (7th Edition):

Mutnuri, Keertana. “Channel adaptive process resilient ultra low-power transmitter design with simulated-annealing based self-discovery.” 2014. Web. 16 Feb 2019.

Vancouver:

Mutnuri K. Channel adaptive process resilient ultra low-power transmitter design with simulated-annealing based self-discovery. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/53402.

Council of Science Editors:

Mutnuri K. Channel adaptive process resilient ultra low-power transmitter design with simulated-annealing based self-discovery. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/53402


Georgia Tech

4. Gassel, Kyle Andrew. Analog public PUF for hardware security.

Degree: MS, Electrical and Computer Engineering, 2018, Georgia Tech

In this thesis I improve a current analog PUF design, primarily in uniqueness and reliability, and further analyze it to show fitness for use as a PPUF. Advisors/Committee Members: Chatterjee, Abhijit (advisor), Milor, Linda S (committee member), Keezer, David C (committee member).

Subjects/Keywords: PUF; PPUF; Cryptography; Security

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APA (6th Edition):

Gassel, K. A. (2018). Analog public PUF for hardware security. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59961

Chicago Manual of Style (16th Edition):

Gassel, Kyle Andrew. “Analog public PUF for hardware security.” 2018. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/59961.

MLA Handbook (7th Edition):

Gassel, Kyle Andrew. “Analog public PUF for hardware security.” 2018. Web. 16 Feb 2019.

Vancouver:

Gassel KA. Analog public PUF for hardware security. [Internet] [Masters thesis]. Georgia Tech; 2018. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/59961.

Council of Science Editors:

Gassel KA. Analog public PUF for hardware security. [Masters Thesis]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59961


Georgia Tech

5. Kumar, Tushar. Characterizing and controlling program behavior using execution-time variance.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 Immersive applications, such as computer gaming, computer vision and video codecs, are an important emerging class of applications with QoS requirements that are difficult to… (more)

Subjects/Keywords: Profiling; QoS tuning; Adaptive control; Optimal control; Gain scheduling; LQR; Machine learning; System identification; Parameter estimation; Online training; Multimedia; Video; Gaming; Computer vision; Statistical analysis; Best effort; Probabilistic; Program analysis; Linear fit; Dynamic tuning

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APA (6th Edition):

Kumar, T. (2016). Characterizing and controlling program behavior using execution-time variance. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55000

Chicago Manual of Style (16th Edition):

Kumar, Tushar. “Characterizing and controlling program behavior using execution-time variance.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/55000.

MLA Handbook (7th Edition):

Kumar, Tushar. “Characterizing and controlling program behavior using execution-time variance.” 2016. Web. 16 Feb 2019.

Vancouver:

Kumar T. Characterizing and controlling program behavior using execution-time variance. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/55000.

Council of Science Editors:

Kumar T. Characterizing and controlling program behavior using execution-time variance. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55000


Georgia Tech

6. Banerjee, Aritra. Design of digitally assisted adaptive analog and RF circuits and systems.

Degree: PhD, Electrical and Computer Engineering, 2013, Georgia Tech

 With more and more integration of analog and RF circuits in scaled CMOS technologies, process variation is playing a critical role which makes it difficult… (more)

Subjects/Keywords: Adaptive analog/RF; Digitally assisted analog; Process variation tolerant; Diagnosis; Performance tuning; Power amplifier; Reliability; Carbon nanotube transistor; Testing

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APA (6th Edition):

Banerjee, A. (2013). Design of digitally assisted adaptive analog and RF circuits and systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/52919

Chicago Manual of Style (16th Edition):

Banerjee, Aritra. “Design of digitally assisted adaptive analog and RF circuits and systems.” 2013. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/52919.

MLA Handbook (7th Edition):

Banerjee, Aritra. “Design of digitally assisted adaptive analog and RF circuits and systems.” 2013. Web. 16 Feb 2019.

Vancouver:

Banerjee A. Design of digitally assisted adaptive analog and RF circuits and systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/52919.

Council of Science Editors:

Banerjee A. Design of digitally assisted adaptive analog and RF circuits and systems. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/52919


Georgia Tech

7. Banerjee, Debashis. Intelligent real-time environment and process adaptive radio frequency front-ends for ultra low power applications.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 In the thesis the design of process tolerant, use-aware radio-frequency front-ends were explored. First, the design of fuzzy logic and equation based controllers, which can… (more)

Subjects/Keywords: Radio frequency; Adaptation; Low noise amplifier; LNA; Front-end; Fuzzy logic; Learning; Energy-per-bit; Mixer; Clustering; Process Variation; Channel

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APA (6th Edition):

Banerjee, D. (2015). Intelligent real-time environment and process adaptive radio frequency front-ends for ultra low power applications. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53882

Chicago Manual of Style (16th Edition):

Banerjee, Debashis. “Intelligent real-time environment and process adaptive radio frequency front-ends for ultra low power applications.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/53882.

MLA Handbook (7th Edition):

Banerjee, Debashis. “Intelligent real-time environment and process adaptive radio frequency front-ends for ultra low power applications.” 2015. Web. 16 Feb 2019.

Vancouver:

Banerjee D. Intelligent real-time environment and process adaptive radio frequency front-ends for ultra low power applications. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/53882.

Council of Science Editors:

Banerjee D. Intelligent real-time environment and process adaptive radio frequency front-ends for ultra low power applications. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53882


Georgia Tech

8. Bhatta, Debesh. Algorithms and methodology for incoherent undersampling based acquisition of high speed signal waveforms using low cost test instrumentation.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 The objective of this research is to develop and demonstrate low-complexity, robust, frequency-scalable, wide-band waveform acquisition techniques for testing high speed com- munication systems. High… (more)

Subjects/Keywords: Incoherent undersampling; Low cost testing; Waveform acquisition; High-speed testing

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APA (6th Edition):

Bhatta, D. (2014). Algorithms and methodology for incoherent undersampling based acquisition of high speed signal waveforms using low cost test instrumentation. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54262

Chicago Manual of Style (16th Edition):

Bhatta, Debesh. “Algorithms and methodology for incoherent undersampling based acquisition of high speed signal waveforms using low cost test instrumentation.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/54262.

MLA Handbook (7th Edition):

Bhatta, Debesh. “Algorithms and methodology for incoherent undersampling based acquisition of high speed signal waveforms using low cost test instrumentation.” 2014. Web. 16 Feb 2019.

Vancouver:

Bhatta D. Algorithms and methodology for incoherent undersampling based acquisition of high speed signal waveforms using low cost test instrumentation. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/54262.

Council of Science Editors:

Bhatta D. Algorithms and methodology for incoherent undersampling based acquisition of high speed signal waveforms using low cost test instrumentation. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/54262


Georgia Tech

9. Natarajan, Jayaram. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 One of the challenges faced today in the design of microprocessors is to obtain power, performance scalability and reliability at the same time with technology… (more)

Subjects/Keywords: Microprocessor; Low power; Process variation; Timing variation tolerant; Timing margins; Better than worse-case design; Error resilient pipeline; Reliability

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APA (6th Edition):

Natarajan, J. (2016). Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55577

Chicago Manual of Style (16th Edition):

Natarajan, Jayaram. “Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/55577.

MLA Handbook (7th Edition):

Natarajan, Jayaram. “Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems.” 2016. Web. 16 Feb 2019.

Vancouver:

Natarajan J. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/55577.

Council of Science Editors:

Natarajan J. Self-adjusting pipeline designs and tuning methods for timing variation tolerance in multi-processor systems. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55577


Georgia Tech

10. Chen, Te-Hui. HIGH-SPEED, LOW COST TEST PLATFORM USING FPGA TECHNOLOGY.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The object of this research is to develop a low-cost, adaptable testing platform for multi-GHz digital applications, with concentration on the test requirement of advanced… (more)

Subjects/Keywords: FPGA; High-speed testing

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APA (6th Edition):

Chen, T. (2016). HIGH-SPEED, LOW COST TEST PLATFORM USING FPGA TECHNOLOGY. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56246

Chicago Manual of Style (16th Edition):

Chen, Te-Hui. “HIGH-SPEED, LOW COST TEST PLATFORM USING FPGA TECHNOLOGY.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/56246.

MLA Handbook (7th Edition):

Chen, Te-Hui. “HIGH-SPEED, LOW COST TEST PLATFORM USING FPGA TECHNOLOGY.” 2016. Web. 16 Feb 2019.

Vancouver:

Chen T. HIGH-SPEED, LOW COST TEST PLATFORM USING FPGA TECHNOLOGY. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/56246.

Council of Science Editors:

Chen T. HIGH-SPEED, LOW COST TEST PLATFORM USING FPGA TECHNOLOGY. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56246


Georgia Tech

11. Akbay, Selim Sermet. Constraint-driven RF test stimulus generation and built-in test.

Degree: PhD, Electrical and Computer Engineering, 2009, Georgia Tech

 With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has… (more)

Subjects/Keywords: SVM; MARS; BIST; DfT; BOT; Built-off test; BOST; LNA; Mixer; Transmitter; Receiver; TX; RX; Loopback; Loadboard; Supervised learner; Radio frequency integrated circuits; Testing

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APA (6th Edition):

Akbay, S. S. (2009). Constraint-driven RF test stimulus generation and built-in test. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/33913

Chicago Manual of Style (16th Edition):

Akbay, Selim Sermet. “Constraint-driven RF test stimulus generation and built-in test.” 2009. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/33913.

MLA Handbook (7th Edition):

Akbay, Selim Sermet. “Constraint-driven RF test stimulus generation and built-in test.” 2009. Web. 16 Feb 2019.

Vancouver:

Akbay SS. Constraint-driven RF test stimulus generation and built-in test. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/33913.

Council of Science Editors:

Akbay SS. Constraint-driven RF test stimulus generation and built-in test. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/33913


Georgia Tech

12. Kim, Woongrae. Design and test methodologies with statistical analysis for reliable memory and processor implementations.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The object of the proposed research is to develop comprehensive methodologies, including circuit design, new test methodologies, and statistical failure analysis, to implement reliable microprocessor… (more)

Subjects/Keywords: Reliability; SRAM; DRAM; Processor

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APA (6th Edition):

Kim, W. (2016). Design and test methodologies with statistical analysis for reliable memory and processor implementations. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59737

Chicago Manual of Style (16th Edition):

Kim, Woongrae. “Design and test methodologies with statistical analysis for reliable memory and processor implementations.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/59737.

MLA Handbook (7th Edition):

Kim, Woongrae. “Design and test methodologies with statistical analysis for reliable memory and processor implementations.” 2016. Web. 16 Feb 2019.

Vancouver:

Kim W. Design and test methodologies with statistical analysis for reliable memory and processor implementations. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/59737.

Council of Science Editors:

Kim W. Design and test methodologies with statistical analysis for reliable memory and processor implementations. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/59737


Georgia Tech

13. Wells, Joshua W. Content-adaptive cross-layer optimized video processing using real-time feature feedback.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 The objective of this research is to design a low-power video processing system capable of minimizing power consumption through graceful reduction of the quality of… (more)

Subjects/Keywords: Video processing; Video encoding; Object tracking; Low power; Error tolerant; Content adaptive

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APA (6th Edition):

Wells, J. W. (2017). Content-adaptive cross-layer optimized video processing using real-time feature feedback. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59751

Chicago Manual of Style (16th Edition):

Wells, Joshua W. “Content-adaptive cross-layer optimized video processing using real-time feature feedback.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/59751.

MLA Handbook (7th Edition):

Wells, Joshua W. “Content-adaptive cross-layer optimized video processing using real-time feature feedback.” 2017. Web. 16 Feb 2019.

Vancouver:

Wells JW. Content-adaptive cross-layer optimized video processing using real-time feature feedback. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/59751.

Council of Science Editors:

Wells JW. Content-adaptive cross-layer optimized video processing using real-time feature feedback. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59751

14. Somoye, Idris Olansile. GPU accelerated adaptive compressed sensing.

Degree: MS, Electrical and Computer Engineering, 2016, Georgia Tech

 There are presently image sensors based around compressed sensing that apply the fundamental theory to video acquisition; however, these imagers require specialized hardware modules that… (more)

Subjects/Keywords: GPU; Compressed sensing; GPGPU; Predictive video encoding

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APA (6th Edition):

Somoye, I. O. (2016). GPU accelerated adaptive compressed sensing. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56379

Chicago Manual of Style (16th Edition):

Somoye, Idris Olansile. “GPU accelerated adaptive compressed sensing.” 2016. Masters Thesis, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/56379.

MLA Handbook (7th Edition):

Somoye, Idris Olansile. “GPU accelerated adaptive compressed sensing.” 2016. Web. 16 Feb 2019.

Vancouver:

Somoye IO. GPU accelerated adaptive compressed sensing. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/56379.

Council of Science Editors:

Somoye IO. GPU accelerated adaptive compressed sensing. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56379

15. Hsiao, Sen-Wen. Built-in test for performance characterization and calibration of phase-locked loops.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 The objective of this dissertation is to propose circuit architectures and techniques for built-in test and calibration of phase-locked loops. The design of phase-locked loops… (more)

Subjects/Keywords: Phase-locked loop; Built-in test; Built-in self-test; Calibration; Analog sensor; Reference spur; Frequency synthesizers; Telecommunication systems; Phase detectors; Phase-locked loops

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APA (6th Edition):

Hsiao, S. (2014). Built-in test for performance characterization and calibration of phase-locked loops. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51790

Chicago Manual of Style (16th Edition):

Hsiao, Sen-Wen. “Built-in test for performance characterization and calibration of phase-locked loops.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/51790.

MLA Handbook (7th Edition):

Hsiao, Sen-Wen. “Built-in test for performance characterization and calibration of phase-locked loops.” 2014. Web. 16 Feb 2019.

Vancouver:

Hsiao S. Built-in test for performance characterization and calibration of phase-locked loops. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/51790.

Council of Science Editors:

Hsiao S. Built-in test for performance characterization and calibration of phase-locked loops. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51790

16. Kim, Dae Hyun. Design methodologies for scalable and reliable memory systems.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 The objective of this research is to develop design methodologies for scalable and reliable memory systems in the presence of scalability and reliability issues exacerbated… (more)

Subjects/Keywords: Memory; Scaling; Reliability; System; Circuit; Test; Repair; Design; Error-correcting codes

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APA (6th Edition):

Kim, D. H. (2017). Design methodologies for scalable and reliable memory systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58654

Chicago Manual of Style (16th Edition):

Kim, Dae Hyun. “Design methodologies for scalable and reliable memory systems.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/58654.

MLA Handbook (7th Edition):

Kim, Dae Hyun. “Design methodologies for scalable and reliable memory systems.” 2017. Web. 16 Feb 2019.

Vancouver:

Kim DH. Design methodologies for scalable and reliable memory systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/58654.

Council of Science Editors:

Kim DH. Design methodologies for scalable and reliable memory systems. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58654

17. Gupta, Man Prakash. Numerical investigation of carbon nanotube thin-film composites and devices.

Degree: PhD, Mechanical Engineering, 2014, Georgia Tech

 Carbon nanotubes (CNTs) are known for their exceptional electrical, thermal, mechanical, optical, and chemical properties. With the significant progress in recent years on synthesis, purification… (more)

Subjects/Keywords: Carbon nanotube; Transistors; Modeling; Reliability; Heat dissipation

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APA (6th Edition):

Gupta, M. P. (2014). Numerical investigation of carbon nanotube thin-film composites and devices. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54846

Chicago Manual of Style (16th Edition):

Gupta, Man Prakash. “Numerical investigation of carbon nanotube thin-film composites and devices.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/54846.

MLA Handbook (7th Edition):

Gupta, Man Prakash. “Numerical investigation of carbon nanotube thin-film composites and devices.” 2014. Web. 16 Feb 2019.

Vancouver:

Gupta MP. Numerical investigation of carbon nanotube thin-film composites and devices. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/54846.

Council of Science Editors:

Gupta MP. Numerical investigation of carbon nanotube thin-film composites and devices. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/54846

18. Moon, Thomas. Testing and characterization of high-speed signals using incoherent undersampling driven signal reconstruction algorithms.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The objective of the proposed research is to develop a framework for the signal reconstruction algorithm with sub-Nyquist sampling rate and the low-cost hardware design… (more)

Subjects/Keywords: High-speed signal characterization; Sub-Nyquist rate reconstruction; Direct subsampling; Low-cost test

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APA (6th Edition):

Moon, T. (2015). Testing and characterization of high-speed signals using incoherent undersampling driven signal reconstruction algorithms. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54326

Chicago Manual of Style (16th Edition):

Moon, Thomas. “Testing and characterization of high-speed signals using incoherent undersampling driven signal reconstruction algorithms.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/54326.

MLA Handbook (7th Edition):

Moon, Thomas. “Testing and characterization of high-speed signals using incoherent undersampling driven signal reconstruction algorithms.” 2015. Web. 16 Feb 2019.

Vancouver:

Moon T. Testing and characterization of high-speed signals using incoherent undersampling driven signal reconstruction algorithms. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/54326.

Council of Science Editors:

Moon T. Testing and characterization of high-speed signals using incoherent undersampling driven signal reconstruction algorithms. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/54326

19. Wang, Xian. Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 Low-cost test and tuning methods for difficult-to-measure specifications are presented in this research from the following perspectives: 1)"Safe" test and self-tuning for power converters: To… (more)

Subjects/Keywords: Signature test; RF signal generation; Power converter test; Built-in test; DFT; Alternative testing

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APA (6th Edition):

Wang, X. (2015). Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53521

Chicago Manual of Style (16th Edition):

Wang, Xian. “Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/53521.

MLA Handbook (7th Edition):

Wang, Xian. “Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices.” 2015. Web. 16 Feb 2019.

Vancouver:

Wang X. Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/53521.

Council of Science Editors:

Wang X. Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53521

20. Chen, Chang-Chih. System-level modeling and reliability analysis of microprocessor systems.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 Frontend and backend wearout mechanisms are major reliability concerns for modern microprocessors. In this research, a framework which contains modules for negative bias temperature instability… (more)

Subjects/Keywords: Microprocessor; Reliability; Modeling; Negative bias temperature instability; Positive bias temperature instability; Hot carrier injection; Timing analysis; Aging; SRAM; Cache; Gate oxide breakdown; Wearout; Electromigration; Stress-induced voiding; Stress migration; Time-dependent backend dielectric breakdown

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APA (6th Edition):

Chen, C. (2014). System-level modeling and reliability analysis of microprocessor systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53033

Chicago Manual of Style (16th Edition):

Chen, Chang-Chih. “System-level modeling and reliability analysis of microprocessor systems.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/53033.

MLA Handbook (7th Edition):

Chen, Chang-Chih. “System-level modeling and reliability analysis of microprocessor systems.” 2014. Web. 16 Feb 2019.

Vancouver:

Chen C. System-level modeling and reliability analysis of microprocessor systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/53033.

Council of Science Editors:

Chen C. System-level modeling and reliability analysis of microprocessor systems. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/53033

21. Tzou, Nicholas. Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 Cost reduction has been and will continue to be a primary driving force in the evolution of hardware design and associated technologies. The objective of… (more)

Subjects/Keywords: Low-cost; Sub-Nyquist; Algorithm; Hardware; Measurement; Multi-rate; Band-interleaved; Undersampling; Jitter; Crosstalk separation; Broadband communication systems Equipment and supplies; Algorithms

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APA (6th Edition):

Tzou, N. (2014). Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51876

Chicago Manual of Style (16th Edition):

Tzou, Nicholas. “Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/51876.

MLA Handbook (7th Edition):

Tzou, Nicholas. “Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement.” 2014. Web. 16 Feb 2019.

Vancouver:

Tzou N. Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/51876.

Council of Science Editors:

Tzou N. Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51876

22. Deyati, Sabyasachi. Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 With the advent of SOCs and SOPs, more functionalities are integrated into an IC or package. Higher level of integration has made testing, validation of… (more)

Subjects/Keywords: Adaptive testing; Analog/RF testing; Mixed signal validation; Machine learning; Beam forming MIMO systems; Trojan detection; Analog physically unclonable function

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APA (6th Edition):

Deyati, S. (2017). Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58757

Chicago Manual of Style (16th Edition):

Deyati, Sabyasachi. “Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/58757.

MLA Handbook (7th Edition):

Deyati, Sabyasachi. “Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems.” 2017. Web. 16 Feb 2019.

Vancouver:

Deyati S. Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/58757.

Council of Science Editors:

Deyati S. Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58757

23. Majid, Ashraf Muhammad. Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 Methods for Extending High-Performance Automated Test Equipment (ATE) using Multi-Gigahertz FPGA Technologies Ashraf M. Majid 264 Pages Directed by Dr. David Keezer This thesis presents… (more)

Subjects/Keywords: FPGA based testing; Test enhancement; High-speed digital test; Automated test equipment; Test module; Multi-GHz testing; Field programmable gate arrays; Integrated circuits; Semiconductors

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APA (6th Edition):

Majid, A. M. (2011). Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/39562

Chicago Manual of Style (16th Edition):

Majid, Ashraf Muhammad. “Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies.” 2011. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/39562.

MLA Handbook (7th Edition):

Majid, Ashraf Muhammad. “Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies.” 2011. Web. 16 Feb 2019.

Vancouver:

Majid AM. Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/39562.

Council of Science Editors:

Majid AM. Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/39562

24. Terizhandur Varadharajan, Narayanan. Fast methods for full-wave electromagnetic simulations of integrated circuit package modules.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 Fast methods for the electromagnetic simulation of integrated circuit (IC) package modules through model order reduction are demonstrated. The 3D integration of multiple functional IC… (more)

Subjects/Keywords: Electromagnetic simulation; Model order reduction; Microelectronic packaging; Electromagnetic interference; Integrated circuits Computer simulation

Page 1 Page 2 Page 3 Page 4 Page 5

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APA (6th Edition):

Terizhandur Varadharajan, N. (2011). Fast methods for full-wave electromagnetic simulations of integrated circuit package modules. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/41059

Chicago Manual of Style (16th Edition):

Terizhandur Varadharajan, Narayanan. “Fast methods for full-wave electromagnetic simulations of integrated circuit package modules.” 2011. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/41059.

MLA Handbook (7th Edition):

Terizhandur Varadharajan, Narayanan. “Fast methods for full-wave electromagnetic simulations of integrated circuit package modules.” 2011. Web. 16 Feb 2019.

Vancouver:

Terizhandur Varadharajan N. Fast methods for full-wave electromagnetic simulations of integrated circuit package modules. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/41059.

Council of Science Editors:

Terizhandur Varadharajan N. Fast methods for full-wave electromagnetic simulations of integrated circuit package modules. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/41059

25. Natarajan, Vishwanath. Self-healing RF SoCs: low cost built-in test and control driven simultaneous tuning of multiple performance metrics.

Degree: PhD, Electrical and Computer Engineering, 2010, Georgia Tech

 The advent of deep submicron technology coupled with ever increasing demands from the customer for more functionality on a compact silicon real estate has led… (more)

Subjects/Keywords: Embedded sensors; Low-cost testing; Behavioral modeling; Wireless; OFDM; Calibration; Compensation; Tuning; Self-healing; Production testing; RF testing; Loop-back; Black box modeling; Parameter identification; Process variations; Yield; Receiver; Transmitter; Wireless communication systems; Microelectronics

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APA (6th Edition):

Natarajan, V. (2010). Self-healing RF SoCs: low cost built-in test and control driven simultaneous tuning of multiple performance metrics. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/37165

Chicago Manual of Style (16th Edition):

Natarajan, Vishwanath. “Self-healing RF SoCs: low cost built-in test and control driven simultaneous tuning of multiple performance metrics.” 2010. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/37165.

MLA Handbook (7th Edition):

Natarajan, Vishwanath. “Self-healing RF SoCs: low cost built-in test and control driven simultaneous tuning of multiple performance metrics.” 2010. Web. 16 Feb 2019.

Vancouver:

Natarajan V. Self-healing RF SoCs: low cost built-in test and control driven simultaneous tuning of multiple performance metrics. [Internet] [Doctoral dissertation]. Georgia Tech; 2010. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/37165.

Council of Science Editors:

Natarajan V. Self-healing RF SoCs: low cost built-in test and control driven simultaneous tuning of multiple performance metrics. [Doctoral Dissertation]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/37165

26. Kook, Se Hun. Low-cost testing of high-precision analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 The advent of deep submicron technology has resulted in a new generation of highly integrated mixed-signal system-on-chips (SoCs) and system-on-packages (SoPs). As a result, the… (more)

Subjects/Keywords: Sigma Delta ADC; Incremental ADC; High-resolution ADC testing; Analog-to-digital converters; Test; Data converters; Analog-to-digital converters; Testing

…research work and enjoying fun time with me for the duration of my stay at Georgia Tech. Most of… …love and confidence, I would not have been able to achieve my goals while studying at Georgia… …Tech. At last, I would like to give my special thanks to my fiancé, Joung Min Leah Choi, who… 

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APA (6th Edition):

Kook, S. H. (2011). Low-cost testing of high-precision analog-to-digital converters. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/41170

Chicago Manual of Style (16th Edition):

Kook, Se Hun. “Low-cost testing of high-precision analog-to-digital converters.” 2011. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/41170.

MLA Handbook (7th Edition):

Kook, Se Hun. “Low-cost testing of high-precision analog-to-digital converters.” 2011. Web. 16 Feb 2019.

Vancouver:

Kook SH. Low-cost testing of high-precision analog-to-digital converters. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/41170.

Council of Science Editors:

Kook SH. Low-cost testing of high-precision analog-to-digital converters. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/41170

27. Chatterjee, Subho. A design methodology for robust, energy-efficient, application-aware memory systems.

Degree: PhD, Electrical and Computer Engineering, 2012, Georgia Tech

 Memory design is a crucial component of VLSI system design from area, power and performance perspectives. To meet the increasingly challenging system specifications, architecture, circuit… (more)

Subjects/Keywords: Application-aware; SRAM; STTRAM; Integrated circuits Very large scale integration; Memory management (Computer science); Computer storage devices; Random access memory

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APA (6th Edition):

Chatterjee, S. (2012). A design methodology for robust, energy-efficient, application-aware memory systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/50146

Chicago Manual of Style (16th Edition):

Chatterjee, Subho. “A design methodology for robust, energy-efficient, application-aware memory systems.” 2012. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/50146.

MLA Handbook (7th Edition):

Chatterjee, Subho. “A design methodology for robust, energy-efficient, application-aware memory systems.” 2012. Web. 16 Feb 2019.

Vancouver:

Chatterjee S. A design methodology for robust, energy-efficient, application-aware memory systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2012. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/50146.

Council of Science Editors:

Chatterjee S. A design methodology for robust, energy-efficient, application-aware memory systems. [Doctoral Dissertation]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/50146

28. Maikisch, Jonathan Stephen. Compact silicon diffractive sensor: design, fabrication, and functional demonstration.

Degree: PhD, Electrical and Computer Engineering, 2012, Georgia Tech

 The primary objective of the presented research is to develop a class of integrated compact silicon diffractive sensors (CSDS) based on in-plane diffraction gratings. This… (more)

Subjects/Keywords: Integrated diffraction grating; Finite-difference time-domain simulation; Rigorous coupled-wave analysis; Diffraction gratings; Microelectronics; Microtechnology

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APA (6th Edition):

Maikisch, J. S. (2012). Compact silicon diffractive sensor: design, fabrication, and functional demonstration. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/45882

Chicago Manual of Style (16th Edition):

Maikisch, Jonathan Stephen. “Compact silicon diffractive sensor: design, fabrication, and functional demonstration.” 2012. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/45882.

MLA Handbook (7th Edition):

Maikisch, Jonathan Stephen. “Compact silicon diffractive sensor: design, fabrication, and functional demonstration.” 2012. Web. 16 Feb 2019.

Vancouver:

Maikisch JS. Compact silicon diffractive sensor: design, fabrication, and functional demonstration. [Internet] [Doctoral dissertation]. Georgia Tech; 2012. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/45882.

Council of Science Editors:

Maikisch JS. Compact silicon diffractive sensor: design, fabrication, and functional demonstration. [Doctoral Dissertation]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/45882

29. Devarakond , Shyam Kumar. Signature driven low cost test, diagnosis and tuning of wireless systems.

Degree: PhD, Electrical and Computer Engineering, 2013, Georgia Tech

 With increased and varied performance demands, it is essential that complex multi-standard radio/systems coexist on a same chip. To have cost and performance benefits, these… (more)

Subjects/Keywords: Analog/RF self-tuning; Spice-level diagnosis; Analog/RF test; Wireless communication systems; Radio; Radio frequency; Mixed signal circuits

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APA (6th Edition):

Devarakond , S. K. (2013). Signature driven low cost test, diagnosis and tuning of wireless systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/47594

Chicago Manual of Style (16th Edition):

Devarakond , Shyam Kumar. “Signature driven low cost test, diagnosis and tuning of wireless systems.” 2013. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/47594.

MLA Handbook (7th Edition):

Devarakond , Shyam Kumar. “Signature driven low cost test, diagnosis and tuning of wireless systems.” 2013. Web. 16 Feb 2019.

Vancouver:

Devarakond SK. Signature driven low cost test, diagnosis and tuning of wireless systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/47594.

Council of Science Editors:

Devarakond SK. Signature driven low cost test, diagnosis and tuning of wireless systems. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/47594

30. Liu, Taizhi. Comprehensive variation-aware aging simulator for logic timing and SRAM stability.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 This research developed a framework which analyzes circuit-level reliability and evaluates the lifetimes of complex systems like state-of-art microprocessors. The novelty of the proposed work… (more)

Subjects/Keywords: Microelectronics; Statistical timing analysis; SRAM stability; Data cache; Circuit aging; BTI; HCI; GOBD

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APA (6th Edition):

Liu, T. (2017). Comprehensive variation-aware aging simulator for logic timing and SRAM stability. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58287

Chicago Manual of Style (16th Edition):

Liu, Taizhi. “Comprehensive variation-aware aging simulator for logic timing and SRAM stability.” 2017. Doctoral Dissertation, Georgia Tech. Accessed February 16, 2019. http://hdl.handle.net/1853/58287.

MLA Handbook (7th Edition):

Liu, Taizhi. “Comprehensive variation-aware aging simulator for logic timing and SRAM stability.” 2017. Web. 16 Feb 2019.

Vancouver:

Liu T. Comprehensive variation-aware aging simulator for logic timing and SRAM stability. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Feb 16]. Available from: http://hdl.handle.net/1853/58287.

Council of Science Editors:

Liu T. Comprehensive variation-aware aging simulator for logic timing and SRAM stability. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58287

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