Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

You searched for +publisher:"Georgia Tech" +contributor:("Cahtterjee,Abhijit"). One record found.

Search Limiters

Last 2 Years | English Only

No search limiters apply to these results.

▼ Search Limiters


Georgia Tech

1. Ghosh, Mrinmoy. Microarchitectural techniques to reduce energy consumption in the memory hierarchy.

Degree: PhD, Electrical and Computer Engineering, 2009, Georgia Tech

This thesis states that dynamic profiling of the memory reference stream can improve energy and performance in the memory hierarchy. The research presented in this theses provides multiple instances of using lightweight hardware structures to profile the memory reference stream. The objective of this research is to develop microarchitectural techniques to reduce energy consumption at different levels of the memory hierarchy. Several simple and implementable techniques were developed as a part of this research. One of the techniques identifies and eliminates redundant refresh operations in DRAM and reduces DRAM refresh power. Another, reduces leakage energy in L2 and higher level caches for multiprocessor systems. The emphasis of this research has been to develop several techniques of obtaining energy savings in caches using a simple hardware structure called the counting Bloom filter (CBF). CBFs have been used to predict L2 cache misses and obtain energy savings by not accessing the L2 cache on a predicted miss. A simple extension of this technique allows CBFs to do way-estimation of set associative caches to reduce energy in cache lookups. Another technique using CBFs track addresses in a Virtual Cache and reduce false synonym lookups. Finally this thesis presents a technique to reduce dynamic power consumption in level one caches using significance compression. The significant energy and performance improvements demonstrated by the techniques presented in this thesis suggest that this work will be of great value for designing memory hierarchies of future computing platforms. Advisors/Committee Members: Lee, Hsien-Hsin S. (Committee Chair), Cahtterjee,Abhijit (Committee Member), Mukhopadhyay, Saibal (Committee Member), Pande, Santosh (Committee Member), Yalamanchili, Sudhakar (Committee Member).

Subjects/Keywords: Energy; Cache; Dram; Microarchitecture; Memory management (Computer science) Power supply; Computer architecture

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ghosh, M. (2009). Microarchitectural techniques to reduce energy consumption in the memory hierarchy. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/28265

Chicago Manual of Style (16th Edition):

Ghosh, Mrinmoy. “Microarchitectural techniques to reduce energy consumption in the memory hierarchy.” 2009. Doctoral Dissertation, Georgia Tech. Accessed February 20, 2019. http://hdl.handle.net/1853/28265.

MLA Handbook (7th Edition):

Ghosh, Mrinmoy. “Microarchitectural techniques to reduce energy consumption in the memory hierarchy.” 2009. Web. 20 Feb 2019.

Vancouver:

Ghosh M. Microarchitectural techniques to reduce energy consumption in the memory hierarchy. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2019 Feb 20]. Available from: http://hdl.handle.net/1853/28265.

Council of Science Editors:

Ghosh M. Microarchitectural techniques to reduce energy consumption in the memory hierarchy. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/28265

.