Gray, Carl Edward.
An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices.
Degree: PhD, Electrical and Computer Engineering, 2012, Georgia Tech
This thesis presents methods for developing FPGA-based test solutions that solve the challenges of evaluating source-synchronous and protocol-laden systems and devices at multi-gigabit per second signaling rates. These interfaces are becoming more prevalent in emerging designs and are difficult to test using traditional automated test equipment (ATE) and test instrumentation which were designed for testing designs utilizing synchronous and deterministic signaling. The main motivation of this research was to develop solutions that address these challenges. The methods shown in this thesis are used to design a test architecture consisting of custom hardware components, reprogrammable digital logic for hardware integration, and a software interface for external data transport and configuration. The hardware components consist of a multi-GHz field programmable gate array (FPGA) based interface board providing processing, control, and data capabilities to the system and enhanced by one or more application modules which can be tailored for specific test functionality compatible with source-synchronous and protocol interfaces. Software controls from a host computer provide high and low level access to the internal tester data and configuration memory space.
The architecture described in this thesis is demonstrated through a specific test solution for a high-speed optical packet switched network called the Data Vortex. Reprogrammable firmware and software controls allow for a high degree of adaptability and application options. The modularized implementation of the hardware elements introduces additional adaptability and future upgradability, capable of incorporating new materials and design techniques for the test platform and application modules.
Advisors/Committee Members: Keezer, David (Committee Chair), Bergman, Keren (Committee Member), Martin, Kevin (Committee Member), Milor, Linda (Committee Member), Wills, Linda (Committee Member).
Subjects/Keywords: Test architecture; Digital systems; High-speed; Field programmable gate arrays; Gigabit communications; Digital communications Testing; Computer networks Testing
to Zotero / EndNote / Reference
APA (6th Edition):
Gray, C. E. (2012). An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/44858
Chicago Manual of Style (16th Edition):
Gray, Carl Edward. “An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices.” 2012. Doctoral Dissertation, Georgia Tech. Accessed July 17, 2019.
MLA Handbook (7th Edition):
Gray, Carl Edward. “An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices.” 2012. Web. 17 Jul 2019.
Gray CE. An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices. [Internet] [Doctoral dissertation]. Georgia Tech; 2012. [cited 2019 Jul 17].
Available from: http://hdl.handle.net/1853/44858.
Council of Science Editors:
Gray CE. An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices. [Doctoral Dissertation]. Georgia Tech; 2012. Available from: http://hdl.handle.net/1853/44858