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You searched for +publisher:"EPFL" +contributor:("Burg, Andreas Peter"). Showing records 1 – 6 of 6 total matches.

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1. Meinerzhagen, Pascal Andreas. Novel Approaches Toward Area- and Energy-Efficient Embedded Memories.

Degree: 2014, EPFL

Subjects/Keywords: embedded memories; VLSI systems; SoC; ASIC; CMOS; SRAM; eDRAM; standard-cell based memory; dynamic storage cells; voltage scaling; near-threshold operation; sub-threshold operation; ultra-low power; reliability; non-volatile memory; ReRAM; OxRAM; gain-cells; gain-cell based eDRAM (GC-eDRAM); retention time improvement; refresh power reduction; body biasing; replica techniques; technology scaling; multilevel gain-cell

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Meinerzhagen, P. A. (2014). Novel Approaches Toward Area- and Energy-Efficient Embedded Memories. (Thesis). EPFL. Retrieved from http://infoscience.epfl.ch/record/196329

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Meinerzhagen, Pascal Andreas. “Novel Approaches Toward Area- and Energy-Efficient Embedded Memories.” 2014. Thesis, EPFL. Accessed June 15, 2019. http://infoscience.epfl.ch/record/196329.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Meinerzhagen, Pascal Andreas. “Novel Approaches Toward Area- and Energy-Efficient Embedded Memories.” 2014. Web. 15 Jun 2019.

Vancouver:

Meinerzhagen PA. Novel Approaches Toward Area- and Energy-Efficient Embedded Memories. [Internet] [Thesis]. EPFL; 2014. [cited 2019 Jun 15]. Available from: http://infoscience.epfl.ch/record/196329.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Meinerzhagen PA. Novel Approaches Toward Area- and Energy-Efficient Embedded Memories. [Thesis]. EPFL; 2014. Available from: http://infoscience.epfl.ch/record/196329

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


EPFL

2. Senning, Carl Christian Sten Dominic. Energy Efficient VLSI Circuits for MIMO-WLAN.

Degree: 2014, EPFL

 Mobile communication - anytime, anywhere access to data and communication services - has been continuously increasing since the operation of the first wireless communication link… (more)

Subjects/Keywords: MIMO; OFDM; VLSI Systems; ASIC; preprocessing circuits for MIMO detectors; PHY layer; energy efficiency; matrix decompositions; lattice reduction; Seysen's algorithm

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Senning, C. C. S. D. (2014). Energy Efficient VLSI Circuits for MIMO-WLAN. (Thesis). EPFL. Retrieved from http://infoscience.epfl.ch/record/202206

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Senning, Carl Christian Sten Dominic. “Energy Efficient VLSI Circuits for MIMO-WLAN.” 2014. Thesis, EPFL. Accessed June 15, 2019. http://infoscience.epfl.ch/record/202206.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Senning, Carl Christian Sten Dominic. “Energy Efficient VLSI Circuits for MIMO-WLAN.” 2014. Web. 15 Jun 2019.

Vancouver:

Senning CCSD. Energy Efficient VLSI Circuits for MIMO-WLAN. [Internet] [Thesis]. EPFL; 2014. [cited 2019 Jun 15]. Available from: http://infoscience.epfl.ch/record/202206.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Senning CCSD. Energy Efficient VLSI Circuits for MIMO-WLAN. [Thesis]. EPFL; 2014. Available from: http://infoscience.epfl.ch/record/202206

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

3. Preyss, Nicholas Alexander. Modulation, Coding, and Receiver Design for Gigabit mmWave Communication.

Degree: 2016, EPFL

 While wireless communication has become an ubiquitous part of our daily life and the world around us, it has not been able yet to deliver… (more)

Subjects/Keywords: millimeter wave communication; mmWave; digital communication; digital signal processing; baseband algorithms; synchronization; sequence estimation; DDFSE; VLSI systems; sub-sampling; digital modulation; amplitude phase-shift keying modulation; polar codes

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Preyss, N. A. (2016). Modulation, Coding, and Receiver Design for Gigabit mmWave Communication. (Thesis). EPFL. Retrieved from http://infoscience.epfl.ch/record/220240

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Preyss, Nicholas Alexander. “Modulation, Coding, and Receiver Design for Gigabit mmWave Communication.” 2016. Thesis, EPFL. Accessed June 15, 2019. http://infoscience.epfl.ch/record/220240.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Preyss, Nicholas Alexander. “Modulation, Coding, and Receiver Design for Gigabit mmWave Communication.” 2016. Web. 15 Jun 2019.

Vancouver:

Preyss NA. Modulation, Coding, and Receiver Design for Gigabit mmWave Communication. [Internet] [Thesis]. EPFL; 2016. [cited 2019 Jun 15]. Available from: http://infoscience.epfl.ch/record/220240.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Preyss NA. Modulation, Coding, and Receiver Design for Gigabit mmWave Communication. [Thesis]. EPFL; 2016. Available from: http://infoscience.epfl.ch/record/220240

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


EPFL

4. Balatsoukas Stimming, Alexios Konstantinos. Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders.

Degree: 2016, EPFL

 The goal of channel coding is to detect and correct errors that appear during the transmission of information. In the past few decades, channel coding… (more)

Subjects/Keywords: Polar codes; successive cancellation list decoding; hardware implementation; VLSI; approximate computing; faulty decoding; LDPC codes; unrolled decoding

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Balatsoukas Stimming, A. K. (2016). Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders. (Thesis). EPFL. Retrieved from http://infoscience.epfl.ch/record/222437

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Balatsoukas Stimming, Alexios Konstantinos. “Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders.” 2016. Thesis, EPFL. Accessed June 15, 2019. http://infoscience.epfl.ch/record/222437.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Balatsoukas Stimming, Alexios Konstantinos. “Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders.” 2016. Web. 15 Jun 2019.

Vancouver:

Balatsoukas Stimming AK. Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders. [Internet] [Thesis]. EPFL; 2016. [cited 2019 Jun 15]. Available from: http://infoscience.epfl.ch/record/222437.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Balatsoukas Stimming AK. Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders. [Thesis]. EPFL; 2016. Available from: http://infoscience.epfl.ch/record/222437

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


EPFL

5. Amarù, Luca Gaetano. New Data Structures and Algorithms for Logic Synthesis and Verification.

Degree: 2015, EPFL

 The strong interaction between Electronic Design Automation (EDA) tools and Complementary Metal-Oxide Semiconductor (CMOS) technology contributed substantially to the advancement of modern digital electronics. The… (more)

Subjects/Keywords: electronic design automation; new logic primitives; logic synthesis; formal methods

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Amarù, L. G. (2015). New Data Structures and Algorithms for Logic Synthesis and Verification. (Thesis). EPFL. Retrieved from http://infoscience.epfl.ch/record/214607

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Amarù, Luca Gaetano. “New Data Structures and Algorithms for Logic Synthesis and Verification.” 2015. Thesis, EPFL. Accessed June 15, 2019. http://infoscience.epfl.ch/record/214607.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Amarù, Luca Gaetano. “New Data Structures and Algorithms for Logic Synthesis and Verification.” 2015. Web. 15 Jun 2019.

Vancouver:

Amarù LG. New Data Structures and Algorithms for Logic Synthesis and Verification. [Internet] [Thesis]. EPFL; 2015. [cited 2019 Jun 15]. Available from: http://infoscience.epfl.ch/record/214607.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Amarù LG. New Data Structures and Algorithms for Logic Synthesis and Verification. [Thesis]. EPFL; 2015. Available from: http://infoscience.epfl.ch/record/214607

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


EPFL

6. Constantin, Jeremy Hugues-Felix. Microarchitectural Low-Power Design Techniques for Embedded Microprocessors.

Degree: 2016, EPFL

 With the omnipresence of embedded processing in all forms of electronics today, there is a strong trend towards wireless, battery-powered, portable embedded systems which have… (more)

Subjects/Keywords: low-power microarchitectural design; instruction set extensions; ultra-low-power embedded processor; sub-threshold operation; dynamic timing margins; dynamic timing analysis; dynamic clock adjustment; statistical fault injection; cryptographic hash functions; compressed sensing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Constantin, J. H. (2016). Microarchitectural Low-Power Design Techniques for Embedded Microprocessors. (Thesis). EPFL. Retrieved from http://infoscience.epfl.ch/record/222867

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Constantin, Jeremy Hugues-Felix. “Microarchitectural Low-Power Design Techniques for Embedded Microprocessors.” 2016. Thesis, EPFL. Accessed June 15, 2019. http://infoscience.epfl.ch/record/222867.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Constantin, Jeremy Hugues-Felix. “Microarchitectural Low-Power Design Techniques for Embedded Microprocessors.” 2016. Web. 15 Jun 2019.

Vancouver:

Constantin JH. Microarchitectural Low-Power Design Techniques for Embedded Microprocessors. [Internet] [Thesis]. EPFL; 2016. [cited 2019 Jun 15]. Available from: http://infoscience.epfl.ch/record/222867.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Constantin JH. Microarchitectural Low-Power Design Techniques for Embedded Microprocessors. [Thesis]. EPFL; 2016. Available from: http://infoscience.epfl.ch/record/222867

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.