Colorado State University
Parameterized and multi-level tiled loop generation.
Degree: PhD, Computer Science, 2010, Colorado State University
Tiling is a loop transformation that decomposes computations into a set of smaller computation blocks. The transformation has been proven to be useful for many high-level program optimizations, such as data locality optimization and exploiting coarse-grained parallelism, and crucial for architecture with limited resources, such as embedded systems, GPUs, and the Cell architecture. Data locality and parallelism will continue to serve as major vehicles for achieving high performance on modern architecture in multi-core era. In parameterized tiling the size of blocks is not fixed at compile time but remains a symbolic constant so that it can be selected/changed even at runtime. Parameterized tiled loops facilitate iterative and runtime optimizations, such as iterative compilation, auto-tuning and dynamic program adaption. In this dissertation we present a collection of techniques for generating parameterized and multi-level tiled loops from affine control loops and their parallelization. The tiled loop generation problem even for perfectly nested loops has been believed to have an exponential time complexity due to the heavy machinery like Fourier-Motzkin elimination. Disproving this decade-long belief, we provide a simple technique for generating tiled loop nests even from imperfectly nested loops. Our technique for perfectly nested loops consists of only syntactic processing that is applied only once and independently to each loop bound. Our approach to imperfectly nested loops is composed of a direct extension of the tiled code generation technique for perfectly nested loops and three simple optimizations on the resulting parameterized tiled loops. The generation as well as the optimizations are achieved only with purely syntactic processing, hence loop generation time remains negligible. We also present three schemes for multi-level tiling where tiling is applied more than once. All the schemes are scalable with respect to the number of tiling levels and can be combined to achieve better performance. To facilitate parallelization of parameterized tiled loops, we generate outermost tile-loops that are perfectly nested. We also provide a technique for statically restructuring parameterized tiled loops to the wavefront scheduling on shared memory system. Because the formulation of parameterized tiling does not fit into the well established polyhedral framework, such static restructuring has been a great challenge. However, we achieve this limited restructuring through a syntactic processing without any sophisticated machinery.
Advisors/Committee Members: Rajopadhye, Sanjay Vishnu (advisor), Böhm, Anton Pedro Willem, 1948- (committee member), Chong, Edwin Kah Pin (committee member), Strout, Michelle Mills, 1974- (committee member).
Subjects/Keywords: tiling; polyhedral model; parallelization; optimization; compiler; code generation; Loop tiling (Computer science); Compilers (Computer programs); Loops (Group theory); Parallel processing (Electronic computers)
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APA (6th Edition):
Kim, D. (2010). Parameterized and multi-level tiled loop generation. (Doctoral Dissertation). Colorado State University. Retrieved from http://hdl.handle.net/10217/39103
Chicago Manual of Style (16th Edition):
Kim, DaeGon. “Parameterized and multi-level tiled loop generation.” 2010. Doctoral Dissertation, Colorado State University. Accessed May 08, 2021.
MLA Handbook (7th Edition):
Kim, DaeGon. “Parameterized and multi-level tiled loop generation.” 2010. Web. 08 May 2021.
Kim D. Parameterized and multi-level tiled loop generation. [Internet] [Doctoral dissertation]. Colorado State University; 2010. [cited 2021 May 08].
Available from: http://hdl.handle.net/10217/39103.
Council of Science Editors:
Kim D. Parameterized and multi-level tiled loop generation. [Doctoral Dissertation]. Colorado State University; 2010. Available from: http://hdl.handle.net/10217/39103