Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for +publisher:"California State University – Sacramento" +contributor:("Heedley, Perry"). Showing records 1 – 16 of 16 total matches.

Search Limiters

Last 2 Years | English Only

No search limiters apply to these results.

▼ Search Limiters


California State University – Sacramento

1. Silva, William. A tapered CML buffer chain design for a 1 GHz interpolating flash ADC.

Degree: MS, Electrical and Electronic Engineering, 2010, California State University – Sacramento

 Current Mode Logic buffers are based on the MOS differential amplifier circuit. Since CML buffers utilize a differential circuit topology, they are less vulnerable to… (more)

Subjects/Keywords: Current; Mode; Logic

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Silva, W. (2010). A tapered CML buffer chain design for a 1 GHz interpolating flash ADC. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.9/461

Chicago Manual of Style (16th Edition):

Silva, William. “A tapered CML buffer chain design for a 1 GHz interpolating flash ADC.” 2010. Masters Thesis, California State University – Sacramento. Accessed October 14, 2019. http://hdl.handle.net/10211.9/461.

MLA Handbook (7th Edition):

Silva, William. “A tapered CML buffer chain design for a 1 GHz interpolating flash ADC.” 2010. Web. 14 Oct 2019.

Vancouver:

Silva W. A tapered CML buffer chain design for a 1 GHz interpolating flash ADC. [Internet] [Masters thesis]. California State University – Sacramento; 2010. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10211.9/461.

Council of Science Editors:

Silva W. A tapered CML buffer chain design for a 1 GHz interpolating flash ADC. [Masters Thesis]. California State University – Sacramento; 2010. Available from: http://hdl.handle.net/10211.9/461


California State University – Sacramento

2. Dabhi, Chirag V. Design of a charge pump for a phase locked loop FM synthesizer in 0.5??m CMOS.

Degree: MS, Electrical and Electronic Engineering, 2011, California State University – Sacramento

 The aim of this project was to design, simulate and layout a charge pump for a phase locked loop (PLL) FM synthesizer in a 0.5um… (more)

Subjects/Keywords: PLL; Charge pump; Differential amplifier

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dabhi, C. V. (2011). Design of a charge pump for a phase locked loop FM synthesizer in 0.5??m CMOS. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.9/859

Chicago Manual of Style (16th Edition):

Dabhi, Chirag V. “Design of a charge pump for a phase locked loop FM synthesizer in 0.5??m CMOS.” 2011. Masters Thesis, California State University – Sacramento. Accessed October 14, 2019. http://hdl.handle.net/10211.9/859.

MLA Handbook (7th Edition):

Dabhi, Chirag V. “Design of a charge pump for a phase locked loop FM synthesizer in 0.5??m CMOS.” 2011. Web. 14 Oct 2019.

Vancouver:

Dabhi CV. Design of a charge pump for a phase locked loop FM synthesizer in 0.5??m CMOS. [Internet] [Masters thesis]. California State University – Sacramento; 2011. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10211.9/859.

Council of Science Editors:

Dabhi CV. Design of a charge pump for a phase locked loop FM synthesizer in 0.5??m CMOS. [Masters Thesis]. California State University – Sacramento; 2011. Available from: http://hdl.handle.net/10211.9/859


California State University – Sacramento

3. Martin, Nicholas Thomas. Fault diagnosis and comparator redesign for an 8-bit 20ms/s calibrated pipelined analog-to-digital converter in 0.5um CMOS.

Degree: MS, Electrical and Electronic Engineering, 2011, California State University – Sacramento

 This project is a fault diagnosis and redesign effort for an 8-bit 20-MS/s pipelined analog-to-digital converter designed and fabricated in a 0.5??m CMOS process technology.… (more)

Subjects/Keywords: Swing minimizing circuit; Dynamic offset test bench; Preamplifier

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Martin, N. T. (2011). Fault diagnosis and comparator redesign for an 8-bit 20ms/s calibrated pipelined analog-to-digital converter in 0.5um CMOS. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.9/1346

Chicago Manual of Style (16th Edition):

Martin, Nicholas Thomas. “Fault diagnosis and comparator redesign for an 8-bit 20ms/s calibrated pipelined analog-to-digital converter in 0.5um CMOS.” 2011. Masters Thesis, California State University – Sacramento. Accessed October 14, 2019. http://hdl.handle.net/10211.9/1346.

MLA Handbook (7th Edition):

Martin, Nicholas Thomas. “Fault diagnosis and comparator redesign for an 8-bit 20ms/s calibrated pipelined analog-to-digital converter in 0.5um CMOS.” 2011. Web. 14 Oct 2019.

Vancouver:

Martin NT. Fault diagnosis and comparator redesign for an 8-bit 20ms/s calibrated pipelined analog-to-digital converter in 0.5um CMOS. [Internet] [Masters thesis]. California State University – Sacramento; 2011. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10211.9/1346.

Council of Science Editors:

Martin NT. Fault diagnosis and comparator redesign for an 8-bit 20ms/s calibrated pipelined analog-to-digital converter in 0.5um CMOS. [Masters Thesis]. California State University – Sacramento; 2011. Available from: http://hdl.handle.net/10211.9/1346


California State University – Sacramento

4. Beidalah, Sammi. Low jitter ring oscillator using a modified inverter delay cell.

Degree: MS, Electrical and Electronic Engineering, 2014, California State University – Sacramento

 A ring oscillator is a device whose output oscillates between two voltage levels, which is used for timing and sequencing of logic circuitry. The inverters… (more)

Subjects/Keywords: Circuit; Oscillator; Jitter

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Beidalah, S. (2014). Low jitter ring oscillator using a modified inverter delay cell. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/125035

Chicago Manual of Style (16th Edition):

Beidalah, Sammi. “Low jitter ring oscillator using a modified inverter delay cell.” 2014. Masters Thesis, California State University – Sacramento. Accessed October 14, 2019. http://hdl.handle.net/10211.3/125035.

MLA Handbook (7th Edition):

Beidalah, Sammi. “Low jitter ring oscillator using a modified inverter delay cell.” 2014. Web. 14 Oct 2019.

Vancouver:

Beidalah S. Low jitter ring oscillator using a modified inverter delay cell. [Internet] [Masters thesis]. California State University – Sacramento; 2014. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10211.3/125035.

Council of Science Editors:

Beidalah S. Low jitter ring oscillator using a modified inverter delay cell. [Masters Thesis]. California State University – Sacramento; 2014. Available from: http://hdl.handle.net/10211.3/125035


California State University – Sacramento

5. Shanks, Anthony. Biomedical low noise amplifier.

Degree: MS, Electrical and Electronic Engineering, 2015, California State University – Sacramento

 Using electrodes to read electrical signals from the human body and display them on an oscilloscope requires an analog front end to properly capture, amplify,… (more)

Subjects/Keywords: Biomedical AFE; Current Balancing Amplifier; Low noise amplifier; Biomedical front end; Current balancing amplifier

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shanks, A. (2015). Biomedical low noise amplifier. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/143994

Chicago Manual of Style (16th Edition):

Shanks, Anthony. “Biomedical low noise amplifier.” 2015. Masters Thesis, California State University – Sacramento. Accessed October 14, 2019. http://hdl.handle.net/10211.3/143994.

MLA Handbook (7th Edition):

Shanks, Anthony. “Biomedical low noise amplifier.” 2015. Web. 14 Oct 2019.

Vancouver:

Shanks A. Biomedical low noise amplifier. [Internet] [Masters thesis]. California State University – Sacramento; 2015. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10211.3/143994.

Council of Science Editors:

Shanks A. Biomedical low noise amplifier. [Masters Thesis]. California State University – Sacramento; 2015. Available from: http://hdl.handle.net/10211.3/143994


California State University – Sacramento

6. Ahmad, Riaz. Design of a digitally controlled oscillator for an integrated circuit phase-locked loop.

Degree: MS, Electrical and Electronic Engineering, 2017, California State University – Sacramento

 The project focuses on the design and simulation of a digitally-controlled oscillator (DCO) for an all-digital phase-locked loop in a 180nm CMOS process. A ring… (more)

Subjects/Keywords: Oscillator for ADPLL; Differential ring oscillator; Cross-coupled inverters

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ahmad, R. (2017). Design of a digitally controlled oscillator for an integrated circuit phase-locked loop. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/194217

Chicago Manual of Style (16th Edition):

Ahmad, Riaz. “Design of a digitally controlled oscillator for an integrated circuit phase-locked loop.” 2017. Masters Thesis, California State University – Sacramento. Accessed October 14, 2019. http://hdl.handle.net/10211.3/194217.

MLA Handbook (7th Edition):

Ahmad, Riaz. “Design of a digitally controlled oscillator for an integrated circuit phase-locked loop.” 2017. Web. 14 Oct 2019.

Vancouver:

Ahmad R. Design of a digitally controlled oscillator for an integrated circuit phase-locked loop. [Internet] [Masters thesis]. California State University – Sacramento; 2017. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10211.3/194217.

Council of Science Editors:

Ahmad R. Design of a digitally controlled oscillator for an integrated circuit phase-locked loop. [Masters Thesis]. California State University – Sacramento; 2017. Available from: http://hdl.handle.net/10211.3/194217


California State University – Sacramento

7. Morgan, Jeffrey. Design of a phase frequency detector and charge pump for a phase-locked loop in 0.18??m CMOS.

Degree: MS, Electrical and Electronic Engineering, 2017, California State University – Sacramento

 The design and simulation of a phase frequency detector and a charge pump for a low-jitter, high-frequency phase-locked loop in 0.18??m CMOS are explored. The… (more)

Subjects/Keywords: CMOS; Analog/Mixed-signal; Integrated circuit; CML; Current-mode logic; Operational amplifier; Microelectronics

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Morgan, J. (2017). Design of a phase frequency detector and charge pump for a phase-locked loop in 0.18??m CMOS. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/190177

Chicago Manual of Style (16th Edition):

Morgan, Jeffrey. “Design of a phase frequency detector and charge pump for a phase-locked loop in 0.18??m CMOS.” 2017. Masters Thesis, California State University – Sacramento. Accessed October 14, 2019. http://hdl.handle.net/10211.3/190177.

MLA Handbook (7th Edition):

Morgan, Jeffrey. “Design of a phase frequency detector and charge pump for a phase-locked loop in 0.18??m CMOS.” 2017. Web. 14 Oct 2019.

Vancouver:

Morgan J. Design of a phase frequency detector and charge pump for a phase-locked loop in 0.18??m CMOS. [Internet] [Masters thesis]. California State University – Sacramento; 2017. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10211.3/190177.

Council of Science Editors:

Morgan J. Design of a phase frequency detector and charge pump for a phase-locked loop in 0.18??m CMOS. [Masters Thesis]. California State University – Sacramento; 2017. Available from: http://hdl.handle.net/10211.3/190177


California State University – Sacramento

8. Gavankar, Akhil A. A digital loop filter for an all-digital phase-locked loop.

Degree: MS, Electrical and Electronic Engineering, 2017, California State University – Sacramento

 The digital loop filter for an all-digital phase-locked loop was designed to meet a given set of specifications, and the performance of the filter was… (more)

Subjects/Keywords: Loop filter; Digital design; Phase-locked loop

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gavankar, A. A. (2017). A digital loop filter for an all-digital phase-locked loop. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/198839

Chicago Manual of Style (16th Edition):

Gavankar, Akhil A. “A digital loop filter for an all-digital phase-locked loop.” 2017. Masters Thesis, California State University – Sacramento. Accessed October 14, 2019. http://hdl.handle.net/10211.3/198839.

MLA Handbook (7th Edition):

Gavankar, Akhil A. “A digital loop filter for an all-digital phase-locked loop.” 2017. Web. 14 Oct 2019.

Vancouver:

Gavankar AA. A digital loop filter for an all-digital phase-locked loop. [Internet] [Masters thesis]. California State University – Sacramento; 2017. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10211.3/198839.

Council of Science Editors:

Gavankar AA. A digital loop filter for an all-digital phase-locked loop. [Masters Thesis]. California State University – Sacramento; 2017. Available from: http://hdl.handle.net/10211.3/198839


California State University – Sacramento

9. Kantharaj, Ashwin. Verilog-AMS verification methodology of the control bits for mixed-signal transceiver.

Degree: MS, Electrical and Electronic Engineering, 2017, California State University – Sacramento

 Connectivity verification on a complex and large-scale chip can be a daunting and one of the crucial tasks to ensure the silicon to work on… (more)

Subjects/Keywords: Mixed-signal; Verification; Analog assertions

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kantharaj, A. (2017). Verilog-AMS verification methodology of the control bits for mixed-signal transceiver. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/198295

Chicago Manual of Style (16th Edition):

Kantharaj, Ashwin. “Verilog-AMS verification methodology of the control bits for mixed-signal transceiver.” 2017. Masters Thesis, California State University – Sacramento. Accessed October 14, 2019. http://hdl.handle.net/10211.3/198295.

MLA Handbook (7th Edition):

Kantharaj, Ashwin. “Verilog-AMS verification methodology of the control bits for mixed-signal transceiver.” 2017. Web. 14 Oct 2019.

Vancouver:

Kantharaj A. Verilog-AMS verification methodology of the control bits for mixed-signal transceiver. [Internet] [Masters thesis]. California State University – Sacramento; 2017. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10211.3/198295.

Council of Science Editors:

Kantharaj A. Verilog-AMS verification methodology of the control bits for mixed-signal transceiver. [Masters Thesis]. California State University – Sacramento; 2017. Available from: http://hdl.handle.net/10211.3/198295


California State University – Sacramento

10. Khazane, Nitish Kumar. Design of a comparator and an integrator for a dynamic offset testbench in 0.18??m CMOS.

Degree: MS, Electrical and Electronic Engineering, 2019, California State University – Sacramento

 This report describes the operation, design, and simulation of a comparator and an integrator for a Dynamic Offset Test Bench (DOTB) in 0.18??m CMOS. The… (more)

Subjects/Keywords: DOTB; Comparator; Integrator; Input-Referred Offset; Dynamic Offset Testbench; CMOS

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Khazane, N. K. (2019). Design of a comparator and an integrator for a dynamic offset testbench in 0.18??m CMOS. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/207783

Chicago Manual of Style (16th Edition):

Khazane, Nitish Kumar. “Design of a comparator and an integrator for a dynamic offset testbench in 0.18??m CMOS.” 2019. Masters Thesis, California State University – Sacramento. Accessed October 14, 2019. http://hdl.handle.net/10211.3/207783.

MLA Handbook (7th Edition):

Khazane, Nitish Kumar. “Design of a comparator and an integrator for a dynamic offset testbench in 0.18??m CMOS.” 2019. Web. 14 Oct 2019.

Vancouver:

Khazane NK. Design of a comparator and an integrator for a dynamic offset testbench in 0.18??m CMOS. [Internet] [Masters thesis]. California State University – Sacramento; 2019. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10211.3/207783.

Council of Science Editors:

Khazane NK. Design of a comparator and an integrator for a dynamic offset testbench in 0.18??m CMOS. [Masters Thesis]. California State University – Sacramento; 2019. Available from: http://hdl.handle.net/10211.3/207783


California State University – Sacramento

11. Galvez, Angela Marie. Design of a fully-differential dual-slope analog-to-digital converter.

Degree: MS, Electrical and Electronic Engineering, 2019, California State University – Sacramento

 Dual-slope analog-to-digital converters (ADCs) are known for their high accuracy, but slow conversion times. The objective of this project was to design a 12-bit dual-slope… (more)

Subjects/Keywords: 12-bit synchronous counter; IC design; CMOS; ADC; OTA; CMFB; Folded-cascode; Circuit; Wide-swing bias; Common-mode feedback; Latching comparator; Integrator; Microelectronic design; Digital design; Analog design; Operational transconductance amplifier

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Galvez, A. M. (2019). Design of a fully-differential dual-slope analog-to-digital converter. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/210270

Chicago Manual of Style (16th Edition):

Galvez, Angela Marie. “Design of a fully-differential dual-slope analog-to-digital converter.” 2019. Masters Thesis, California State University – Sacramento. Accessed October 14, 2019. http://hdl.handle.net/10211.3/210270.

MLA Handbook (7th Edition):

Galvez, Angela Marie. “Design of a fully-differential dual-slope analog-to-digital converter.” 2019. Web. 14 Oct 2019.

Vancouver:

Galvez AM. Design of a fully-differential dual-slope analog-to-digital converter. [Internet] [Masters thesis]. California State University – Sacramento; 2019. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10211.3/210270.

Council of Science Editors:

Galvez AM. Design of a fully-differential dual-slope analog-to-digital converter. [Masters Thesis]. California State University – Sacramento; 2019. Available from: http://hdl.handle.net/10211.3/210270

12. Richardson, Heather Ren??e. Fault diagnosis and redesign of a 12-bit successive approximation analog-to-digital converter.

Degree: MS, Electrical and Electronic Engineering, 2013, California State University – Sacramento

 The objective of this project was to debug and redesign as needed an existing but broken 12-bit successive approximation analog-to-digital converter (SA ADC) for use… (more)

Subjects/Keywords: ADC; CMOS; Binary search algorithm; Analog design; Digital design

Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Richardson, H. R. (2013). Fault diagnosis and redesign of a 12-bit successive approximation analog-to-digital converter. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.9/2144

Chicago Manual of Style (16th Edition):

Richardson, Heather Ren??e. “Fault diagnosis and redesign of a 12-bit successive approximation analog-to-digital converter.” 2013. Masters Thesis, California State University – Sacramento. Accessed October 14, 2019. http://hdl.handle.net/10211.9/2144.

MLA Handbook (7th Edition):

Richardson, Heather Ren??e. “Fault diagnosis and redesign of a 12-bit successive approximation analog-to-digital converter.” 2013. Web. 14 Oct 2019.

Vancouver:

Richardson HR. Fault diagnosis and redesign of a 12-bit successive approximation analog-to-digital converter. [Internet] [Masters thesis]. California State University – Sacramento; 2013. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10211.9/2144.

Council of Science Editors:

Richardson HR. Fault diagnosis and redesign of a 12-bit successive approximation analog-to-digital converter. [Masters Thesis]. California State University – Sacramento; 2013. Available from: http://hdl.handle.net/10211.9/2144

13. Patel, Dhruval. Low noise amplifier for an electro-cardiogram integrated circuit analog front end.

Degree: MS, Electrical and Electronic Engineering, 2013, California State University – Sacramento

 An electrocardiogram is a measurement of the signal due to the electrical activity of the heart. This signal contains a great deal of useful diagnostic… (more)

Subjects/Keywords: IC for biomedical application; High CMRR circuit; To detect heart signal

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Patel, D. (2013). Low noise amplifier for an electro-cardiogram integrated circuit analog front end. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.9/2270

Chicago Manual of Style (16th Edition):

Patel, Dhruval. “Low noise amplifier for an electro-cardiogram integrated circuit analog front end.” 2013. Masters Thesis, California State University – Sacramento. Accessed October 14, 2019. http://hdl.handle.net/10211.9/2270.

MLA Handbook (7th Edition):

Patel, Dhruval. “Low noise amplifier for an electro-cardiogram integrated circuit analog front end.” 2013. Web. 14 Oct 2019.

Vancouver:

Patel D. Low noise amplifier for an electro-cardiogram integrated circuit analog front end. [Internet] [Masters thesis]. California State University – Sacramento; 2013. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10211.9/2270.

Council of Science Editors:

Patel D. Low noise amplifier for an electro-cardiogram integrated circuit analog front end. [Masters Thesis]. California State University – Sacramento; 2013. Available from: http://hdl.handle.net/10211.9/2270

14. Polavarapu, Sai Praneeth. Design of a fully-differential charge pump for an integrated dynamic offset test bench.

Degree: MS, Electrical and Electronic Engineering, 2014, California State University – Sacramento

 Comparators are one of the most important building blocks used in analog and mixed-signal integrated circuits. As the input offset voltage is the basic specification… (more)

Subjects/Keywords: Comparator; DOTB; Offset error

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Polavarapu, S. P. (2014). Design of a fully-differential charge pump for an integrated dynamic offset test bench. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/131276

Chicago Manual of Style (16th Edition):

Polavarapu, Sai Praneeth. “Design of a fully-differential charge pump for an integrated dynamic offset test bench.” 2014. Masters Thesis, California State University – Sacramento. Accessed October 14, 2019. http://hdl.handle.net/10211.3/131276.

MLA Handbook (7th Edition):

Polavarapu, Sai Praneeth. “Design of a fully-differential charge pump for an integrated dynamic offset test bench.” 2014. Web. 14 Oct 2019.

Vancouver:

Polavarapu SP. Design of a fully-differential charge pump for an integrated dynamic offset test bench. [Internet] [Masters thesis]. California State University – Sacramento; 2014. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10211.3/131276.

Council of Science Editors:

Polavarapu SP. Design of a fully-differential charge pump for an integrated dynamic offset test bench. [Masters Thesis]. California State University – Sacramento; 2014. Available from: http://hdl.handle.net/10211.3/131276

15. Wheeler, Ian. A fast settling reference generator with signal-dependent charge cancellation for an 8-bit 1.5 bit/stage pipelined ADC.

Degree: MS, Electrical and Electronic Engineering, 2013, California State University – Sacramento

 The reference voltage generator is an important circuitry block in pipelined analog-to-digital converters (ADCs). The function of the reference generator is to provide accurate reference… (more)

Subjects/Keywords: Pipelined ADC; Matlab; Voltage; Reference generator; Residue stage

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wheeler, I. (2013). A fast settling reference generator with signal-dependent charge cancellation for an 8-bit 1.5 bit/stage pipelined ADC. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.9/2289

Chicago Manual of Style (16th Edition):

Wheeler, Ian. “A fast settling reference generator with signal-dependent charge cancellation for an 8-bit 1.5 bit/stage pipelined ADC.” 2013. Masters Thesis, California State University – Sacramento. Accessed October 14, 2019. http://hdl.handle.net/10211.9/2289.

MLA Handbook (7th Edition):

Wheeler, Ian. “A fast settling reference generator with signal-dependent charge cancellation for an 8-bit 1.5 bit/stage pipelined ADC.” 2013. Web. 14 Oct 2019.

Vancouver:

Wheeler I. A fast settling reference generator with signal-dependent charge cancellation for an 8-bit 1.5 bit/stage pipelined ADC. [Internet] [Masters thesis]. California State University – Sacramento; 2013. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10211.9/2289.

Council of Science Editors:

Wheeler I. A fast settling reference generator with signal-dependent charge cancellation for an 8-bit 1.5 bit/stage pipelined ADC. [Masters Thesis]. California State University – Sacramento; 2013. Available from: http://hdl.handle.net/10211.9/2289

16. Grandhi, Sri Harsha. Design of a crystal oscillator for an all-digital phase-locked loop in 0.18um CMOS.

Degree: MS, Electrical and Electronic Engineering, 2017, California State University – Sacramento

 A phase-locked loop (PLL) is widely used on many integrated circuits to provide an accurate and stable clock. A PLL uses negative feedback around an… (more)

Subjects/Keywords: Crystal oscillator; Common source amplifier; Phase locked loop

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Grandhi, S. H. (2017). Design of a crystal oscillator for an all-digital phase-locked loop in 0.18um CMOS. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/191241

Chicago Manual of Style (16th Edition):

Grandhi, Sri Harsha. “Design of a crystal oscillator for an all-digital phase-locked loop in 0.18um CMOS.” 2017. Masters Thesis, California State University – Sacramento. Accessed October 14, 2019. http://hdl.handle.net/10211.3/191241.

MLA Handbook (7th Edition):

Grandhi, Sri Harsha. “Design of a crystal oscillator for an all-digital phase-locked loop in 0.18um CMOS.” 2017. Web. 14 Oct 2019.

Vancouver:

Grandhi SH. Design of a crystal oscillator for an all-digital phase-locked loop in 0.18um CMOS. [Internet] [Masters thesis]. California State University – Sacramento; 2017. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10211.3/191241.

Council of Science Editors:

Grandhi SH. Design of a crystal oscillator for an all-digital phase-locked loop in 0.18um CMOS. [Masters Thesis]. California State University – Sacramento; 2017. Available from: http://hdl.handle.net/10211.3/191241

.