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Title Low-cost testing of high-precision analog-to-digital converters
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Publication Date
Date Accessioned
Degree PhD
Discipline/Department Electrical and Computer Engineering
Degree Level doctoral
University/Publisher Georgia Tech
Abstract The advent of deep submicron technology has resulted in a new generation of highly integrated mixed-signal system-on-chips (SoCs) and system-on-packages (SoPs). As a result, the cost of electrical products has sharply declined, and their performance has greatly improved. However, a testing throughput still remains one of the major contribution factors to final cost of the electrical products. In addition, highly precise and robust test methods and equipment are needed to promise non-defective products to customers. Hence, the testing is a critical part of the manufacturing process in the semiconductor industry. Testing such highly integrated systems and devices requires high-performance and high-cost equipment. Analog-to-digital converters (A/D converters) are the largest volume mixed-signal circuits, and they play a key role in communication between the analog and digital domains in many mixed-signal systems. Due to the increasing complexity of the mixed-signal systems and the availability of the new generations of highly integrated systems, reliable and robust data conversion schemes are necessary for many mixed-signal designs. Many applications such as telecommunications, instrumentation, sensing, and data acquisition have demanded data converters that support ultra high-speed, wide-bandwidths, and high-precision with excellent dynamic performance and low-noise. However, as resolutions and speeds in the A/D converters increase, testing becomes much harder and more expensive. In this research work, low-cost test strategies to reduce overall test cost for high-precision A/D converters are developed. The testing of data converters can be classified as dynamic (or alternating current (AC)) performance test and static (or direct current (DC)) performance test [1]. In the dynamic specification test, a low-cost test stimulus is generated using an optimization algorithm to stimulate high-precision sigma-delta A/D converters under test. Dynamic specifications are accurately predicted in two different ways using concepts of an alternate-based test and a signature-based test. For this test purpose, the output pulse stream of a sigma-delta modulator is made observable and useful. This technique does not require spectrally pure input signals, so the test cost can be reduced compared to a conventional test method. In addition, two low-cost test strategies for static specification testing of high-resolution A/D converters are developed using a polynomial-fitting method. The cost of testing can be significantly reduced as a result of the measurement of fewer samples than a conventional histogram test. While one test strategy needs no expensive high-precision stimulus generator, which can reduce the test cost, the other test strategy finds the optimal set of test-measurement points for the maximum fault coverage, which can use minimum-code measurement as a production test solution. The theoretical concepts of the proposed test strategies are developed in software simulation and validated by hardware experiments using a…
Subjects/Keywords Sigma Delta ADC; Incremental ADC; High-resolution ADC testing; Analog-to-digital converters; Test; Data converters; Analog-to-digital converters; Testing
Contributors Chatterjee, Abhijit (Committee Chair); Anderson, David (Committee Member); Frazier, Bruno (Committee Member); Milor, Linda (Committee Member); Sitaraman, Suresh (Committee Member)
Country of Publication us
Record ID handle:1853/41170
Repository gatech
Date Indexed 2020-05-13
Issued Date 2011-07-05 00:00:00
Note [degree] Ph.D.; [advisor] Committee Chair: Chatterjee, Abhijit; Committee Member: Anderson, David; Committee Member: Frazier, Bruno; Committee Member: Milor, Linda; Committee Member: Sitaraman, Suresh;

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…SIMULATION RESULTS FOR VALIDATION 4.4. VALIDATION OF PROPOSED METHODOLOGY 4.4.1 Hardware Measurement Procedure 4.4.2 Experimental Result 150 150 152 4.5. 155 SUMMARY CHAPTER Ⅴ OPTIMAL LINEARITY TESTING OF SIGMA-DELTA INCREMENTAL A/D CONVERTERS USING…

…RESTRICTED CODE MEASUREMENTS 156 5.1. 158 PREVIOUS WORK 5.2. PROBLEM DEFINITION 5.2.1 Overview of Incremental A/D Converters 5.2.2 Problem Definition 160 161 162 5.3. PROPOSED METHODOLOGY 5.3.1 Behavioral Model of Incremental A/D Converters 5.3.2 Test…

…for Hardware Validation. 152 Figure 101. INL Measurements using Histogram Test and Proposed Test in Hardware Experiment. 154 Figure 102. Behavioral model of 24-bit 3rd order differential CIFF incremental A/D converter 165 Figure 103. Resolution…

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