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Title Analog signal processing on a reconfigurable platform
URL
Publication Date
Date Accessioned
Degree MS
Discipline/Department Electrical and Computer Engineering
Degree Level masters
University/Publisher Georgia Tech
Abstract The Cooperative Analog/Digital Signal Processing (CADSP) research group's approach to signal processing is to see what opportunities lie in adjusting the line between what is traditionally computed in digital and what can be done in analog. By allowing more computation to be done in analog, we can take advantage of its low power, continuous domain operation, and parallel capabilities. One setback keeping Analog Signal Processing (ASP) from achieving more wide-spread use, however, is its lack of programmability. The design cycle for a typical analog system often involves several iterations of the fabrication step, which is labor intensive, time consuming, and expensive. These costs in both time and money reduce the likelihood that engineers will consider an analog solution. With CADSP's development of a reconfigurable analog platform, a Field-Programmable Analog Array (FPAA), it has become much more practical for systems to incorporate processing in the analog domain. In this Thesis, I present an entire chain of tools that allow one to design simply at the system block level and then compile that design onto analog hardware. This tool chain uses the Simulink design environment and a custom library of blocks to create analog systems. I also present several of these ASP blocks, covering a broad range of functions from matrix computation to interfacing. In addition to these tools and blocks, the most recent FPAA architectures are discussed. These include the latest RASP general-purpose FPAAs as well as an adapted version geared toward high-speed applications.
Subjects/Keywords Field programmable analog array; FPAA; Field programmable gate array; MITE; Signal processing; Floating gate; Reconfigurable; Simulink; Programmable; Signal processing; Programmable logic devices; Field programmable gate arrays
Contributors Hasler, Paul (Committee Chair); Anderson, David (Committee Member); Ghovanloo, Maysam (Committee Member)
Country of Publication us
Record ID handle:1853/29623
Repository gatech
Date Indexed 2018-01-11
Issued Date 2009-07-08 00:00:00
Note [degree] M.S.; [advisor] Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Ghovanloo, Maysam;

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…43 Figure 32 Example Simulink VMM and WTA . . . . . . . . . . . . . . . . . . . . 44 Figure 33 Example .mdl file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 34 Example Spice code generated by sim2spice…

…46 Figure 35 Simulink libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 36 VMM properties box in sim2spice . . . . . . . . . . . . . . . . . . . . . 48 Figure 37 VMM implementation on FPAA…

…54 Figure 41 Header map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 42 Simulink block level design . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 43 Gaussian convolution…

…design onto analog hardware. This tool chain uses the Simulink design environment and a custom library of blocks to create analog systems. I also present several of these ASP blocks covering a broad range of functions from matrix computation to…

…sim2spice, a compiler and library that allows one to create analog systems in the Simulink environment. The compiler then turns this design into a Spice netlist, which I show can be targeted to the FPAA with the RASPER tool. I also describe the evaluation…

…for interfacing with the off-chip world (V-to-I, I-to-V). All of the blocks here have been built into the Simulink library discussed in Chapter 5, and all of the data is from the RASP 2.8a FPAA. 22 4.1.1 Winner-Take-All A simple yet…

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