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Author
Title Low Power Circuit Topologies for Digital-to-analog Converters with a Mm-wave Sampling Clock
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Publication Date
Date Available
Degree Level masters
University/Publisher University of Toronto
Abstract

This thesis describes the design of an 8-bit, 75GS/s, full-rate, low-power DAC in 55nm SiGe BiCMOS process. This is the highest sampling frequency (75GHz) broadband DAC to the best of the author's knowledge. It has an output swing of 1.2Vppd, which is sufficient to directly drive high performance VCSELs for short-reach data center communication links. The low power circuit topologies minimize the power consumption of the DAC to

M.A.S.

Subjects/Keywords DAC; 0544
Contributors Voinigescu, Sorin; Electrical and Computer Engineering
Country of Publication ca
Record ID handle:1807/69080
Repository toronto-thes
Date Retrieved
Date Indexed 2017-12-19

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