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Title Direct Synthesis of Netlists into Pre-routed FPGAs
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Publication Date
Date Available
Degree Level masters
University/Publisher University of Toronto
Abstract

This thesis introduces a new approach to compilation for FPGAs, which we call direct synthesis. We take a technology-mapped circuit netlist and directly map it into a pre-placed and routed FPGA overlay. Solving this problem may help to address the increasing portion of compile time that is attributed to placement and routing, and the tremendous amount of area and energy consumed by the highly flexible FPGA routing network. This thesis presents a direct synthesis algorithm and an algorithm for generating the pre-placed and routed FPGA overlays. Using the direct synthesis flow which we have designed, we can successfully map circuits less than 100 BLEs in size, after modest modi cations to the architecture of the FPGA overlay circuit. While we show that direct synthesis problem is challenging, further architectural modi cations are proposed which can allow the direct synthesis of larger circuits to succeed.

MAST

Subjects/Keywords FPGA; CAD; 0544
Contributors Rose, Jonathan; Electrical and Computer Engineering
Language en
Country of Publication ca
Record ID handle:1807/65549
Repository toronto-thes
Date Retrieved
Date Indexed 2017-12-19

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